Select the Right Components to Achieve 7.5-Digit Measurement Resolution

Instrument designers are challenged to achieve 7.5-digit resolution in high-performance data-acquisition systems, including digital multimeters (DMMs), weight scales, and seismic recorders. While multi-slope analog-to-digital converters (ADCs) are used for instruments with resolutions up to 6.5 digits, higher-resolution designs become more difficult due to several component specification limits and implementation challenges.

This article investigates how the specification limitations of precision analog components affect the obtainable instrument resolution. It then shows how 7.5-digit resolution can be achieved by carefully selecting successive approximation register (SAR) ADCs, high-precision voltage references, matched resistor networks, and zero-drift, low-noise amplifiers (LNAs) from Analog Devices.

Overview of a digitizer front-end

Precision digital instruments, such as DMMs, use a front-end that converts analog voltages into digital values. At the core of the front-end is the ADC (Figure 1). Most ADCs have a fixed input voltage range, so input signals must be amplified or attenuated to match it. This requires amplifiers and resistive attenuators. If a SAR ADC is used, a precision voltage reference source is also required. All these components must be selected with an eye toward low noise, low DC drift, and stable gain to maximize total system accuracy.

Figure 1: Shown is a block diagram of a digital front-end for a high-precision instrument, the core of which is an ADC. (Image source: ADI)

Selecting the right ADC

The first step in selecting an ADC is determining the required voltage resolution. With an instrument such as a DMM, it is usually specified in digits. A typical benchtop DMM would have a resolution of 6.5 digits. This means there are six decimal digits (0 through 9) plus a half-digit with values of 0 or 1. The unscaled readout range extends from +1,999,999 to -1,999,999 counts; a total commonly referred to as 4,000,000 count resolution.

The count for a binary device is simply two raised to the power of the number of bits. The number of digits and the number of bits can be plotted against one another (Figure 2), but they do not line up as integer multiples of each other.

Figure 2: Shown is a plot of the number of digits as a function of the number of bits calculated for both integer numbers of bits and the number of displayed digits. (Image source: Art Pini)

The common element in these calculations is the count, or number, of discrete values the device represents. The number of digits for a given count is simply log₁₀(count). The equivalent number of bits of a given count is log₁₀(count)/log₁₀(2) or digits/log₁₀(2). So, the count of 4,000,000 has an equivalent number of 21.932 bits.

A word on resolution and accuracy

Both the number of digits and the number of bits refer to the instrument’s voltage resolution. A 6.5-digit DMM on the 10 volt range can measure voltages from -10 V to +10 V with a count of 4,000,000. This means each step is 5 µV. This is the device's resolution, not the accuracy of the reading. Accuracy is a measurement of how close the measured value is to the true value. Many factors affect the measurement accuracy, including noise, offset error, gain error, and nonlinearity. All these sources of uncertainty arise in the instrument’s front-end components.

A typical 7.5-digit DMM on its 10 V range may have a 24 hour accuracy of 8 parts per million (ppm) of the measured value plus a 2 ppm uncertainty for the selected range (8+2). The rated long-term accuracy over 1 year can be ±(16+2) ppm. The ADC linearity needs to be in the range of 1.5 ppm, and the temperature error must be as low as 5 ±1 ppm per °C (ppm/°C).

Achieving this level of accuracy requires an understanding of the short and long-term error sources of the required components.

ADCs for high-precision digital front-ends

Figure 1 shows a typical digital front-end. It uses a 24-bit SAR ADC offering high resolution and moderate speed. SAR ADCs apply the input signal to a comparator. The other leg of the comparator receives a guess voltage from a digital-to-analog converter (DAC) driven by the SAR. The register has as many stages as the ADC’s number of bits. It starts by generating a guess voltage at one-half of the ADC voltage range. The comparator indicates that the input is either higher or lower than the reference-based guess voltage. If the guess value is less than the input, then a “1” is stored in the register bit; otherwise, a “0” is stored.

The register progresses through its states sequentially, lowering the guess voltage in binary steps. When the guess voltage is as close as possible to the input signal, the process stops, and the register contains the digital code equal to the input voltage. The ADC then issues a conversion-complete signal to read the binary code.

Note that the SAR ADC requires a precise and stable voltage reference to drive its DAC. For a multirange instrument, signal conditioning is also necessary to ensure the ADC input is as close to the ADC's full-scale range as possible without exceeding it.

The Analog Devices AD4630-24BBCZ-RL is a good choice for a 7.5-digit digital front-end. This dual-channel 24-bit SAR ADC operates at 2 megasamples per second (MSPS) and supports single-ended or differential operation. This ADC uses a 5 V reference voltage and features a typical linearity of 0.1 ppm (0.9 ppm max). It includes a block-averaging filter with a programmable decimation ratio that can significantly reduce noise and extend the dynamic range to 153 decibels (dB) at low output rates. Using block averaging, it achieves a 98 nV rms input-referred noise at a 60 hertz (Hz) output data rate, yielding a noise-limited effective resolution of 7.7 digits when referenced to full-scale input.

The voltage reference

Since the SAR ADC bases its output on comparisons of the input voltage with voltage levels derived from the voltage reference, it is highly dependent on the accuracy, stability, and noise level of that reference. To support stability, buried Zener reference technology achieves a very stable breakdown voltage by forming the device deep within the silicon substrate. This approach isolates it from surface contamination, reduces thermal effects, and makes it less sensitive to stress and humidity. Greater reference voltage stability can be achieved by including an internal heater, further minimizing the impact of ambient temperature changes.

The voltage reference used in Figure 1 is an ADR1001AEZ (Figure 3). This is an oven-controlled, buried Zener high-precision device that integrates the heater control, reference source, output buffer amplifier, and all associated signal conditioning in a single package, simplifying the design process and reducing the mounting footprint.

Figure 3: A functional block diagram of the ADR1001AEZ shows the heater control (left), reference source (center), and output buffer amplifier (right). (Image source: ADI)

The ADR1001AEZ’s nominal output voltage is 6.6 V, precision-trimmed to 5 V ±0.25%, with a rated output current of 10 mA. Its on-chip heater maintains a temperature coefficient of less than 0.2 ppm/°C. The 5 V output noise (0.1 to 10 Hz) is 0.13 ppm peak to peak (p-p), which calculates out to 0.65 mV p-p.

Amplifiers for 7.5-digit resolution

The input amplifier to the digital front-end, working with the matched resistor network, scales the input signal to match the ADC's specified input voltage. Designed to provide gain or attenuation as needed, this amplifier must have low-voltage drift and noise to achieve the desired 7.5-digit resolution. For this task, the chopper-stabilized ADA4523-1 is a good choice. This is a low-noise, zero-drift rail-to-rail amplifier with an offset voltage of ±4 µV (max) over an operating temperature range of -40°C to +125°C at 5 V. Low DC drift is ensured by a self-calibrating circuit that holds offset voltage drift with temperature below 0.01 µV per °C (µV/°C).

The ADA4523-1 has a common-mode rejection ratio of 160 dB (typical) and a noise level of 88 nV p-p (typical) from 0.1 to 10 Hz (Figure 4).

Figure 4: Shown is the noise waveform from 0.1 Hz to 10 Hz of a typical ADA4523-1 amplifier. (Image source: ADI)

Selecting the matched resistor network

A matched resistor network is a single package containing multiple resistors with matched electrical properties, such as resistance value, tolerance, and temperature coefficient. The absolute resistance is not critical, but the values are matched precisely and track over a wide temperature range, so the resistance ratios remain constant.

For instance, the LT5400BIMS8E-7 (Figure 5) is a four-resistor array that includes two 1.25 kΩ resistors and two 5 kΩ resistors, giving a 4:1 ratio and a gain of four. These resistors have a nominal resistance tolerance of ±15%, but the resistance ratios are matched to ±0.025%. Due to the common packaging, the 4:1 resistance ratio tracks over temperature, with a temperature coefficient of ±25 ppm/°C. The drift in the resistance ratios with temperature is ±0.2 ppm/°C.

Figure 5: Shown is a differential amplifier with a gain of four using the LT5400-7. (Image source: ADI)

Low temperature drift is essential because the amplifier gain is set by the ratios of R1 to R2 and R4 to R3. The resistor matching stabilizes the gain of each half of the amplifier and ensures that the gains of the two halves match, thereby maintaining a high common-mode rejection ratio (CMRR).

Conclusion

While instrument designers may be challenged to achieve 7.5-digit resolution in high-performance data-acquisition systems, it is possible to implement effectively with the right components. As shown, highly accurate, low nonlinearity, and low offset drift components from Analog Devices, such as the AD4630-24BBCZ-RL ADC, ADR1001AEZ precision voltage reference, ADA4523-1 amplifier, and LT5400BIMS8E-7 matched resistor network, simplify high-performance front-end design.