UltraScale, Ultrascale+ FPGAs Specification Datasheet by AMD

(I XILINX.
UltraScale and
UltraScale+ FPGAs
Packaging and Pinouts
Product Specification
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/20/2019 1.12
Chapter 1: Added an Important note about XQ devices with eutectic BGA balls on
page 17. Added the XQKU5P (FFRB676, SFRB784), XQKU15P (FFRA1156, FFRE1517),
XQVU3P (FFRC1517), XQVU7P (FLRA2104, FLRB2104), and XQVU11P (FLRC2104)
device/package combinations to Table 1-1, Table 1-2, Table 1-4, Table 1-6, Table 1-7,
Table 1-8, Table 1-8, and the appropriate figures in the Device Diagrams section. In
Table 1-5, corrected D[04 to 31] configuration data pins label and added note to
VCCAUX_IO. Revised the XCVU31P Bank Diagrams, XCVU33P Bank Diagrams,
XCVU35P Bank Diagrams, XCVU37P Bank Diagrams and to show the correct PCIE4 and
PCIE4C banks.Added the XCVU27P (FIGD2104, FSGA2577) and XCVU29P (FIGD2104,
FSGA2577) devices. This includes adding Table 1-3 and updates to Table 1-1,
Table 1-4, Table 1-5, Table 1-6, Table 1-7, Table 1-8, and the appropriate figures in the
Device Diagrams section. Updated the XCVU27P Bank Diagrams.
Chapter 2: Added an Important note about XQ devices with eutectic BGA balls on
page 173. In Table 2-1, added the XCVU27P (FIGD2104, FSGA2577) and XCVU29P
(FIGD2104, FSGA2577) devices and the XQKU5P (FFRB676, SFRB784), XQKU15P
(FFRA1156, FFRE1517), XQVU3P (FFRC1517), XQVU7P (FLRA2104, FLRB2104), and
XQVU11P (FLRC2104) device/package combinations.
Chapter 3: Added an Important note about XQ devices with eutectic BGA balls on
page 177. In Table 3-3, added the XQKU5P (FFRB676, SFRB784), XQKU15P (FFRA1156,
FFRE1517) device/package combinations. In Table 3-4, added the XCVU27P
(FIGD2104, FSGA2577), XCVU29P (FIGD2104, FSGA2577), XQVU3P (FFRC1517),
XQVU7P (FLRA2104, FLRB2104), and XQVU11P (FLRC2104) device/package
combinations.
Chapter 4: Added to the Summary information on XQ devices with eutectic BGA balls
and updated Table 4-1 with the packages specific to the XQ versions. In Table 4-1,
added the mechanical drawings for the XQKU5P (FFRB676, SFRB784), XQKU15P
(FFRA1156, FFRE1517), XQVU3P (FFRC1517), XQVU7P (FLRA2104, FLRB2104), and
XQVU11P (FLRC2104), and updated the FIGD2104 and FSGA2577 drawings to add the
XCVU27P and XCVU29P.
Chapter 5: Added Figure 5-5 and updated Table 5-1.
Chapter 6: Updated Table 6-1 with the FSGA2577 package and the XQ packages
(FFRB676, SFRB784, FFRA1156, FFRC1517, FFRE1517, FLRA2104, FLRB2104, FLRC2104).
Added an Important note about XQ devices with eutectic BGA balls on page 409.
Chapter 7: Updated the Sn/Pb reflow soldering guidelines including changes to
Figure 7-2. Added the FSGA2577 package and the XQ packages (FFRB676, SFRB784,
FFRA1156, FFRC1517, FFRE1517, FLRA2104, FLRB2104, FLRC2104) to Table 7-2 and
added Note 2. Updated the Conformal Coating section.
Chapter 9: Added an Important note about XQ devices with eutectic BGA balls on
page 419. Updated Table 9-1 with new data.
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01/08/2019 1.12
(cont’d)
Chapter 9: Although the same information was already in Note 2 at the end of
Table 9-1, it is repeated in an additional Important note on page 418. Added an
Important note about XQ devices with eutectic BGA balls on page 419. In Table 9-1,
revised FFVE900 values, added the XCVU27P (FIGD2104, FSGA2577), XCVU29P
(FIGD2104, FSGA2577), XQKU5P (FFRB676, SFRB784), XQKU15P (FFRA1156,
FFRE1517), XQVU3P (FFRC1517), XQVU7P (FLRA2104, FLRB2104), and XQVU11P
(FLRC2104) device/package data. Also added data to the XCVU31P, XCVU33P,
XCVU35P, and XCVU37P devices.
Chapter 10: Updated applied pressure range in Recommended note on page 428 to
20–50 psi.
8/23/2018 1.11
Chapter 1: In Table 1-5, updated the GC or HDGC direction to Input/Output. In
Table 1-8, updated the XCVU160-FLGB2104 map to change the 233 quad location and
added the 233 and 133 quads to XCVU160-FLGC2104 map.
Chapter 2: In Table 2-1, updated the XCVU31P-FSVH1924,
XCVU33P/XCVU35P-FSVH2104, XCVU13P-FSGA2577, and
XCVU35P/XCVU37P-FSVH2892 to production and revised the links.
Chapter 3: In Table 3-4, updated the XCVU31P-FSVH1924,
XCVU33P/XCVU35P-FSVH2104, XCVU13P-FSGA2577, and
XCVU35P/XCVU37P-FSVH2892 to production.
Chapter 4: In Table 4-1, updated the mechanical drawing status for
XCVU31P-FSVH1924, XCVU33P/XCVU35P-FSVH2104, XCVU13P-FSGA2577, and
XCVU35P/XCVU37P-FSVH2892 to production.
Chapter 9: In Table 9-1, added the XCVU31P-FSVH1924,
XCVU33P/XCVU35P-FSVH2104, XCVU13P-FSGA2577, and
XCVU35P/XCVU37P-FSVH2892 devices.
4/09/2018 1.10
Chapter 1: Updated the Bank Locations of Dedicated and Multi-Function Pins section.
Added the XCVU13P-FSGA2577 device/package combination and the XCVU31P,
XCVU33P, XCVU35P, and XCVU37P devices. This includes updates to Table 1-1,
Table 1-2, Table 1-4, Table 1-5, Table 1-6, Table 1-7, and Table 1-8. Added
Figure 1-122, Figure 1-123, Figure 1-124, Figure 1-125, Figure 1-126, Figure 1-127,
Figure 1-128, Figure 1-129, and Figure 1-130.
Chapter 2: Added the XCVU13P-FSGA2577 device/package combination and the
XCVU31P, XCVU33P, XCVU35P, and XCVU37P devices to Table 2-1.
Chapter 3: Added the XCVU13P-FSGA2577 device/package combination and the
XCVU31P, XCVU33P, XCVU35P, and XCVU37P devices to Table 3-4.
Chapter 4: Added the XCVU13P-FSGA2577 device/package combination and the
XCVU31P, XCVU33P, XCVU35P, and XCVU37P devices to Table 4-1.
Chapter 6: Added the FSVH1924, FSVH2104, FSGA2577, and FSVH2892 packages to
Table 6-1.
Chapter 7: Added the FSVH1924, FSVH2104, FSGA2577, and FSVH2892 packages to
Table 7-2.
Chapter 9: Added the XCVU13P-FSGA2577 device/package combination and the
XCVU31P, XCVU33P, XCVU35P, and XCVU37P devices to Table 9-1.
Chapter 12: Added a link to Mechanical and Thermal Design Guidelines for Lidless
Flip-Chip Packages Application Note (XAPP1301).
Date Version Revision
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12/15/2017 1.9
Chapter 2, Package Files: Updated links and package designations in Table 2-1.
Chapter 3, Device Diagrams: Updated package designations in Table 3-3 and
Table 3-4. Added Figure 3-85, Figure 3-86, Figure 3-133, and Figure 3-134.
Chapter 4, Mechanical Drawings: Updated package designations in Table 4-1. Added
Figure 4-45. Updated Figure 4-46 (the dimensions inside the Top View changed).
Added Figure 4-47.
Chapter 9, Thermal Specifications: Added Note 2 to Table 9-1.
Chapter 10, Thermal Management Strategy updated the System Level Heat Sink
Solutions and Heat Sink Removal sections. Added the Measurement Debug section.
Chapter 12, Mechanical and Thermal Design Guidelines for Lidless Flip-chip Packages
was added to user guide.
8/25/2017 1.8
Chapter 1, Packaging Overview: In Table 1-4, corrected (increased) the available HP
I/O pin counts for the XCKU095-FFVB2104. In Table 1-5, revised the VCCINT_IO
description. In Table 1-7, updated the XCKU5P-FFVB676 mapping and added the
XCKU095-FFVC1517. Added at Tip on page 57. Updated bank designations in
Figure 1-8, Figure 1-13, Figure 1-15, Figure 1-28, Figure 1-32, Figure 1-35, all
XCVU080 Bank Diagrams, XCVU095 Bank Diagrams, Figure 1-52, XCKU9P Bank
Diagrams, Figure 1-79, XCKU13P Bank Diagrams, and XCKU15P and XQKU15P Bank
Diagrams.
Chapter 2, Package Files: Updated links and package designations in Table 2-1.
Chapter 3, Device Diagrams: Updated package designations in Table 3-3 and
Table 3-4. Added Figure 3-91 and Figure 3-92. Updated Figure 3-95 and Figure 3-96.
Added Figure 3-113, Figure 3-114, Figure 3-127, Figure 3-128, Figure 3-135, and
Figure 3-136.
Chapter 4, Mechanical Drawings: Updated package designations in Table 4-1.
Chapter 5, Package Marking: Updated the Top Marks for Figure 5-1 and Figure 5-2 to
show the date code and lot number on the bar code version. Added package types to
Table 5-1.
Chapter 6, Packing and Shipping: Added package types to Table 6-1.
Chapter 7, Soldering Guidelines: Added guidelines for lidless packages with stiffener
ring and updated Table 7-1. Revised the Mass Reflow from 250°C to 245°C on a
number of package types in Table 7-2. Revised Figure 7-2 with new guidelines.
Chapter 9, Thermal Specifications: Added package types to Table 9-1.
Added Documentation Navigator and Design Hubs in Appendix A.
4/27/2017 1.7.1 Replaced the FFVE1760 (XCKU15P) figures in Chapter 3, Device Diagrams.
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4/26/2017 1.7
Added the XQKU040, XQKU060, XQKU095, and XQKU115 devices where applicable.
Added the RBA676, RFA1156, RLD1517, and RLF1924 packages where applicable.
Chapter 1, Packaging Overview: Updated Note 5 in Table 1-5. Revised Table 1-6,
Table 1-7, and Table 1-8. Added notes and recommendations to the SYSMON,
Configuration, PCIe, Interlaken, and 100GE Integrated Blocks section. Revised many of
the Device Diagrams.
Chapter 2, Package Files: Updated the links. Added and updated package files for
Virtex UltraScale+ and Kintex UltraScale+ FPGAs.
Chapter 3, Device Diagrams: Added and updated diagrams for Virtex UltraScale+ and
Kintex UltraScale+ FPGAs.
Chapter 4, Mechanical Drawings: Added and replaced many of the mechanical
drawings for the Virtex UltraScale+ and Kintex UltraScale+ devices.
Chapter 5, Package Marking: Updated the Virtex UltraScale and Kintex UltraScale
device top-mark diagrams to include the bar code top-mark diagrams. Added the
Virtex UltraScale+ and Kintex UltraScale+ device top-mark diagrams.
Chapter 7, Soldering Guidelines: Added the Sn/Pb Reflow Soldering section. Updated
the Conformal Coating recommendation.
4/25/2016 1.6
Added Kintex UltraScale+ and Virtex UltraScale+ FPGAs.
Chapter 1, Packaging Overview: Revised GC or HDGC description and added
RSVDGND to Table 1-5. Revised the Die Level Bank Numbering Overview section
including adding and replacing figures and removing tables.
Chapter 2, Package Files: Updated the links.
Chapter 3, Device Diagrams: Corrected Figure 3-7 and Figure 3-8.
Chapter 4, Mechanical Drawings: Updated top-lid flat-surface dimension from 31.05
sq. max. to 29.70sq. max. in Figure 4-12 (FFVA1156). Updated the top-lid flat-surface
dimension from 29.10 max. to 29.70 sq. max. in Figure 4-13 (FFVA1156) and
Figure 4-14 (FFVA1156). Added top-lid flat-surface dimension 33.10 in Figure 4-18
(FFVA1517). Update dimension A nominal from 3.61 to 3.51 in Figure 4-24 (FFVB1760).
Updated Figure 4-38 (FLGB2104) to add a missing decimal point. Updated Figure 4-41
(FFVC2104) with the correct package dimensions.
Chapter 7, Soldering Guidelines: Updated the device list in Table 7-2.
Chapter 10, Thermal Management Strategy: Added a new recommendation and
Figure 10-2.
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10/19/2015 1.5
Added the XCKU025 and the XCKU095 in the FFVA1156 package.
In Chapter 1, Packaging Overview, updated SFVA784 package in Table 1-7, Table 1-9
and Table 1-10. Updated the FLVB1760 rows in Table 1-8.Added an important note in
Footprint Compatibility between Packages. Replaced Figure 1-13.
In Chapter 3, Device Diagrams, replaced the SFVA784 drawings in Figure 3-3 and
Figure 3-4 with updated pinouts. Updated Figure 3-43 and Figure 3-44.
In Chapter 4, Mechanical Drawings, updated Figure 4-6 (SFVA784) and Figure 4-13
(FFVA1156), and corrected the heading for Figure 4-38 to include FLGB2104 and
FLGC2104. Replaced Figure 4-38, Figure 4-50, Figure 4-51, and Figure 4-55.
In Chapter 8, Recommended PCB Design Rules for BGA Packages, updated Table 8-1.
In Chapter 9, Thermal Specifications, added thermal resistance data to Table 9-1.
Substantial edits to the Introduction, Thermal Resistance Data, and Support for
Thermal Models sections. Added a new recommendation on page 423.
In Chapter 10, Thermal Management Strategy, removed Design and Silicon section,
updated the Flip-Chip Packages and System Level Heat Sink Solutions sections,
removed the Thermal Management Options section, added more information to Types
of TIM, removed the Comparing the Types of Interface Materials section, added the
Applied Pressure from Heat Sink to the Package via Thermal Interface Materials
section, and removed the Package Pressure Handling Capacity section.
In Chapter 11, Heat Sink Guidelines for Bare-die Flip-Chip Packages, removed the
Package Loading Specifications section.
5/13/2015 1.4
Added the XCKU035 and XCKU040 devices in the SFVA784 package throughout this
guide. Added XCKU085 and XCKU095 updates throughout including Table 1-7,
Table 1-8, and Table 3-1.
In Chapter 1, Packaging Overview, in Table 1-5 changed D01_DIN_0, D02_0, and
D03_0 to bidirectional. Updated Figure 1-9 to Figure 1-14 with new GTH Quad
placements.
In Chapter 4, Mechanical Drawings, updated Table 4-1 and the specific mechanical
drawings of the SFVA784, FBVA900, FLVA1517, FLVD1517, FLVB1760, FLVA2104,
FLVB2104, FLGB2104, FFVC2104, FLVC2104, and FLGC2104.
3/23/2015 1.3
Updated the Differences from Previous Generations section. In Table 1-5, updated
VCCINT and VCCAUX descriptions and the Multi-gigabit Serial Transceiver Pins
(GTHE3 and GTYE3) section. Updated the Die Level Bank Numbering Overview section
including adding the SYSMON, Configuration, PCIe, Interlaken, and 100GE Integrated
Blocks section. Replaced Figure 1-4 through Figure 1-62 and updated information in
Table 1-9 through Table 1-21. Removed the XCKU075 and XCKU100 throughout.
Added the XCKU085 and XCKU095 where data is available.
In Chapter 2, Package Files, updated the links to the ASCII files.
In Chapter 3, Device Diagrams, updated Figure 3-13, Figure 3-14 and added
numerous new figures.
In Chapter 4, Mechanical Drawings, removed the FBVA900 mechanical drawings and
updated Figure 4-21.
In Chapter 5, Package Marking, added to the 2nd line description in Table 5-1.
Revised Table 9-1.
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1/12/2015 1.2
Revised the device/package combinations per the update to the UltraScale
Architecture and Product Overview (DS890) [Ref 1]. This revision was throughout the
guide in every table with package listings, Package Files, Device Diagrams, and
Mechanical Drawings.
Updated Table 1-16, Table 1-17, and replaced Table 1-18, Table 1-19, and Table 1-20.
Updated descriptions in Table 5-1.
Updated descriptions in Table 7-2.
Revised and added to Table 9-1.
Added references to Appendix A.
9/04/2014 1.1
Added a discussion on ULA materials on page 15. In Differences from Previous
Generations, updated the differential clock pin pairs and the VREF pin discussion.
Added the Virtex UltraScale FPGA packages to Table 1-1. Also added the Virtex
UltraScale devices to Table 1-2, Table 1-4, and Table 1-6. Updated PERSTN[0 to 1],
DOUT_CSO_B, FWE_FCS2_B, RS[0 to 1], RDWR_FCS_B_0, D00_MOSI_0, D01_DIN_0, and
VREF_[bank number] descriptions. Updated Multi-gigabit Serial Transceiver Pins
(GTHE3 and GTYE3) pin names. Added Table 1-7 and Table 1-8. Revised the T[0 to 3][U
or L] and N[0 to 12] descriptions in the User I/O Pins section of Table 1-5: Pin
Definitions. Updated the figures and added tables to the Die Level Bank Numbering
Overview section.
Changed the TXT and CSV files associated with Table 2-1. Also updated Table 2-1 with
additional device/packages and links.
In Chapter 3, Device Diagrams, replaced or added figures.
Added Figure 4-1 through Figure 4-4. Replaced Figure 4-12 and Figure 4-13. Added
Figure 4-18 through Figure 4-13.
Added the Virtex UltraScale device package marking template to Chapter 5.
Clarified the maximum reflow soldering guidelines on page 410 and updated
Table 7-2: Peak Package Reflow Body Temperature(1). Replaced Figure 7-2. Removed
the Sn/Pb Reflow Soldering section from Chapter 7, Soldering Guidelines. Added Post
Reflow/Cleaning/Washing and Conformal Coating sections.
Updated Thermal Management Options and Figure 10-2. Added Heat Sink Removal
and Package Pressure Handling Capacity to Chapter 10.
Updated the links to references [Ref 21], [Ref 22], and [Ref 23] in Appendix A. Added
further references.
12/10/2013 1.0 Initial Xilinx release.
Date Version Revision
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Packaging Overview
Introduction to the UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Introduction to UltraScale and UltraScale+ FPGAs Packaging and Pinouts . . . . . . . . . . . . . . . . . . . 15
Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device/Package Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Gigabit Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
User I/O Pins by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Footprint Compatibility between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 2: Package Files
About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Package Specifications Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Chapter 3: Device Diagrams
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
FBVA676 Package–XCKU035 and XCKU040 and RBA676 Package–XQKU040 . . . . . . . . . . . . . . . . 183
SFVA784 (XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
FBVA900 (XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
FFVA1156 (XCKU025). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
FFVA1156 (XCKU035). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
FFVA1156 (XCKU040) and RFA1156 (XQKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
FFVA1156 (XCKU060) and RFA1156 (XQKU060) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
FFVA1156 (XCKU095) and RFA1156 (XQKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
FFVA1517 (XCKU060). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
FLVA1517 (XCKU085 and XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
FFVC1517 (XCKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
FLVD1517 (XCKU115) and RLD1517 (XQKU115). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
FFVB1760 (XCKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
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FLVB1760 (XCKU085) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
FLVB1760 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
FLVD1924 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
FLVF1924 (XCKU085) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
FLVF1924 (XCKU115) and RLF1924 (XQKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
FLVA2104 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
FFVB2104 (XCKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
FLVB2104 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
FFVC1517 (XCVU065) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
FFVC1517 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
FFVD1517 (XCVU080 and XCVU095). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
FLVD1517 (XCVU125). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
FFVB1760 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
FLVB1760 (XCVU125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
FFVA2104 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
FLVA2104 (XCVU125). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
FFVB2104 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
FLVB2104 (XCVU125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
FLGB2104 (XCVU160 and XCVU190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
FFVC2104 (XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
FLVC2104 (XCVU125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
FLGC2104 (XCVU160 and XCVU190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
FLGB2377 (XCVU440). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
FLGA2577 (XCVU190). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
FLGA2892 (XCVU440). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
FFVA676 (XCKU3P and XCKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
FFVB676 (XCKU3P and XCKU5P) and FFRB676 (XQKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
SFVB784 (XCKU3P and XCKU5P) and SFRB784 (XQKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
FFVD900 (XCKU3P and XCKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
FFVD900 (XCKU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
FFVE900 (XCKU9P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
FFVE900 (XCKU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
FFVA1156 (XCKU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
FFVA1156 (XCKU15P) and FFRA1156 (XQKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
FFVE1517 (XCKU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
FFVE1517 (XCKU15P) and FFRE1517 (XQKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
FFVA1760 (XCKU15P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
FFVE1760 (XCKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
FFVC1517 (XCVU3P) and FFRC1517 (XQVU3P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
FLGF1924 (XCVU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
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FSVH1924 (XCVU31P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
FLVA2104 (XCVU5P and XCVU7P) and FLRA2104 (XQVU7P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
FLGA2104 (XCVU9P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
FHGA2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
FLVB2104 (XCVU5P and XCVU7P) and FLRB2104 (XQVU7P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
FLGB2104 (XCVU9P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
FLGB2104 (XCVU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
FHGB2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
FLVC2104 (XCVU5P and XCVU7P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
FLGC2104 (XCVU9P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
FLGC2104 (XCVU11P) and FLRC2104 (XQVU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
FHGC2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
FSGD2104 (XCVU9P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
FSGD2104 (XCVU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
FIGD2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
FIGD2104 (XCVU27P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
FIGD2104 (XCVU29P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
FSVH2104 (XCVU33P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
FSVH2104 (XCVU35P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
FLGA2577 (XCVU9P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
FLGA2577 (XCVU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
FLGA2577 and FSGA2577 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
FSGA2577 (XCVU27P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
FSGA2577 (XCVU29P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
FSVH2892 (XCVU35P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
FSVH2892 (XCVU37P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Chapter 4: Mechanical Drawings
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
FBVA676 Bare-die Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
FFVA676 and FFVB676 Flip-Chip, Fine-Pitch BGA
(XCKU3P and XCKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
FFRB676 Ruggedized Flip-Chip, Fine-Pitch BGA (XQKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
RBA676 Ruggedized Flip-Chip, Fine-Pitch BGA (XQKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
SFVA784 Flip-Chip, Chip-Scale (0.8 mm) BGA
(XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
SFVB784 Flip-Chip, Super-Fine Pitch (0.8 mm) BGA
(XCKU3P and XCKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
SFRB784 Ruggedized Flip-Chip, Super Fine-Pitch BGA (XQKU5P). . . . . . . . . . . . . . . . . . . . . . . . . . 352
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FBVA900 Bare-die Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
FFVD900 (XCKU3P, XCKU5P, and XCKU11P) and FFVE900 (XCKU9P and XCKU13P) . . . . . . . . . . . 355
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU025, XCKU035, and XCKU040). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU060, XCKU095, and XCKU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
FFVA1156 Flip-Chip, Fine-Pitch BGA (XCKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
FFRA1156 Ruggedized Flip-Chip, Fine-Pitch BGA (XQKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
RFA1156 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
RFA1156 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU060 and XQKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
FFVA1517, FFVC1517, and FFVD1517 Flip-Chip, Fine-Pitch BGA (XCKU060, XCKU095, XCVU065,
XCVU080, XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
FFVC1517 (XCVU3P) and FFVE1517 (XCKU11P and XCKU15P) Flip-Chip, Fine-Pitch BGA . . . . . . . 363
FFRC1517 (XQVU3P) and FFRE1517 (XQKU15P) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . 364
FLVA1517 (XCKU085 and XCKU115) and FLVD1517 (XCKU115 and XCVU125) Flip-Chip, Fine-Pitch
BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
RLD1517 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
FFVA1760 Flip-Chip, Fine-Pitch BGA (XCKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
FFVB1760 Flip-Chip, Fine-Pitch BGA (XCKU095, XCVU080, and XCVU095) . . . . . . . . . . . . . . . . . . 368
FLVB1760 Flip-Chip, Fine-Pitch BGA (XCKU085, XCKU115, and XCVU125) . . . . . . . . . . . . . . . . . . 369
FFVE1760 Flip-Chip, Fine-Pitch BGA (XCKU15P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
FLVD1924 (XCKU115) and FLVF1924 (XCKU085 and XCKU115) Flip-Chip, Fine-Pitch BGA . . . . . . 371
FLGF1924 (XCVU11P) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
RLF1924 (XQKU115) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
FSVH1924 (XCVU31P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 374
FFVA2104 (XCVU080 and XCVU095) and FFVB2104 (XCKU095, XCVU080, and XCVU095) Flip-Chip,
Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
FHGA2104 (XCVU13P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
FHGB2104 (XCVU13P) and FHGC2104 (XCVU13P) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . 377
FLVA2104 (XCKU115 and XCVU125) and FLVB2104 (XCKU115 and XCVU125) Flip-Chip, Fine-Pitch
BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
FLVA2104 (XCVU5P and XCVU7P) and FLVB2104 (XCVU5P and XCVU7P) Flip-Chip, Fine-Pitch BGA. .
379
FLRA2104 (XQVU7P) and FLRB2104 (XQVU7P) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . . 380
FLGA2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
FLGB2104 (XCVU160 and XCVU190) and FLGC2104 (XCVU160 and XCVU190) Flip-Chip, Fine-Pitch
BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
FLGB2104 (XCVU9P and XCVU11P) and
FLGC2104 (XCVU11P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
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FLRC2104 (XQVU11P) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
FFVC2104 (XCVU095) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
FLGC2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
FLVC2104 (XCVU125) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
FLVC2104 (XCVU5P and XCVU7P) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
FIGD2104 (XCVU13P, XCVU27P, and XCVU29P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . 389
FSGD2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
FSGD2104 (XCVU11P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
FSVH2104 (XCVU33P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 392
FSVH2104 (XCVU35P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 393
FLGB2377 Flip-Chip, Fine-Pitch BGA (XCVU440) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU9P and XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
FSGA2577 Flip-Chip, Fine-Pitch BGA
(XCVU13P, XCVU27P, and XCVU29P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
FLGA2892 Flip-Chip, Fine-Pitch BGA (XCVU440) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
FSVH2892 (XCVU35P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 400
FSVH2892 (XCVU37P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 401
Chapter 5: Package Marking
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Chapter 6: Packing and Shipping
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Chapter 7: Soldering Guidelines
Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Chapter 8: Recommended PCB Design Rules for BGA Packages
BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Chapter 9: Thermal Specifications
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Support for Thermal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Chapter 10: Thermal Management Strategy
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Thermal Interface Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Heat Sink Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
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Measurement Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Chapter 11: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Heat Sink Attachments for Bare-die FB Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Chapter 12: Mechanical and Thermal Design Guidelines for Lidless Flip-chip
Packages
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Lidless Flip-Chip Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Appendix A: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
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Chapter 1
Packaging Overview
Introduction to the UltraScale Architecture
The Xilinx® UltraScale™ architecture is the first ASIC-class architecture to enable
multi-hundred gigabit-per-second levels of system performance with smart processing,
while efficiently routing and processing data on-chip. UltraScale architecture-based devices
address a vast spectrum of high-bandwidth, high-utilization system requirements by using
industry-leading technical innovations, including next-generation routing, ASIC-like
clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new power
reduction features. The devices share many building blocks, providing scalability across
process nodes and product families to leverage system-level investment across platforms.
Virtex® UltraScale+™ devices provide the highest performance and integration capabilities
in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as
well as the highest on-chip memory density. As the industry's most capable FPGA family,
the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and
data center and fully integrated radar/early-warning systems.
Virtex UltraScale devices provide the greatest performance and integration at 20 nm,
including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at
the 20 nm process node, this family is ideal for applications including 400G networking,
large scale ASIC prototyping, and emulation.
Kintex® UltraScale+ devices provide the best price/performance/watt balance in a FinFET
node, delivering the most cost-effective solution for high-end capabilities, including
transceiver and memory interface line rates as well as 100G connectivity cores. Our newest
mid-range family is ideal for both packet processing and DSP-intensive functions and is well
suited for applications including wireless MIMO technology, Nx100G networking, and data
center.
Kintex UltraScale devices provide the best price/performance/watt at 20 nm and include
the highest signal processing bandwidth in a mid-range device, next-generation
transceivers, and low-cost packaging for an optimum blend of capability and
cost-effectiveness. The family is ideal for packet processing in 100G networking and data
centers applications as well as DSP-intensive processing needed in next-generation medical
imaging, 8k4k video, and heterogeneous wireless infrastructure.
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Chapter 1: Packaging Overview
Zynq® UltraScale+ MPSoC devices provide 64-bit processor scalability while combining
real-time control with soft and hard engines for graphics, video, waveform, and packet
processing. Integrating an Arm®-based system for advanced analytics and on-chip
programmable logic for task acceleration creates unlimited possibilities for applications
including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.
This packaging and pinout specification user guide is part of the UltraScale Architecture
documentation suite available at: www.xilinx.com/ultrascale.
Introduction to UltraScale and UltraScale+ FPGAs
Packaging and Pinouts
This section describes the packages and pinouts for the UltraScale architecture-based
FPGAs in various organic flip-chip 0.8 mm and 1.0 mm pitch BGA packages.
• Kintex UltraScale and Kintex UltraScale+ devices are offered in low-cost, space-saving
flip-chip and bare-die flip-chip packages that are optimally designed for high
performance-to-price ratio.
• Virtex UltraScale and Virtex UltraScale+ devices are offered exclusively in high
performance flip-chip BGA packages that are optimally designed for highest system
capacity, bandwidth and signal performance. Package inductance is minimized as a
result of optimal placement and even distribution as well as an increased number of
power and GND pins.
• Zynq UltraScale+ MPSoCs are further described in the Zynq UltraScale+ MPSoC
Packaging and Pinouts User Guide (UG1075) [Ref 4].
IMPORTANT: Many of the standard packages for commercial (XC) devices are lead-free (signified by an
additional V in the package name). All of the UltraScale or UltraScale+ devices supported in a
particular package are footprint compatible. Each device is split into I/O banks to allow for flexibility in
the choice of I/O standards. See the UltraScale Architecture SelectIO Resources User Guide (UG571)
[Ref 5].
UltraScale and UltraScale+ device’s flip-chip assembly materials are manufactured using
ultra-low alpha (ULA) materials defined as <0.002 cph/cm2 or materials that emit less than
0.002 alpha-particles per square centimeter per hour.
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Chapter 1: Packaging Overview
Differences from Previous Generations
The packaging and pinout specifications for UltraScale architecture-based FPGAs differ
from past generations, including the 7 series devices. These details are outlined in this
section.
• All packages are constructed on organic laminate substrates.
• Many of the package and die components, including flip-chip solder bumps, are
lead-free. The FLGx devices have lead in their bumps.
• Package names contain a single-character alphabetic designator followed by the exact
number of pins found on the package.
• VCCAUX_IO pins are not divided into bank groups. VCCAUX_IO must be connected to
VCCAUX at the board level.
• Internal logic is separated from I/O logic by the addition of the VCCINT_IO power pins.
VCCINT_IO must be connected to VCCINT at the board level.
• Groups of gigabit serial transceiver (GT) power pins are separated by column for each
column of GT Quads/Duals.
• Standard I/O banks each have a total of 52 SelectIO™ pins, optionally configurable as
up to 24 differential pairs.
• Each bank has one dedicated VREF pin. These pins cannot be used as user I/Os.
• Four differential clock pin pairs per bank (two per 26-pin bank) consist of a single type
of global clock (GC) input.
• Four memory byte groups per I/O bank (two per 26-pin bank) are each separated into
an upper and a lower memory byte group.
• All configuration pins are located in bank 0 and bank 65.
• A POR_OVERRIDE pin is used to override the default power-on-reset delay. See
Table 1-5.
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Chapter 1: Packaging Overview
Device/Package Combinations
Table 1-1 shows the size and BGA pitch of the UltraScale and UltraScale+ device packages.
The devices with stacked-silicon interconnect (SSI) technology are labeled.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC, and the third digit in the package name is Q (for example: FFQA1156).
Table 1-1: Package Specifications
Packages(1) Description Package Specifications
Package Type Pitch (mm) Size (mm)
FBVA676 Bare-die, flip-chip, fine-pitch
BGA
1.0 27 x 27
FFVA676 Flip-chip, fine-pitch
FFVB676
FFRB676 Ruggedized, flip-chip, fine-pitch
RBA676
SFVA784 Flip-chip, super-fine-pitch 0.8 23 x 23SFVB784
SFRB784 Ruggedized, flip-chip, super-fine pitch
FBVA900 Bare-die, flip-chip, fine-pitch
1.0
31 x 31FFVD900 Flip-chip, fine-pitch
FFVE900
FFVA1156 Flip-chip, fine-pitch
35 x 35FFRA1156 Ruggedized, flip-chip, fine-pitch
RFA1156
FFVA1517
Flip-chip, fine-pitch
40 x 40
FFVC1517
FFVD1517
FFVE1517
FFRC1517 Ruggedized, flip-chip, fine-pitch
FFRE1517
RLD1517 Ruggedized, SSI, flip-chip, fine-pitch
FLVA1517 SSI, flip-chip, fine-pitch
FLVD1517
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Chapter 1: Packaging Overview
FFVA1760
Flip-chip, fine-pitch
BGA 1.0
42.5 x 42.5
FFVB1760
FFVE1760
FLVB1760
SSI, flip-chip, fine-pitch
FLGF1924
45 x 45
FLVD1924
FLVF1924
FSVH1924 SSI, flip-chip, fine-pitch, lidless with stiffener ring
RLF1924 Ruggedized, SSI, flip-chip, fine-pitch
FFVA2104
Flip-chip, fine-pitch
47.5 x 47.5
FFVB2104
FFVC2104
FLVA2104
SSI, flip-chip, fine-pitchFLVB2104
FLVC2104
FLGA2104
SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 47.5 x 47.5FLGB2104
FLGC2104
FLRA2104
Ruggedized, SSI, flip-chip, fine-pitch 47.5 x 47.5FLRB2104
FLRC2104
FSGD2104 SSI, flip-chip, fine-pitch, lidless with stiffener ring,
RoHS 6/6 with exemption 15 47.5 x 47.5
FSVH2104 SSI, flip-chip, fine-pitch, lidless with stiffener ring 47.5 x 47.5
FHGA2104(2)
SSI, flip-chip, fine-pitch, overhang, RoHS 6/6 with
exemption 15 52.5 x 52.5FHGB2104(2)
FHGC2104(2)
FIGD2104(2) SSI, flip-chip, fine-pitch, overhang, lidless with
stiffener ring, RoHS 6/6 with exemption 15 52.5 x 52.5
FLGB2377 SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 50 x 50
FLGA2577 SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 52.5 x 52.5
FSGA2577 SSI, flip-chip, fine-pitch, lidless with stiffener ring,
RoHS 6/6 with exemption 15 52.5 x 52.5
Table 1-1: Package Specifications (Cont’d)
Packages(1) Description Package Specifications
Package Type Pitch (mm) Size (mm)
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Chapter 1: Packaging Overview
Gigabit Transceiver Channels by Device/Package
Table 1-2 lists the quantity of gigabit transceiver channels for the UltraScale and
UltraScale+ devices. In all devices, a gigabit transceiver channel is one set of MGTRXP,
MGTRXN, MGTTXP, and MGTTXN pins. For transceiver data rate limitations on specific
device/package combinations, see the specific UltraScale and UltraScale+ device data
sheets [Ref 3].
FLGA2892 SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 BGA 1.0 55 x 55
FSVH2892 SSI, flip-chip, fine-pitch, lidless with stiffener ring 55 x 55
Notes:
1. FFV, FLV, and FLG packages are footprint compatible when the package code letter designator and pin count are identical.
See UltraScale Architecture and Product Overview (DS890) [Ref 1] for specific letter codes and ordering code information.
2. These 52.5 x 52.5 packages have the same PCB ball footprint as the 47.5 x 47.5 packages and are footprint compatible.
Table 1-1: Package Specifications (Cont’d)
Packages(1) Description Package Specifications
Package Type Pitch (mm) Size (mm)
Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package
Device Package GTH Channels GTY Channels
Kintex UltraScale Devices
XCKU035 FBVA676 16 0
XCKU040 16 0
XCKU035 SFVA784 80
XCKU040 8 0
XCKU035 FBVA900 16 0
XCKU040 16 0
XCKU025
FFVA1156
12 0
XCKU035 16 0
XCKU040 20 0
XCKU060 28 0
XCKU095 20 8
XCKU060 FFVA1517 32 0
XCKU085 FLVA1517 48 0
XCKU115 48 0
XCKU095 FFVC1517 20 20
XCKU115 FLVD1517 64 0
XCKU095 FFVB1760 32 16
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Chapter 1: Packaging Overview
XCKU085 FLVB1760 44 0
XCKU115 52 0
XCKU115 FLVD1924 52 0
XCKU085 FLVF1924 56 0
XCKU115 64 0
XCKU115 FLVA2104 52 0
XCKU095 FFVB2104 32 32
XCKU115 FLVB2104 64 0
XQKU040 RBA676 16 0
XQKU040
RFA1156
20 0
XQKU060 28 0
XQKU095 20 0
XQKU115 RLD1517 64 0
XQKU115 RLF1924 64 0
Virtex UltraScale Devices
XCVU065
FFVC1517
20 20
XCVU080 20 20
XCVU095 20 20
XCVU080 FFVD1517 32 32
XCVU095 32 32
XCVU125 FLVD1517 40 32
XCVU080 FFVB1760 32 16
XCVU095 32 16
XCVU125 FLVB1760 36 16
XCVU080 FFVA2104 28 24
XCVU095 28 24
XCVU125 FLVA2104 28 24
XCVU080 FFVB2104 32 32
XCVU095 32 32
XCVU125 FLVB2104 40 36
XCVU160 FLGB2104 40 36
XCVU190 40 36
XCVU095 FFVC2104 32 32
XCVU125 FLVC2104 40 40
Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)
Device Package GTH Channels GTY Channels
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Chapter 1: Packaging Overview
XCVU160 FLGC2104 52 52
XCVU190 52 52
XCVU440 FLGB2377 36 0
XCVU190 FLGA2577 60 60
XCVU440 FLGA2892 48 0
Kintex UltraScale+ Devices
XCKU3P FFVA676 016
XCKU5P 0 16
XCKU3P FFVB676 016
XCKU5P 0 16
XCKU3P SFVB784 016
XCKU5P 0 16
XCKU3P
FFVD900
016
XCKU5P 0 16
XCKU11P 16 0
XCKU9P FFVE900 28 0
XCKU13P 28 0
XCKU11P FFVA1156 20 8
XCKU15P 20 8
XCKU11P FFVE1517 32 20
XCKU15P 32 24
XCKU15P FFVA1760 44 32
XCKU15P FFVE1760 32 24
XQKU5P FFRB676 0 16
XQKU5P SFRB784 0 16
XQKU15P FFRA1156 20 8
XQKU15P FFRE1517 32 24
Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)
Device Package GTH Channels GTY Channels
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Chapter 1: Packaging Overview
Virtex UltraScale+ Devices
XCVU3P FFVC1517 0 40
XCVU11P FLGF1924 0 64
XCVU31P FSVH1924 0 32
XCVU5P FLVA2104 052
XCVU7P 0 52
XCVU9P FLGA2104 0 52
XCVU13P FHGA2104 0 52
XCVU5P FLVB2104 076
XCVU7P 0 76
XCVU9P FLGB2104 076
XCVU11P 0 76
XCVU13P FHGB2104 0 76
XCVU5P FLVC2104 080
XCVU7P 0 80
XCVU9P FLGC2104 0 104
XCVU11P 0 96
XCVU13P FHGC2104 0 104
XCVU9P FSGD2104 076
XCVU11P 0 76
XCVU13P FIGD2104 0 76
XCVU33P FSVH2104 032
XCVU35P 0 64
XCVU9P
FLGA2577
0 120
XCVU11P 0 96
XCVU13P 0 128
XCVU13P FSGA2577 0 128
XCVU35P FSVH2892 064
XCVU37P 0 96
XQVU3P FFRC1517 0 40
XQVU7P FLRA2104 0 52
XQVU7P FLRB2104 0 76
XQVU11P FLRC2104 0 96
Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)
Device Package GTH Channels GTY Channels
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Chapter 1: Packaging Overview
Table 1-3: Serial Transceiver Channels (GTH/GTY/GTM) by Device/Package
Device Package GTH Channels GTY Channels GTM Channels
Virtex UltraScale+ Devices
XCVU27P FIGD2104 01630
XCVU29P 0 16 30
XCVU27P FSGA2577 03248
XCVU29P 0 32 48
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Chapter 1: Packaging Overview
User I/O Pins by Device/Package
Table 1-4 lists the number of available 3.3V-capable high-range (HR), 3.3V-capable
high-density (HD), and 1.8V-capable high-performance (HP) I/Os and the number of
differential I/O pairs for each UltraScale and UltraScale+ device/package combination.
IMPORTANT: Because of package inductance, each device/package supports a limited number of
simultaneous switching outputs. Limitations for specific applications can be determined using the
Vivado Design Suite report_ssn tool. See the Simultaneous Switching Outputs section of the UltraScale
Architecture SelectIO Resources User Guide (UG571) [Ref 5] for more information.
Table 1-4: Available I/O Pins by Device/Package
Device Package Total User I/O Differential I/O
HD(1) HR(1) HP(1) HD HR HP
Kintex UltraScale Devices
XCKU035 FBVA676 0 104 208 0 96 192
XCKU040 0 104 208 0 96 192
XCKU035 SFVA784 0 104 364 0 96 336
XCKU040 0 104 364 0 96 336
XCKU035 FBVA900 0 104 364 0 96 336
XCKU040 0 104 364 0 96 336
XCKU025
FFVA1156
0 104 208 0 96 192
XCKU035 0 104 416 0 96 384
XCKU040 0 104 416 0 96 384
XCKU060 0 104 416 0 96 384
XCKU095 0 52 468 0 48 432
XCKU060 FFVA1517 0 104 520 0 96 480
XCKU085 FLVA1517 0 104 520 0 96 480
XCKU115 0 104 520 0 96 480
XCKU095 FFVC1517 0 52 468 0 48 432
XCKU115 FLVD1517 0 104 234 0 96 216
XCKU095 FFVB1760 0 52 598 0 48 552
XCKU085 FLVB1760 0 104 572 0 96 528
XCKU115 0 104 598 0 96 552
XCKU115 FLVA2104 0 156 676 0 144 624
XCKU095 FFVB2104 0 52 650 0 48 600
XCKU115 FLVB2104 0 104 598 0 96 552
XCKU115 FLVD1924 0 156 676 0 144 624
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Chapter 1: Packaging Overview
XCKU085 FLVF1924 0 104 520 0 96 480
XCKU115 0 104 624 0 96 576
XQKU040 RBA676 0 104 208 0 96 192
XQKU040
RFA1156
0 104 416 0 96 384
XQKU060 0 104 416 0 96 384
XQKU095 0 52 468 0 48 432
XQKU115 RLD1517 0 104 234 0 96 216
XQKU115 RLF1924 0 104 624 0 96 576
Virtex UltraScale Devices
XCVU065
FFVC1517
0 52 468 0 48 432
XCVU080 0 52 468 0 48 432
XCVU095 0 52 468 0 48 432
XCVU080 FFVD1517 0 52 286 0 48 264
XCVU095 0 52 286 0 48 264
XCVU125 FLVD1517 0 52 286 0 48 264
XCVU080 FFVB1760 0 52 650 0 48 600
XCVU095 0 52 650 0 48 600
XCVU125 FLVB1760 0 52 650 0 48 600
XCVU080 FFVA2104 0 52 780 0 48 720
XCVU095 0 52 780 0 48 720
XCVU125 FLVA2104 0 52 780 0 48 720
XCVU080 FFVB2104 0 52 650 0 48 600
XCVU095 0 52 650 0 48 600
XCVU125 FLVB2104 0 52 650 0 48 600
XCVU160 FLGB2104 0 52 650 0 48 600
XCVU190 0 52 650 0 48 600
XCVU095 FFVC2104 0 52 364 0 48 336
XCVU125 FLVC2104 0 52 364 0 48 336
XCVU160 FLGC2104 0 52 364 0 48 336
XCVU190 0 52 364 0 48 336
XCVU440 FLGB2377 0 52 1248 0 48 1152
XCVU190 FLGA2577 0 0 448 0 0 412
XCVU440 FLGA2892 0 52 1404 0 48 1296
Table 1-4: Available I/O Pins by Device/Package (Cont’d)
Device Package Total User I/O Differential I/O
HD(1) HR(1) HP(1) HD HR HP
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Kintex UltraScale+ Devices
XCKU3P FFVA676 48 0 208 48 0 192
XCKU5P 48 0 208 48 0 192
XCKU3P FFVB676 72 0 208 72 0 192
XCKU5P 72 0 208 72 0 192
XCKU3P SFVB784 96 0 208 96 0 192
XCKU5P 96 0 208 96 0 192
XCKU3P
FFVD900
96 0 208 96 0 192
XCKU5P 96 0 208 96 0 192
XCKU11P 96 0 312 96 0 288
XCKU9P FFVE900 96 0 208 96 0 192
XCKU13P 96 0 208 96 0 192
XCKU11P FFVA1156 48 0 416 48 0 384
XCKU15P 48 0 468 48 0 432
XCKU11P FFVE1517 96 0 416 96 0 384
XCKU15P 96 0 416 96 0 384
XCKU15P FFVA1760 96 0 416 96 0 384
XCKU15P FFVE1760 96 0 572 96 0 528
XQKU5P FFRB676 72 0 208 72 0 192
XQKU5P SFRB784 96 0 208 96 0 192
XQKU15P FFRA1156 48 0 468 48 0 432
XQKU15P FFRE1517 96 0 416 96 0 384
Virtex UltraScale+ Devices
XCVU3P FFVC1517 0 0 520 0 0 480
XCVU11P FLGF1924 0 0 624 0 0 576
XCVU31P FSVH1924 0 0 208 0 0 192
XCVU5P FLVA2104 0 0 832 0 0 768
XCVU7P 0 0 832 0 0 768
XCVU9P FLGA2104 0 0 832 0 0 768
XCVU13P FHGA2104 0 0 832 0 0 768
XCVU5P FLVB2104 0 0 702 0 0 648
XCVU7P 0 0 702 0 0 648
Table 1-4: Available I/O Pins by Device/Package (Cont’d)
Device Package Total User I/O Differential I/O
HD(1) HR(1) HP(1) HD HR HP
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XCVU9P FLGB2104 0 0 702 0 0 648
XCVU11P 0 0 572 0 0 528
XCVU13P FHGB2104 0 0 702 0 0 648
XCVU5P FLVC2104 0 0 416 0 0 384
XCVU7P 0 0 416 0 0 384
XCVU9P FLGC2104 0 0 416 0 0 384
XCVU11P 0 0 416 0 0 384
XCVU13P FHGC2104 0 0 416 0 0 384
XCVU9P FSGD2104 0 0 676 0 0 624
XCVU11P 0 0 572 0 0 528
XCVU13P FIGD2104 0 0 676 0 0 624
XCVU27P FIGD2104 0 0 520 0 0 240
XCVU29P 0 0 676 0 0 312
XCVU33P FSVH2104 0 0 208 0 0 192
XCVU35P 0 0 416 0 0 384
XCVU9P
FLGA2577
0 0 448 0 0 414
XCVU11P 0 0 448 0 0 414
XCVU13P 0 0 448 0 0 414
XCVU13P FSGA2577 0 0 448 0 0 414
XCVU27P FSGA2577 0 0 292 0 0 134
XCVU29P 0 0 448 0 0 206
XCVU35P FSVH2892 0 0 416 0 0 384
XCVU37P 0 0 624 0 0 576
XQVU3P FFRC1517 0 0 520 0 0 480
XQVU7P FLRA2104 0 0 832 0 0 768
XQVU7P FLRB2104 0 0 702 0 0 648
XQVU11P FLRC2104 0 0 416 0 0 384
Notes:
1. The maximum user I/O numbers do not include pins in the configuration bank 0 or the GT serial transceivers.
Table 1-4: Available I/O Pins by Device/Package (Cont’d)
Device Package Total User I/O Differential I/O
HD(1) HR(1) HP(1) HD HR HP
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Chapter 1: Packaging Overview
Pin Definitions
Table 1-5 lists the pin definitions used in UltraScale and UltraScale+ device packages.
Table 1-5: Pin Definitions
Pin Name Type Direction Description
User I/O Pins
IO_L[1to24][P or N]_T[0to3] [UorL]_N[0to12]_ [multi-function]_[bank number] or
IO_T[0to3][UorL]_N[0to12]_[multi-function]_[bank number]
Dedicated Input/
Output
Most user I/O pins are capable of differential signaling
and can be implemented as pairs. Each user I/O pin name
consists of several indicator labels, where:
• IO indicates a user I/O pin.
•L[1to24] indicates a unique differential pair with P
(positive) and N (negative) sides. User I/O pins without
the L indicator are single-ended.
•T[0 to 3][U or L] indicates the assigned byte group and
nibble location (upper or lower portion) within that
group for the pin.
•N[0 to 12] the number of the I/O within its byte group.
•[multi-function] indicates any other functions that the
pin can provide. If not used for this function, the pin can
be a user I/O.
•[bank number] indicates the assigned bank for the user
I/O pin.
User I/O Multi-Function Pins
GC or HDGC Multi-
function
Input/
Output
Four global clock (GC) pin pairs are in each bank. HDGC
pins have direct access to the global clock buffers. GC pins
have direct access to the global clock buffers, MMCMs,
and PLLs that are in the clock management tile (CMT)
adjacent to the same I/O bank. GC and HDGC inputs
provide dedicated, high-speed access to the internal
global and regional clock resources. GC and HDGC inputs
use dedicated routing and must be used for clock inputs
where the timing of various clocking features is
imperative. GC or HDGC pins can be treated as user I/O
when not used as input clocks.
Up-to-date information about designing with the GC
(or HDGC) pin is available in the UltraScale Architecture
Clocking Resources User Guide (UG572) [Ref 6].
VRP(1) Multi-
function N/A
This pin is for the DCI voltage reference resistor of P
transistor (per bank, to be pulled Low with a reference
resistor).
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
DBC
QBC
Multi-
function Input
Byte lane clock (DBC and QBC) input pin pairs are clock
inputs directly driving source synchronous clocks to the
bit slices in the I/O banks. In memory applications, these
are also known as DQS. For more information, consult the
UltraScale Architecture SelectIO Resources User Guide
(UG571) [Ref 5].
PERSTN[0 to 1]Multi-
function Input Default reset pin locations for the integrated block for PCI
Express.
User I/O Multi-Function Configuration Pins
For further descriptions, including configuration modes and recommended external pull-up/pull-down resistors,
see the UltraScale Architecture Configuration User Guide (UG570) [Ref 7].
EMCCLK Multi-
function Input External master configuration clock.
DOUT_CSO_B Multi-
function Output Data output for serial daisy-chaining or active-Low
chip-select output for SelectMAP daisy-chaining.
D[04 to 31]Multi-
function Bidirectional Configuration data pins.
A[00 to 28]Multi-
function Output Address output.
CSI_ADV_B Multi-
function
Input or
Output Active-Low chip-select input or address valid output.
FOE_B Multi-
function Output Active-Low flash output enable.
FWE_FCS2_B Multi-
function Output Active-Low flash write-enable for BPI flash or flash
chip-select for second SPI (x8) flash.
RS[0 to 1]Multi-
function Output Revision select outputs.
Dedicated (Bank 0) Configuration Pins(2)
For more information see the UltraScale Architecture Configuration User Guide (UG570) [Ref 7].
M[0 to 2]_0 Dedicated Input Configuration mode selection.
INIT_B_0 Dedicated Bidirectional
(open-drain) Active-Low initialization
Table 1-5: Pin Definitions (Cont’d)
Pin Name Type Direction Description
(I XILINXa Send Feed back
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CFGBVS_0 Dedicated Input
Bank 0 and bank 65 voltage select. This pin determines the
I/O voltage operating range and voltage tolerance for the
dedicated configuration bank 0 and multi-function
bank 65. Connect CFGBVS High or Low per the bank
voltage requirements.
•V
CCO_0 = 2.5V or 3.3V, tie CFGBVS High (connect to
VCCO_0).
•V
CCO_0 = 1.5V or 1.8V, tie CFGBVS Low (connect to GND)
CAUTION! To avoid device damage, this pin must be
connected correctly to either VCCO_0 or GND.
PUDC_B_0 Dedicated Input
Active-Low input enables internal pull-ups during
configuration on all SelectIO pins:
0 = Weak preconfiguration I/O pull-up resistors enabled.
1 = Weak preconfiguration I/O pull-up resistors disabled.
POR_OVERRIDE Dedicated Input
All configuration modes
Power-on reset delay override.
CAUTION! Do not allow this pin to float before and
during configuration. This pin must be tied to VCCINT or
GND. Do not connect to VCCO_0.
Information about designing with the POR_OVERRIDE pin
is available in the UltraScale Architecture Configuration
User Guide (UG570) [Ref 7].
DONE_0 Dedicated Bidirectional Active-High, DONE indicates successful completion of
configuration.
PROGRAM_B_0 Dedicated Input Active Low, asynchronous reset to configuration logic.
TDO_0 Dedicated Output JTAG test data output.
TDI_0 Dedicated Input JTAG test data input.
RDWR_FCS_B_0 Dedicated Input/
Output
Input control signal for SelectMAP data bus direction:
High for reading or Low for writing configuration data.
Or, active-Low flash chip-select output.
TMS_0 Dedicated Input JTAG test mode data select.
TCK_0 Dedicated Input JTAG test clock
CCLK_0 Dedicated Input/
Output
Configuration clock. Output in Master mode or input in
Slave mode.
D00_MOSI_0 Dedicated Bidirectional Data Bit 0 or SPI master-output
D01_DIN_0 Dedicated Bidirectional Data Bit 1 or serial mode data input
D02_0 Dedicated Bidirectional Data Bit 2
D03_0 Dedicated Bidirectional Data Bit 3
Table 1-5: Pin Definitions (Cont’d)
Pin Name Type Direction Description
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Other Dedicated Pins
DXN
Dedicated N/A
Temperature-sensing diode pins (Anode: DXP; Cathode:
DXN). The thermal diode is accessed by using the DXP and
DXN pins in bank 0. When not used, tie to GND.
To use the thermal diode an appropriate external thermal
monitoring IC must be added. Consult the external
thermal monitoring IC data sheet for usage guidelines.
DXP
System Monitor Pins(3)
AD[0 to 15][P or N] Multi-
function Input System Monitor differential auxiliary analog inputs 0–15.
VCCADC Dedicated N/A System Monitor analog positive supply voltage.
GNDADC Dedicated N/A System Monitor analog ground reference.
VREFP Dedicated N/A Voltage reference input.
VREFN Dedicated N/A Voltage reference GND.
VP Dedicated Input System Monitor dedicated differential analog input
(positive side).
VN Dedicated Input System Monitor dedicated differential analog input
(negative side).
I2C_SCLK Multi-
function Bidirectional
I2C serial clock. Directly connected to the System Monitor
DRP interface for I2C operation configuration.
IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used for
I2C access until after configuration.
I2C_SDA Multi-
function Bidirectional
I2C serial data line. Directly connected to the System
Monitor DRP interface for I2C operation configuration.
IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used for
I2C access until after configuration.
Table 1-5: Pin Definitions (Cont’d)
Pin Name Type Direction Description
(I XILINXa Send Feed back
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SMBALERT Multi-
function Bidirectional
Optional PMBus alert, interrupt signal. When Low,
indicates a system fault that must be cleared using PMBus
commands. Connect to SMBALERT_TS.
For more information, see the UltraScale Architecture
System Monitor User Guide (UG580) [Ref 10].
IMPORTANT: By default, the PMBus is active prior to
configuration. Only use as a multi-functional I/O pin in
designs that can tolerated this pin being driven prior to
configuration.
This pin is present on Kintex UltraScale+ and Virtex
UltraScale+ devices.
Power/Ground Pins
For more information on voltage specifications see the UltraScale and UltraScale+ device data sheets [Ref 3].
GND Dedicated N/A Ground.
VCCINT Dedicated N/A Power-supply pins for the internal logic.
VCCINT_IO Dedicated N/A
Power-supply pins for the I/O banks. For Kintex and Virtex
UltraScale devices, connect VCCINT_IO to VCCINT. For
Kintex and Virtex UltraScale+ devices, connect VCCINT_IO
to VCCBRAM. Both migration and lower voltage
differences (-1LI and -2LE at 0.72V) are discussed in the
UltraScale Architecture PCB and Pin Planning User Guide
(UG583). See the connection matrix in the Power Supply
Voltage Levels and VCCINT_IO Connection section [Ref 11].
VCCINT_GT_[L or R] Dedicated N/A GTM core power-supply pins.
VCCAUX Dedicated N/A Power-supply pins for auxiliary circuits.
VCCAUX_IO Dedicated N/A
Auxiliary power-supply pins for the I/O banks. VCCAUX_IO
must be connected to VCCAUX on the board.
Note: Package files for XQ ruggedized Kintex and
Virtex UltraScale+devices (for example: FFRB676) have
unique pin names for VCCAUX_HPIO and
VCCAUX_HDIO. These pins can be connected to a
common VCCAUX_IO supply.
VCCIO_HBM_[HBM bank
number] Dedicated N/A HBM component I/O power supply (VDDQ)
VCC_HBM_[HBM bank
number] Dedicated N/A HBM component core power supply (VDDC)
VCCAUX_HBM_[HBM
bank number] Dedicated N/A HBM component word line voltage pump (VPP)
VCCBRAM Dedicated N/A Block RAM power supply pins.
Table 1-5: Pin Definitions (Cont’d)
Pin Name Type Direction Description
(I XILINXa Send Feed back
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VBATT Dedicated N/A Decryptor key memory backup supply; this pin should be
tied to the appropriate VCC or GND when not used.
VCCO_[bank number](4) Dedicated N/A Power-supply pins for the output drivers (per bank).
VREF_[bank number] Dedicated N/A These are input threshold voltage pins.
RSVDGND Dedicated N/A
Reserved pins—must be tied to GND.
These pins are present on Kintex UltraScale+ and Virtex
UltraScale+ devices.
TIP: In footprint compatible devices, this pin can be
labeled differently and serve different purposes. When
planning migration between devices, include the
functionality between all footprint compatible devices.
RSVD Dedicated N/A
Reserved pins—leave floating.
TIP: In footprint compatible devices, this pin can be
labeled differently and serve different purposes. When
planning migration between devices, include the
functionality between all footprint compatible devices.
Multi-gigabit Serial Transceiver Pins (GTHE3 and GTYE3)
For more information on the GTH and GTY transceivers see the UltraScale Architecture GTH Transceivers User
Guide (UG576)[Ref 8] or UltraScale Architecture GTY Transceivers User Guide [Ref 9].
MGTHRX[P or N][0 to 3]
_[GT quad number] Dedicated Input Differential receive port GTH Quad.
MGTHTX[P or N][0 to 3]
_[GT quad number] Dedicated Output Differential transmit port GTH Quad.
MGTYRX[P or N][0 to 3]
_[GT quad number] Dedicated Input Differential receive port GTY Quad.
MGTYTX[P or N][0 to 3]
_[GT quad number] Dedicated Output Differential transmit port GTY Quad.
MGTYRX[P or N][0 to 3]
_[GT dual number] Dedicated Input Differential receive port GTM Dual.
MGTYTX[P or N][0 to 3]
_[GT dual number] Dedicated Output Differential transmit port GTM Dual.
MGTAVCC_[L or R]
[N, UC, C, LC, or S](5) Dedicated Input Analog power-supply pin for the receiver and transmitter
internal circuits.
Table 1-5: Pin Definitions (Cont’d)
Pin Name Type Direction Description
(I XILINXa Send Feed back
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MGTAVTT_[L or R]
[N, UC, C, LC, or S](5) Dedicated Input Analog power-supply pin for the transmit driver.
MGTVCCAUX_[L or R]
[N, UC, C, LC, or S](5) Dedicated Input Auxiliary analog Quad PLL (QPLL) voltage supply for the
transceivers.
MGTREFCLK[0 or 1]
[P or N] Dedicated Input Differential reference clock for the transceivers.
MGTAVTTRCAL_[L or R]
[N, UC, C, LC, or S](5) Dedicated N/A Precision reference resistor pin for internal calibration
termination.
MGTRREF_[L or R]
[N, UC, C, LC, or S](5) Dedicated Input Precision reference resistor pin for internal calibration
termination.
Notes:
1. See the DCI sections in UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 5] for more information on the
VRP pins.
2. All dedicated configuration pins are powered by VCCO_0.
3. See the UltraScale Architecture System Monitor User Guide (UG580) [Ref 10] for the default connections required to support
on-chip monitoring.
4. VCCO pins in unbonded banks must be connected to the VCCO for that bank (for package migration). Do NOT connect
unbonded VCCO pins to different supplies. Without a package migration requirement, VCCO pins in unbonded banks can be
tied to a common supply (VCCO or GND).
5. L (left) or R (right) plus N (north), UC (upper center), C (center), LC (lower center), and S (south) signify the GT transceiver
quad power supply groups. For example, RUC signifies the right-upper-center power supply group and LLC signifies the
left-lower-center power supply group in the FLGA2577 package.
Table 1-5: Pin Definitions (Cont’d)
Pin Name Type Direction Description
(I XILINXm ix? A676 XCKU035 XCKU040 XQKUO40 XCKUSP XCKUSP
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Footprint Compatibility between Packages
UltraScale and UltraScale+ devices are footprint compatible only with other UltraScale and UltraScale+ devices with the same
number of package pins and the same preceding alphabetic designator. For example, XCKU060-FFVA1517 is compatible with
XCKU085-FLVA1517 and XCKU115-FLVA1517, but not with XCKU115-FLVD1517. Pins that are available in one device but are not
available in another device with a compatible package include the other device's name in the No Connect column of the
package file. These pins are labeled as No Connects in the other device's package file.
IMPORTANT: Footprint compatibility does not necessarily imply that all pins will function in the same manner for different devices in a
package. For limitations and guidelines on designing for footprint compatible packages, refer to the Migration Between UltraScale Devices and
Packages section of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref 11].
Table 1-6 shows the footprint compatible devices available for each UltraScale and UltraScale+ device package. See UltraScale
Architecture and Product Overview (DS890) [Ref 1] for specific package letter code options.
IMPORTANT: The height dimensions of footprint compatible packages can vary since some devices contain SSI technology.
Table 1-6: Footprint Compatibility
Packages Footprint Compatible Devices
A676 XCKU035 XCKU040 XQKU040 XCKU3P XCKU5P
B676 XCKU3P XCKU5P XQKU5P
A784 XCKU035 XCKU040
B784 XCKU3P XCKU5P XQKU5P
A900 XCKU035 XCKU040
D900 XCKU3P XCKU5P XCKU11P
E900 XCKU9P XCKU13P
A1156 XCKU025 XCKU035 XCKU040 XQKU040 XCKU060 XQKU060 XCKU095 XQKU095 XCKU11P XCKU15P XQKU15P
(I XILINXG A1517 XCKUOGO XCKUDBS XCKUllS
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A1517 XCKU060 XCKU085 XCKU115
C1517 XCKU095 XCVU065 XCVU080 XCVU095 XCVU3P XQVU3P
D1517 XCKU115 XQKU115 XCVU080 XCVU095 XCVU125
E1517 XCKU11P XCKU15P XQKU15P
A1760 XCKU15P
B1760 XCKU085 XCKU095 XCKU115 XCVU080 XCVU095 XCVU125
E1760 XCKU15P
D1924 XCKU115
F1924 XCKU085 XCKU115 XQKU115 XCVU11P
H1924 XCVU31P
A2104 XCKU115 XCVU080 XCVU095 XCVU125 XCVU5P XCVU7P XCVU9P XCVU13P(1) XQVU7P
B2104 XCKU095 XCKU115 XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 XCVU5P XCVU7P XCVU9P XCVU11P XCVU13P(1) XQVU7P
C2104 XCVU095 XCVU125 XCVU160 XCVU190 XCVU5P XCVU7P XCVU9P XCVU11P XCVU13P(1) XQVU11P
D2104 XCVU9P XCVU11P XCVU13P XCVU27P(1) XCVU29P(1)
H2104 XCVU33P XCVU35P
B2377 XCVU440
A2577 XCVU190 XCVU9P XCVU11P XCVU13P XCVU27P XCVU29P
A2892 XCVU440
H2892 XCVU35P XCVU37P
Notes:
1. While footprint compatible, the body size for the VU13P, VU27P, and VU39P is 52.5 mm, which is larger than the 47.5 mm for a 2104 ball package.
Table 1-6: Footprint Compatibility (Cont’d)
Packages Footprint Compatible Devices
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
Many UltraScale and UltraScale+ devices that are footprint compatible in a package have
different I/O bank and transceiver quad numbers connected to the same package pins. Due
to these differences, when migrating between devices in a specific package, the type of
bank (HP vs. HR) or quad (GTH vs. GTY), whether a bank is connected or NC at the package
pins, and where the bank or quad is located on the die must be taken into consideration.
Table 1-7 and Table 1-8 show how the banks and transceiver quads are numbered between
devices in each package.
For all grouped-together footprint compatible packages, the bank and quad numbers in the
same column for each device are connect to the same package pins. For example, in the
FFVD1517 and FLVD1517 packages, bank 69 for the XCVU095 is connected to the same pins
as bank 71 for the XCVU125.
A limited number of banks have fewer than 52 SelectIO pins. For a visual representation of
all of this information, see the Die Level Bank Numbering Overview section.
(I X|L|NXm
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Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray)(1)
Package Device Package to Device I/O Mapping Unbonded I/O Banks
ABCDE FGH IJKLMNOPQ R STUVWXYZAAABAC
FBVA676
XCKU035 65 66 44 45 46 64 47, 48, 67, 68
XCKU040 65 66 44 45 46 64 47, 48, 67, 68
RBA676 XQKU040 65 66 44 45 46 64 47, 48, 67, 68
FFVA676
XCKU3P 65 66 64 67 84/85 86, 87
XCKU5P 65 66 64 67 84/85 86, 87
FFVB676
XCKU3P 84 64 65 66 67 86 87 85
XCKU5P 84 64 65 66 67 86 87 85
FFRB676 XQKU5P 84 64 65 66 67 86 87 85
SFVA784
XCKU035 65 44 45 46 47 66 68 67 64 48
XCKU040 65 44 45 46 47 66 68 67 64 48
SFVB784
XCKU3P 64 65 66 67 87 86 84 85
XCKU5P 64 65 66 67 87 86 84 85
SFRB784 XQKU5P 64 65 66 67 87 86 84 85
FBVA900
XCKU035 65 66 67 44 45 46 47 48 64 68
XCKU040 65 66 67 44 45 46 47 48 64 68
FFVD900
XCKU3P 65 66 64 67 84 85 87 86
XCKU5P 65 66 64 67 84 85 87 86
XCKU11P 65 66 67 68 69 70 88 89 91 90 71, 64
FFVE900
XCKU9P 64 65 66 67 44 47 48 49 50
XCKU13P 64 65 66 67 44 47 48 49 50
(I XILINXm
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FFVA1156
XCKU025 65 66 44 45 46 64
XCKU035 65 66 67 68 44 45 46 47 48 64
XCKU040 65 66 67 68 44 45 46 47 48 64
XCKU060 65 66 67 68 44 45 46 47 48 64 24, 25
XCKU095 65 66 68 67 45 44 46 47 48 64 49, 50, 51, 69, 70, 71
XCKU11P 65 66 70 71 67 64 68 69 88/89 90, 91
XCKU15P 65 66 71 72 67 64 68 69 70 90/91 73, 74, 93, 94
FFRA1156 XQKU15P 65 66 71 72 67 64 68 69 70 90/91 73, 74, 93, 94
RFA1156
XQKU040 65 66 67 68 44 45 46 47 48 64
XQKU060 65 66 67 68 44 45 46 47 48 64 24, 25
XQKU095 65 66 68 67 45 44 46 47 48 64 49, 50, 51, 69, 70, 71
FFVA1517 XCKU060 65 44 45 24 25 66 67 68 46 47 48 64
FLVA1517
XCKU085 65 44 45 24 25 66 67 68 46 47 48 64 29, 30, 49, 50, 51, 52, 69, 70,
71, 72
XCKU115 65 44 45 24 25 66 67 68 46 47 48 64 29, 30, 49, 50, 51, 52, 69, 70,
71, 72
FFVC1517
XCKU095
84/94
65 66 67 68 44 45 46 47 48 51, 50, 49, 71, 70, 69
XCVU080
84/94
65 66 67 68 44 45 46 47 48 51, 50, 49, 71, 70, 69
XCVU065
84/94
65 66 67 68 44 45 46 47 48
XCVU095
84/94
65 66 67 68 44 45 46 47 48 51, 50, 49, 71, 70, 69
XCVU3P 64 65 66 67 68 44 45 46 47 48
FFRC1517 XQVU3P 64 65 66 67 68 44 45 46 47 48
Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray)(1) (Cont’d)
Package Device Package to Device I/O Mapping Unbonded I/O Banks
ABCDE FGH IJKLMNOPQ R STUVWXYZAAABAC
(I XILINXm
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FFVD1517
XCVU080
84/94
65 66 67(2) 69 70 71 44, 45, 46, 47, 48, 49, 50, 51,
68
XCVU095
84/94
65 66 67(2) 69 70 71 44, 45, 46, 47, 48, 49, 50, 51,
68
FLVD1517
XCKU115
84/94
65 66 67(2) 71 72 73
24, 25, 29, 30, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 68, 69,
70
XCVU125
84/94
65 66 67(2) 71 72 73 44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 68, 69, 70
RLD1517 XQKU115
84/94
65 66 67(2) 71 72 73
24, 25, 29, 30, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 68, 69,
70
FFVE1517
XCKU11P 65 64 66 67 68 91 90 89 88 71 70 69
XCKU15P 65 64 66 67 68 94 93 91 90 71 70 69 74, 73, 72
FFRE1517 XQKU15P 65 64 66 67 68 94 93 91 90 71 70 69 74, 73, 72
FFVA1760 XCKU15P 65 64 66 67 68 94 93 91 90 72 71 70 74, 73, 69
FLVB1760
XCKU085
84/94
65 66 67 44 45 46 47 48 49 50 51 52 24, 25, 29, 30, 68, 69, 70, 71,
72
XCKU115
84/94
65 66 67 44 45 46 47 48 49 50 51 52 53(2) 24, 25, 29, 30, 68, 69, 70, 71,
72, 73
FFVB1760
XCKU095
84/94
65 66 67 44 45 46 47 48 70 71 49 50 51(2) 68, 69
XCVU080
84/94
65 66 67 44 45 46 47 48 70 71 49 50 51(2) 68, 69
XCVU095
84/94
65 66 67 44 45 46 47 48 70 71 49 50 51(2) 68, 69
FLVB1760 XCVU125
84/94
65 66 67 44 45 46 47 48 49 50 51 52 53(2) 68, 69, 70, 71, 72, 73
FFVE1760 XCKU15P 65 64 66 67 68 69 94 93 91 90 74 73 72 71 70
Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray)(1) (Cont’d)
Package Device Package to Device I/O Mapping Unbonded I/O Banks
ABCDE FGH IJKLMNOPQ R STUVWXYZAAABAC
(I XILINXG
Chapter 1: Packaging Overview
UltraScale Device Packaging and Pinouts 41
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FLVD1924 XCKU115
84/94
65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 24, 25, 29, 30, 48, 49, 68, 69
FLVF1924
XCKU085 65 66 67 68 44 45 46 51 52 70 71 72 30, 29, 25, 24, 50, 49, 48, 47,
69, 64
XCKU115 65 66 67 68 44 45 46 51 52 53 70 71 72 73 30, 29, 25, 24, 50, 49, 48, 47,
69, 64
RLF1924 XQKU115 65 66 67 68 44 45 46 51 52 53 70 71 72 73 30, 29, 25, 24, 50, 49, 48, 47,
69, 64
FLGF1924 XCVU11P 65 66 67 68 64 69 70 71 72 73 74 75
FSVH1924 XCVU31P 64 65 66 67
FFVA2104
XCVU080
84/94
65 66 67 44 45 46 47 48 49 50 51 68 69 70 71
XCVU095
84/94
65 66 67 44 45 46 47 48 49 50 51 68 69 70 71
FLVA2104
XCKU115
84/94
65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 30, 29, 25, 24, 49, 48, 69, 68
XCVU125
84/94
65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 49, 48, 69, 68
XCVU5P 64 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 49, 48, 69, 68
XCVU7P 64 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 49, 48, 69, 68
FLRA2104XQVU7P 64656667 444546475051525370717273 49, 48, 69, 68
FLGA2104 XCVU9P 64 65 66 67 40 41 42 43 45 46 47 48 70 71 72 73 53, 52, 51, 50, 49, 44, 39, 69,
68, 63, 62, 61, 60, 59
FHGA2104 XCVU13P 64 65 66 67 60 61 62 63 68 69 70 71 72 73 74 75
Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray)(1) (Cont’d)
Package Device Package to Device I/O Mapping Unbonded I/O Banks
ABCDE FGH IJKLMNOPQ R STUVWXYZAAABAC
(I XILINXm
Chapter 1: Packaging Overview
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FFVB2104
XCKU095
84/94
65 66 67 68(2) 44 45 46 49 50 51 69 70 71 48, 47
XCVU080
84/94
65 66 67 68(2) 44 45 46 49 50 51 69 70 71 48, 47
XCVU095
84/94
65 66 67 68(2) 44 45 46 49 50 51 69 70 71 48, 47
FLVB2104
XCKU115
84/94
65 66 67 68(2) 44 45 46 51 52 53 71 72 73 30, 29, 25, 24, 50, 49, 48, 47,
70, 69
XCVU125
84/94
65 66 67 68(2) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69
XCVU5P 64 65 66 67 68(2) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69
XCVU7P 64 65 66 67 68(2) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69
FLRB2104 XQVU7P 64 65 66 67 68(2) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69
FLGB2104
XCVU160
84/94
65 66 67 68(2) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 43, 42, 41, 40,
73, 69, 63, 62, 61, 60
XCVU190
84/94
65 66 67 68(2) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 43, 42, 41, 40,
39, 73, 69, 63, 62, 61, 60, 59
XCVU9P 64 65 66 67 68(2) 40 41 42 46 47 48 70 71 72 53, 52, 51, 50, 49, 45, 44, 43,
39, 73, 69, 63, 62, 61, 60, 59
XCVU11P 64656667 68 69 70 71 72 73 74 75
FHGB2104 XCVU13P 64 65 66 67 68(2) 61 62 63 69 70 71 72 73 74 75, 60
Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray)(1) (Cont’d)
Package Device Package to Device I/O Mapping Unbonded I/O Banks
ABCDE FGH IJKLMNOPQ R STUVWXYZAAABAC
(I XILINXG
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FFVC2104 XCVU095
84/94
65 66 67 68 69 70 71 51, 50, 49, 48, 47, 46, 45, 44
FLVC2104
XCVU125
84/94
65 66 67 68 70 71 72 53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 73, 69
XCVU5P 64 65 66 67 68 70 71 72 53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 73, 69
XCVU7P 64 65 66 67 68 70 71 72 53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 73, 69
FLGC2104
XCVU160
84/94
65 66 67 68 70 71 72
52, 51, 50, 49, 48, 47, 46, 45,
44, 43, 42, 41, 40, 69, 63, 62,
61, 60
XCVU190
84/94
65 66 67 68 70 71 72
53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 43, 42, 41, 40, 39, 73,
69, 63, 62, 61, 60, 59
XCVU9P 64 65 66 67 68 70 71 72
53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 43, 42, 41, 40, 39, 73,
69, 63, 62, 61, 60, 59
XCVU11P 64656667 68697071 75, 74, 73, 72
FLRC2104 XQVU11P 64 65 66 67 68 69 70 71 75, 74, 73, 72
FHGC2104 XCVU13P 64 65 66 67 68 69 70 71 75, 74, 73, 72, 63, 62, 61, 60
FSGD2104
XCVU9P 64 65 66 67 40 41 42 46 47 48 70 71 72
53, 52, 51, 50, 49, 45, 44, 43,
39, 73, 69, 68, 63, 62, 61, 60,
59
XCVU11P 64656667 68 69 70 71 72 73 74 75
FIGD2104
XCVU13P 64 6566 67 61 62 63 6970717273 74 75, 68, 60
XCVU27P 64 6566 67 61 62 63 6970717273 74 75, 68, 60
XCVU29P 64 6566 67 61 62 63 6970717273 74 75, 68, 60
FSVH2104
XCVU33P 64 65 66 67
XCVU35P 64 65 66 67 68 69 70 71
FLGB2377 XCVU440
84/94
65 66 67 68 60 61 62 63 40 41 42 43 45 46 47 48 50 51 52 53 70 71 72 73 39, 44, 49, 59, 69
Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray)(1) (Cont’d)
Package Device Package to Device I/O Mapping Unbonded I/O Banks
ABCDE FGH IJKLMNOPQ R STUVWXYZAAABAC
(I XILINXm
Chapter 1: Packaging Overview
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FLGA2577
XCVU190 66(2) 65 61 62 63 67 68(2) 70 71 72
53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 43, 42, 41, 40, 39, 73,
69, 64, 60, 59
XCVU9P 66(2) 65 61 62 63 67 68(2) 70 71 72
53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 43, 42, 41, 40, 39, 73,
69, 64, 60, 59
XCVU11P 66(2) 65 68 69 70 71 72(2) 73 74 75 67, 64
XCVU13P 66(2) 65 61 62 63 70 71(2) 73 74 75 72, 69, 68, 67, 64, 60
FSGA2577
XCVU13P 66(2) 65 61 62 63 70 71(2) 73 74 75 72, 69, 68, 67, 64, 60
XCVU27P 66(2) 65 61 62 63 70 71(2) 73 74 75 72, 69, 68, 67, 64, 60
XCVU29P 66(2) 65 61 62 63 70 71(2) 73 74 75 72, 69, 68, 67, 64, 60
FLGA2892 XCVU440
84/94
65 66 67 68 60 61 62 63 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 70 71 72 73 59, 69
FSVH2892
XCVU35P 64 65 66 67 68 69 70 71
XCVU37P 64 65 66 67 68 69 70 71 72 73 74 75
Notes:
1. See the Die Level Bank Numbering Overview for specific changes in column numbering.
2. A limited number of banks have fewer than 52 SelectIO pins. These banks are labeled as partial.
Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray)(1) (Cont’d)
Package Device Package to Device I/O Mapping Unbonded I/O Banks
ABCDE FGH IJKLMNOPQ R STUVWXYZAAABAC
(I XILINXG
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For each grouped set of footprint compatible packages listed in Table 1-8, there is a row detailing the power supply group for
each quad. These groups are labeled according to the regions for the transceiver power supply pins, as listed in the ASCII
Pinout Files linked from Chapter 2, Package Files. For a visual representation of all of this information, see the Die Level Bank
Numbering Overview section.
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
Power Supply Group —
FBVA676
XCKU035 224 225 226 227 228
XCKU040 224 225 226 227 228
RBA676 XQKU040 224 225 226 227 228
Power Supply Group R
FFVA676
XCKU3P 224 225 226 227
XCKU5P 224 225 226 227
Power Supply Group R
FFVB676
XCKU3P 224 225 226 227
XCKU5P 224 225 226 227
FFRA676 XQKU5P 224 225 226 227
Power Supply Group —
SFVA784
XCKU035 224 225 228,227,226
XCKU040 224 225 228,227,226
Power Supply Group R
SFVB784
XCKU3P 224 225 226 227
XCKU5P 224 225 226 227
SFRB784 XQKU5P 224 225 226 227
(I XILINXm
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Power Supply Group —
FBVA900
XCKU035 224 225 226 227 228
XCKU040 224 225 226 227 228
Power Supply Group R
FFVD900
XCKU3P 224 225 226 227
XCKU5P 224 225 226 227
XCKU11P 224 225 226 227
131, 130, 129,
128, 127, 231,
230, 229, 228
Power Supply Group R L
FFVE900
XCKU9P 228 229 230 127 128 129 130
XCKU13P 228 229 230 127 128 129 130
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
(I XILINXG
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Power Supply Group R L
FFVA1156
XCKU025 224 225 226
XCKU035 224 225 226 227 228
XCKU040 224 225 226 227 228
XCKU060 224 225 226 227 228 127 128 126
XCKU095 224 225 226 227 228 129 130
131, 128, 127,
126, 125, 124,
231, 230, 229
XCKU11P 224 225 226 227 228 129 130 131, 128, 127,
231, 230
XCKU15P 224 225 226 227 228 129 130
134, 133, 132,
131, 128, 127,
234, 233, 232,
231, 230, 229
FFRA1156 XQKU15P 224 225 226 227 228 129 130
134, 133, 132,
131, 128, 127,
234, 233, 232,
231, 230, 229
RFA1156
XQKU040 224 225 226 227 228
XQKU060 224 225 226 227 228 127 128 126
XQKU095 224 225 226 227 228 129 130
131, 128, 127,
126, 125, 124,
231, 230, 229
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
Chapter 1: Packaging Overview
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Power Supply Group RS RN L
FFVA1517 XCKU060 224 225 226 227 228 126 127 128
FLVA1517
XCKU085 224 225 226 227 228 229 230 231 232 126 127 128 132,131
XCKU115 224 225 226 227 228 229 230 231 232 126 127 128 132,131
Power Supply Group R L
FFVC1517
XCKU095 224 225 226 227 228 125 126 127 128 129 131, 130, 124,
231, 230, 229
XCVU080 224 225 226 227 228 125 126 127 128 129 131, 130, 124,
231, 230, 229
XCVU065 224 225 226 227 228 124 125 126 127 128
XCVU095 224 225 226 227 228 125 126 127 128 129 131, 130, 124,
231, 230, 229
XCVU3P 224 225 226 227 228 124 125 126 127 128
FFRC1517 XQVU3P 224 225 226 227 228 124 125 126 127 128
Power Supply Group RS RN LS LN
FFVD1517
XCVU080 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
XCVU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
FLVD1517
XCVU125 224 225 226 227 228 229 230 231 232 233 124 125 126 127 129 130 131 132 133,128
XCKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 132 133
RLD1517 XQKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 132 133
Power Supply Group RS RN L
FFVE1517
XCKU11P 224 225 226 227 228 229 230 231 127 128 129 130 131
XCKU15P 224 225 226 227 228 229 230 231 127 128 129 130 131 132 134, 133, 234,
233, 232
FFRE1517 XQKU15P 224 225 226 227 228 229 230 231 127 128 129 130 131 132 134, 133, 234,
233, 232
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
Chapter 1: Packaging Overview
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Power Supply Group RS RN LS LN
FFVA1760 XCKU15P 224 225 226 227 228 229 230 231 232 233 234 127 128 129 130 131 132 133 134
Power Supply Group RS RN L
FLVB1760
XCKU085 224 225 226 227 228 230 231 232 128 131 132 127,126,229
XCKU115 224 225 226 227 228 230 231 232 233 128 131 132 133 127,126,229
FFVB1760
XCKU095 224 225 226 227 228 229 230 231 128 129 130 131 127,126,125,1
24
XCVU080 224 225 226 227 228 229 230 231 128 129 130 131 127,126,125,1
24
XCVU095 224 225 226 227 228 229 230 231 128 129 130 131 127,126,125,1
24
FLVB1760 XCVU125 224 225 226 227 228 230 231 232 233 129 130 131 132 133, 128, 127,
126, 125, 229
Power Supply Group RS RN L
FFVE1760 XCKU15P 224 225 226 227 228 229 230 231 127 128 129 130 131 132 134, 133, 234,
233, 232
Power Supply Group RS RN LS LN
FLVD1924 XCKU115 224 225 226 227 231 232 233 126 127 128 131 132 133 230,229,228
Power Supply Group RS RN LS LN
FLVF1924
XCKU085 224 225 226 227 228 229 230 231 232 126 127 128 131 132
XCKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 133 132
RLF1924 XQKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 133 132
FLGF1924 XCVU11P 224 225 226 227 228 229 230 231 232 233 125 126 127 129 131 130
135, 134, 133,
132, 128, 124,
235, 234
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
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Power Supply Group R L
FSVH1924 XCVU31P 224 225 226 227 124 125 126 127
Power Supply Group RS RN LS LN
FFVA2104
XCVU080 224 225 226 227 228 229 230 125 126 127 128 129 130 131, 124, 231
XCVU095 224 225 226 227 228 229 230 125 126 127 128 129 130 131, 124, 231
FLVA2104
XCKU115 224 225 226 227 231 232 233 126 127 128 131 132 133 230, 229, 228
XCVU125 224 225 226 227 231 232 233 125 126 127 130 131 132
133, 129, 128,
124, 230, 229,
228
XCVU5P 224 225 226 227 231 232 233 125 126 127 130 131 132
133, 129, 128,
124, 230, 229,
228
XCVU7P 224 225 226 227 231 232 233 125 126 127 130 131 132
133, 129, 128,
124, 230, 229,
228
FLRA2104 XQVU7P 224 225 226 227 231 232 233 125 126 127 130 131 132
133, 129, 128,
124, 230, 229,
228
FLGA2104 XCVU9P 224 225 226 227 231 232 233 120 121 122 125 126 127
133, 132, 131,
130, 129, 128,
124, 123, 119,
230, 229, 228,
223, 222, 221,
220, 219
FHGA2104 XCVU13P 224 225 226 227 229 230 231 125 126 127 129 130 131
135, 134, 133,
132, 128, 124,
123, 122, 121,
120, 235, 234,
233, 232, 228,
223, 222, 221,
220
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
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Power Supply Group RS RN LS LN
FFVB2104
XCKU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
XCVU080 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
XCVU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
FLVB2104
XCKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 132 133
XCVU125 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124
XCVU5P 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124
XCVU7P 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124
FLRB2104 XQVU7P 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124
FLGB2104
XCVU160 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133
124, 123, 122,
121, 120, 223,
222, 221, 220
XCVU190 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133
124, 123, 122,
121, 120, 119,
223, 222, 221,
220, 219
XCVU9P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 124 125 126 127 128
133, 132, 131,
130, 129, 119,
223, 222, 221,
220, 219
XCVU11P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 133 135, 134, 132,
235, 234
FHGB2104 XCVU13P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 133
135, 134, 132,
123, 122, 121,
120, 235, 234,
223, 222, 221,
220
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
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Power Supply Group RC RN RS LC LN LS
FFVC2104 XCVU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
FLVC2104
XCVU125 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 132 133
XCVU5P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 132 133
XCVU7P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 132 133
FLGC2104
XCVU160 224 225 226 227 228 229 230 231 232 233 220 221 222 124 125 126 127 128 129 130 131 132 133 120 121 122 123, 223
XCVU190 224 225 226 227 228 229 230 231 232 233 220 221 222 124 125 126 127 128 129 130 131 132 133 120 121 122 123, 119, 223,
219
XCVU9P 224 225 226 227 228 229 230 231 232 233 220 221 222 124 125 126 127 128 129 130 131 132 133 120 121 122 123, 119, 223,
219
XCVU11P 226 227 228 229 230 231 232 233 234 235 224 225 126 127 128 129 130 131 132 133 134 135 124 125
FLRC2104 XQVU11P 226 227 228 229 230 231 232 233 234 235 224 225 126 127 128 129 130 131 132 133 134 135 124 125
FHGC2104 XCVU13P 224 225 226 227 228 229 230 231 232 233 221 222 223 124 125 126 127 128 129 130 131 132 133 121 122 123 135, 134, 120,
235, 234, 220
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
{I XILINX. #
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Power Supply Group RS RN LS LN
FSGD2104
XCVU9P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 124 125 126 127 131
133, 132, 130,
129, 128, 119,
223, 222, 221,
220, 219
XCVU11P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 133 135, 134,
132, 235, 234
FIGD2104
XCVU13P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 128 129 130 131 133
135, 134, 132,
127, 126, 125,
124, 235, 234,
223, 222, 221,
220
XCVU27P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 128 129 130 131 133
135, 134, 132,
127, 126, 125,
124, 235, 234,
223, 222, 221,
220
XCVU29P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 128 129 130 131 133
135, 134, 132,
127, 126, 125,
124, 235, 234,
223, 222, 221,
220
Power Supply Group RS RN LS LN
FSVH2104
XCVU33P 224 225 226 227 124 125 126 127
XCVU35P 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
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Power Supply Group RC RN RS
FLGB2377 XCVU440 224 225 226 231 232 233 221 222 223
233, 232, 231,
226, 225, 224,
223, 222, 221
Power Supply Group RLC RUC RN RS
RLC
LLC LUC LN LS LLC
FLGA2577
XCVU190 224 225 226 227 228 229 230 231 232 233 219 220 221 222 223 124 125 126 127 128 129 130 131 132 133 119 120 121 122 123
XCVU9P 224 225 226 227 228 229 230 231 232 233 219 220 221 222 223 124 125 126 127 128 129 130 131 132 133 119 120 121 122 123
XCVU11P 225 226 227 228 229 230 231 232 233 234 235 224 125 126 127 128 129 130 131 132 133 134 135 124
XCVU13P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124
FSGA2577
XCVU13P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124
XCVU27P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124
XCVU29P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124
Power Supply Group RC RN RS
FLGA2892 XCVU440 224 225 226 227 229 230 231 232 219 220 221 222 233, 228, 223
Power Supply Group RS RC RN LS LC LN
FSVH2892
XCVU35P 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
XCVU37P 224 225 226 227 228 229 230 231 232 233 234 235 124 125 126 127 128 129 130 131 132 133 134 135
Table 1-8: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package Device Package to Device Transceiver Mapping Unbonded
GT Quads
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF
(I X|L|NXm Send Feed back
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Chapter 1: Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
• For each device, not all banks are bonded out in every package.
GTH/GTY/GTM Columns
• One GTH/GTY Quad = Four transceivers = Four GTHE3 or GTYE3 primitives.
• One GTM Dual = Two transceivers = Two GTME3 primitives
• Not all GT Quads/Duals are bonded out in every package.
• Also shown are quads/duals labeled with RCAL. This specifies the location of the RCAL
masters for each device. With respect to the package, the RCAL masters are located on
the same package pin for each package, regardless of the device.
• The XY coordinates shown in each quad/dual correspond to the transceiver channel
number found in the pin names for that quad/dual, as shown in Figure 1-1.
• An alphabetic designator is shown in each quad/dual. Each letter corresponds to the
columns in Table 1-7 and Table 1-8.
• The power supply group is shown in brackets [ ] for each quad/dual.
I/O Banks
• Each user I/O bank has a total of 52 I/Os where 48 can be used as differential
(24 differential pairs) or single-ended I/Os. The remaining four function only as
single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
• A limited number of banks have fewer than 52 SelectIO pins. These banks are labeled as
partial.
• Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock
resources.
• Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
• Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks.
• An alphabetic designator is shown in each bank. Each letter corresponds to the
columns in Table 1-7 and Table 1-8.
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
Clocking
• Each bank has four pairs of global clock (GC) inputs for four differential or four
single-ended clock inputs. Single-ended clock inputs should be connected to the P side
of the differential pair.
• Clock signals are distributed through global buffers driving routing and distribution
networks to reach any clock region, I/O, or GT.
• Global clock inputs can connect to an MMCM and two PLLs within the horizontally
adjacent CMT.
Bank Locations of Dedicated and Multi-Function Pins
• In all UltraScale and UltraScale+ devices, bank 65 contains the multi-function
configuration pins. Bank 0 contains the dedicated configuration pins.
•In Figure 1-2 through Figure 1-115, the multi-function configuration bank 65 is shown
adjacent to the SYSMON/CFG blocks. For devices with multiple super logic regions
(SLRs), banks 60 and 70 are also shown adjacent to the SYSMON/CFG blocks. Due to
the architectural differences between these and other banks, special consideration
must be taken when using them under certain conditions. See the State of I/Os During
and After Configuration and the Special DCI Requirements in Some Banks sections of
UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 5] for details.
• For UltraScale devices, all dedicated configuration I/Os (bank 0) and HR I/Os are 1.5V
to 3.3V capable.
• For UltraScale+ devices, all dedicated configuration I/Os (bank 0) and HR I/Os are 1.5V
to 1.8V capable.
SYSMON, Configuration, PCIe, Interlaken, and 100GE Integrated Blocks
• CFG: Configuration block
• SYSMON/CFG: Block shared between SYSMON and configuration
• PCIe: Integrated block for PCIe
Note: Do not connect the Integrated block for PCIe to transceiver channels through an SLR
crossing. For further details, refer to the Placement Rules section of the UltraScale Devices Gen3
Integrated Block for PCI Express Product Guide (PG156) [Ref 14] and UltraScale+ Devices
Integrated Block for PCI Express Product Guide (PG213) [Ref 15]. PCIe blocks with an additional
(Tandem) label support tandem configuration.
• ILKN: Interlaken block
Note: Do not connect the Interlaken block to transceiver channels through an SLR crossing. For
further details, refer to the Transceiver Interface section of the Integrated Interlaken 150G Product
Guide (PG169) [Ref 16].
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
• CMAC: 100G Ethernet block
Note: Do not connect the 100G Ethernet block to transceiver channels through an SLR crossing.
For further details, refer to the Transceiver Selection Rules section of the UltraScale Devices
Integrated Block for 100G Ethernet Product Guide (PG165) [Ref 17] or UltraScale+ Devices
Integrated 100G Ethernet Subsystem Product Guide (PG203) [Ref 18].
Device Diagrams
Figure 1-1 shows an example diagram with a brief explanation for each component.
TIP: Due to design limitations, the device resources might be less than what is shown in the device
diagrams. The actual available resources by device and package are listed in the UltraScale
Architecture and Product Overview (DS890) [Ref 1].
The following figures show a die view of each device followed by a view with respect to
each available package.
X-Ref Target - Figure 1-1
Figure 1-1: Example Device Diagram
HD 1/0 Bank 46
E
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y12-X0Y15
D[R]
HD 1/0 Bank 45
F
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y8-X0Y11
C[R]
HD 1/0 Bank 44
G
HP I/O Bank 64
J
PCIE4
X0Y1
(tandem)
GTH Quad 224
X0Y4-X0Y7
B [R] (RCAL)
HD 1/0 Bank 43
H
HP I/O Bank 63
I
PCIE4
X0Y0
GTH Quad 223
X0Y0-X0Y3
A[R]
X0Y15 →MGTH[TX or RX][P or N]3_225
X0Y14 →MGTH[TX or RX][P or N]2_225
X0Y13 →MGTH[TX or RX][P or N]1_225
X0Y12 →MGTH[TX or RX][P or N]0_225
X0Y11 →MGTH[TX or RX][P or N]3_225
X0Y10 →MGTH[TX or RX][P or N]2_225
X0Y9 →MGTH[TX or RX][P or N]1_225
X0Y8 →MGTH[TX or RX][P or N]0_225
X0Y7 →MGTH[TX or RX][P or N]3_224
X0Y6 →MGTH[TX or RX][P or N]2_224
X0Y5 →MGTH[TX or RX][P or N]1_224
X0Y4 →MGTH[TX or RX][P or N]0_224
X0Y3 →MGTH[TX or RX][P or N]3_223
X0Y2 →MGTH[TX or RX][P or N]2_223
X0Y1 →MGTH[TX or RX][P or N]1_223
X0Y0 →MGTH[TX or RX][P or N]0_223
Alphabetic Bank/Quad
Designator. Corresponds
to columns in Table 1-6
and Table 1-7.
I/O Bank Type
{HP, HR, or HD]
Integrated Blocks
and Transceiver
XY Coordinates
Transceiver Power
Supply Group
X16518-012717
{I XILINXo 7 Send Feedback
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Chapter 1: Packaging Overview
XCKU025 Bank Diagrams
X-Ref Target - Figure 1-2
Figure 1-2: XCKU025 Banks
X-Ref Target - Figure 1-3
Figure 1-3: XCKU025 Banks in FFVA1156 Package
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 45
H
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
G
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16427-012917
{I XILINXo 7 Send Feedback
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Chapter 1: Packaging Overview
XCKU035 Bank Diagrams
X-Ref Target - Figure 1-4
Figure 1-4: XCKU035 Banks
X-Ref Target - Figure 1-5
Figure 1-5: XCKU035 Banks in FBVA676 Package
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
HP I/O Bank 45 HR I/O Bank 65 Configuration
GTH Quad 225
X0Y4-X0Y7
(RCAL)
HP I/O Bank 44 HR I/O Bank 64
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X16429-012917
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 46
G
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 45
F
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
E
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16430-012917
{I XILINXo 7 Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-6
Figure 1-6: XCKU035 Banks in SFVA784 Package
X-Ref Target - Figure 1-7
Figure 1-7: XCKU035 Banks in FBVA900 Package
HP I/O Bank 48 HP I/O Bank 68
I
PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47
G
HP I/O Bank 67
J
PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
HP I/O Bank 46
F
HP I/O Bank 66
H
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
HP I/O Bank 45
E
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
D
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16432-012917
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47
I
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 45
G
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
F
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16433-012917
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-8
Figure 1-8: XCKU035 Banks in FFVA1156 Package
HP I/O Bank 48
K
HP I/O Bank 68
F
PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47
J
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 45
H
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
G
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16434-062117
{I XILINXo 7 Send Feedback
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Chapter 1: Packaging Overview
XCKU040 and XQKU040 Bank Diagrams
X-Ref Target - Figure 1-9
Figure 1-9: XCKU040 and XQKU040 Banks
X-Ref Target - Figure 1-10
Figure 1-10: XCKU040 Banks in FBVA676 Package and XQKU040 Banks in RBA676 Package
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
HP I/O Bank 45 HR I/O Bank 65 Configuration
GTH Quad 225
X0Y4-X0Y7
(RCAL)
HP I/O Bank 44 HR I/O Bank 64
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X16435-012917
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 46
G
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 45
F
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
E
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16436-012917
{I XILINXo 7 7 Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-11
Figure 1-11: XCKU040 Banks in SFVA784 Package
X-Ref Target - Figure 1-12
Figure 1-12: XCKU040 Banks in FBVA900 Package
HP I/O Bank 48 HP I/O Bank 68
I
PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47
G
HP I/O Bank 67
J
PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
HP I/O Bank 46
F
HP I/O Bank 66
H
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
HP I/O Bank 45
E
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
D
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16437-012917
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
HP I/O Bank 47
I
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 45
G
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
F
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16438-012917
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-13
Figure 1-13: XCKU040 Banks in FFVA1156 Package and XQKU040 in RFA1156 Package
HP I/O Bank 48
K
HP I/O Bank 68
F
PCIe
X0Y2
GTH Quad 228
X0Y16-X0Y19
E [R]
HP I/O Bank 47
J
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 45
H
HR I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 44
G
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16439-062117
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
XCKU060 and XQKU060 Bank Diagrams
X-Ref Target - Figure 1-14
Figure 1-14: XCKU060 and XQKU060 Banks
X-Ref Target - Figure 1-15
Figure 1-15: XCKU060 Banks in FFVA1156 Package and XQKU060 Banks in RFA1156 Package
GTH Quad 128
(RCAL)
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
GTH Quad 127
X0Y12-X0Y15 HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
GTH Quad 126
X0Y8-X0Y11 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
(RCAL)
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65 Configuration GTH Quad 225
X1Y4-X1Y7
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
X0Y16-X0Y19
X16440-012917
GTH Quad 128
G [L] (RCAL)
HP I/O Bank 48
K
HP I/O Bank 68
F
PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [R]
GTH Quad 127
F [L]
HP I/O Bank 47
J
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [R]
GTH Quad 126 HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [R] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
H
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [R]
HP I/O Bank 24 HP I/O Bank 44
G
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [R]
X0Y12-X0Y15
X0Y8-X0Y11
X0Y16-X0Y19
X16441-062117
{I XILINXo 7 Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-16
Figure 1-16: XCKU060 Banks in FFVA1517 Package
GTH Quad 128
L [L] (RCAL)
HP I/O Bank 48
M
HP I/O Bank 68
J
PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
K [L]
HP I/O Bank 47
L
HP I/O Bank 67
I
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
J [L]
HP I/O Bank 46
K
HP I/O Bank 66
H
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25
G
HP I/O Bank 45
E
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24
F
HP I/O Bank 44
D
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
X0Y12-X0Y15
X0Y8-X0Y11
X0Y16-X0Y19
X16442-012917
{I XILINXo Send Feedback
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XCKU085 Bank Diagrams
X-Ref Target - Figure 1-17
Figure 1-17: XCKU085 Banks
GTH Quad 132
X0Y16-X0Y19 HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
GTH Quad 131
X0Y12-X0Y15 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
(RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration GTH Quad 230
X1Y24-X1Y27
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
GTH Quad 128
X0Y8-X0Y11
(RCAL)
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
GTH Quad 127
X0Y4-X0Y7 HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
GTH Quad 126
X0Y0-X0Y3 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
(RCAL)
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65 Configuration GTH Quad 225
X1Y4-X1Y7
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
SLR Crossing
GTH Quad 132
X0Y32-X0Y35 HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
GTH Quad 131
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
(RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration GTH Quad 230
X1Y24-X1Y27
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
GTH Quad 128
X0Y16-X0Y19
(RCAL)
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
GTH Quad 127
X0Y12-X0Y15 HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
GTH Quad 126
X0Y8-X0Y11 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
(RCAL)
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65 Configuration GTH Quad 225
X1Y4-X1Y7
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
SLR Crossing
X16443-012917
(I XILINX, Send Feedback
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X-Ref Target - Figure 1-18
Figure 1-18: XCKU085 Banks in FLVA1517 Package
GTH Quad 132
X0Y32-X0Y35 HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
I [RN]
GTH Quad 131
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration
GTH Quad 230
X1Y24-X1Y27
G [RN]
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
F [RN]
GTH Quad 128
X0Y16-X0Y19
L [L] (RCAL)
HP I/O Bank 48
M
HP I/O Bank 68
J
PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
K [L]
HP I/O Bank 47
L
HP I/O Bank 67
I
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
J [L]
HP I/O Bank 46
K
HP I/O Bank 66
H
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25
G
HP I/O Bank 45
E
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24
F
HP I/O Bank 44
D
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16444-012917
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 69
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-19
Figure 1-19: XCKU085 Banks in FLVB1760 Package
GTH Quad 132
X0Y32-X0Y35
L [L]
HP I/O Bank 52
NHP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
H [RN]
GTH Quad 131
X0Y28-X0Y31
K [L]
HP I/O Bank 51
MHP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
G [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50
LHR I/O Bank 70 Configuration
GTH Quad 230
X1Y24-X1Y27
F [RN]
HP I/O Bank 29 HP I/O Bank 49
KHR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
GTH Quad 128
X0Y16-X0Y19
J [L] (RCAL)
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
HP I/O Bank 47
I
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
G
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16445-012917
(I XILINX, Send Feedback
UltraScale Device Packaging and Pinouts 70
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-20
Figure 1-20: XCKU085 Banks in FLVF1924 Package
GTH Quad 132
X0Y32-X0Y35
O [LN]
HP I/O Bank 52
K
HP I/O Bank 72
O
PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
I [RN]
GTH Quad 131
X0Y28-X0Y31
N [LN]
HP I/O Bank 51
J
HP I/O Bank 71
N
SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70
MConfiguration
GTH Quad 230
X1Y24-X1Y27
G [RN]
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
F [RN]
GTH Quad 128
X0Y16-X0Y19
M [LS] (RCAL)
HP I/O Bank 48 HP I/O Bank 68
F
PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
L [LS]
HP I/O Bank 47 HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
K [LS]
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
H
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
G
HR I/O Bank
84/94
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16446-012917
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 71
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Chapter 1: Packaging Overview
XCKU095 and XQKU095 Bank Diagrams
X-Ref Target - Figure 1-21
Figure 1-21: XCKU095 and XQKU095 Banks
GTY Quad 131
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27 HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y2
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
(RCAL)
CMAC
X0Y1 HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y0 HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y0
GTH Quad 227
X0Y12-X0Y15
GTY Quad 126
X0Y8-X0Y11 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
GTY Quad 125
X0Y4-X0Y7 HP I/O Bank 45 HP I/O Bank 65 Configuration
GTH Quad 225
X0Y4-X0Y7
(RCAL)
GTY Quad 124
X0Y0-X0Y3 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X16448-012917
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 72
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-22
Figure 1-22: XCKU095 Banks in FFVA1156 Package and XQKU095 in RFA1156 Package
GTY Quad 131
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27
G [L]
HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y2
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
F [L] (RCAL)
CMAC
X0Y1 HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
HP I/O Bank 48
K
HP I/O Bank 68
D
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [R]
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y0
HP I/O Bank 47
J
HP I/O Bank 67
F
ILKN
X0Y0
GTH Quad 227
X0Y12-X0Y15
D [R]
GTY Quad 126
X0Y8-X0Y11
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
GTY Quad 125
X0Y4-X0Y7
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
GTY Quad 124
X0Y0-X0Y3
HP I/O Bank 44
H
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16449-012917
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 73
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-23
Figure 1-23: XCKU095 Banks in FFVC1517 Package
GTY Quad 131
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27 HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y2
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
J [L] (RCAL)
CMAC
X0Y1 HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
I [L]
HP I/O Bank 48
K
HP I/O Bank 68
F
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [R]
GTY Quad 127
X0Y12-X0Y15
H [L]
CMAC
X0Y0
HP I/O Bank 47
J
HP I/O Bank 67
E
ILKN
X0Y0
GTH Quad 227
X0Y12-X0Y15
D [R]
GTY Quad 126
X0Y8-X0Y11
G [L]
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
GTY Quad 125
X0Y4-X0Y7
F [L]
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
GTY Quad 124
X0Y0-X0Y3
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16450-012917
(I X|L|NXm Send Feed back
UltraScale Device Packaging and Pinouts 74
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-24
Figure 1-24: XCKU095 Banks in FFVB1760 Package
HP I/O Bank 51
O (Partial)
HP I/O Bank 71
L
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
HP I/O Bank 50
N
HP I/O Bank 70
K
ILKN
X0Y2
GTH Quad 230
X0Y24-X0Y27
G [RN]
CMAC
X0Y1
HP I/O Bank 49
MHP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
CMAC
X0Y0
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X0Y0
GTH Quad 227
X0Y12-X0Y15
D [RS]
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
GTY Quad 131
X0Y28-X0Y31
M [L]
GTY Quad 130
X0Y24-X0Y27
L [L]
GTY Quad 129
X0Y20-X0Y23
K [L] (RCAL)
GTY Quad 128
X0Y16-X0Y19
J [L]
GTY Quad 127
X0Y12-X0Y15
GTY Quad 126
X0Y8-X0Y11
GTY Quad 125
X0Y4-X0Y7
GTY Quad 124
X0Y0-X0Y3
X16451-012917
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 75
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-25
Figure 1-25: XCKU095 Banks in FFVB2104 Package
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
ILKN
X0Y2
GTH Quad 230
X0Y24-X0Y27
G [RN]
CMAC
X0Y1
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
CMAC
X0Y0
ILKN
X0Y0
GTH Quad 227
X0Y12-X0Y15
D [RS]
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
Configuration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
GTY Quad 131
X0Y28-X0Y31
R [LN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
GTY Quad 129
X0Y20-X0Y23
P [LN] (RCAL)
GTY Quad 128
X0Y16-X0Y19
O [LN]
GTY Quad 127
X0Y12-X0Y15
N [LS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
GTY Quad 125
X0Y4-X0Y7
L [LS]
GTY Quad 124
X0Y0-X0Y3
K [LS]
HP I/O Bank 51
L
HP I/O Bank 50
K
HP I/O Bank 49
J
HP I/O Bank 48
HP I/O Bank 47
HP I/O Bank 46
I
HP I/O Bank 45
H
HP I/O Bank 44
G
HP I/O Bank 71
O
HP I/O Bank 70
N
HP I/O Bank 69
M
HP I/O Bank 68
F (Partial)
HP I/O Bank 67
E
HP I/O Bank 66
D
HP I/O Bank 65
C
HR I/O Bank
84/94
B
X16452-012917
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 76
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Chapter 1: Packaging Overview
XCKU115 and XQKU115 Bank Diagrams
TIP: Bank 64 is labeled as 84/94 in some packages.
X-Ref Target - Figure 1-26
Figure 1-26: XCKU115 and XQKU115 Banks
GTH Quad 133
X0Y36-X0Y39
(RCAL)
HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
GTH Quad 132
X0Y32-X0Y35 HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
GTH Quad 131
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
(RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration GTH Quad 230
X1Y24-X1Y27
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
GTH Quad 128
X0Y16-X0Y19
(RCAL)
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
GTH Quad 127
X0Y12-X0Y15 HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
GTH Quad 126
X0Y8-X0Y11 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
(RCAL)
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65 Configuration GTH Quad 225
X1Y4-X1Y7
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
SLR Crossing
X16453-012917
(I XILINX, Send Feedback
UltraScale Device Packaging and Pinouts 77
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-27
Figure 1-27: XCKU115 Banks in FLVA1517 Package
GTH Quad 133
X0Y36-X0Y39
(RCAL)
HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
GTH Quad 132
X0Y32-X0Y35 HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
I [RN]
GTH Quad 131
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration
GTH Quad 230
X1Y24-X1Y27
G [RN]
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
F [RN]
GTH Quad 128
X0Y16-X0Y19
L [L] (RCAL)
HP I/O Bank 48
M
HP I/O Bank 68
J
PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
K [L]
HP I/O Bank 47
L
HP I/O Bank 67
I
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
J [L]
HP I/O Bank 46
K
HP I/O Bank 66
H
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25
G
HP I/O Bank 45
E
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24
F
HP I/O Bank 44
D
HR I/O Bank 64
R
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16454-012917
(I XILINX, Send Feedback
UltraScale Device Packaging and Pinouts 78
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Chapter 1: Packaging Overview
TIP: Bank 64 is labeled as 84/94 in some packages.
X-Ref Target - Figure 1-28
Figure 1-28: XCKU115 Banks in FLVD1517 Package and XQKU115 in the RLD1517 Package
GTH Quad 133
X0Y36-X0Y39
R [LN] (RCAL)
HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
J [RN]
GTH Quad 132
X0Y32-X0Y35
Q [LN]
HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
I [RN]
GTH Quad 131
X0Y28-X0Y31
P [LN]
HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration
GTH Quad 230
X1Y24-X1Y27
G [RN]
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
F [RN]
GTH Quad 128
X0Y16-X0Y19
N [LS] (RCAL)
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
M [LS]
HP I/O Bank 47 HP I/O Bank 67
E (Partial)
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
L [LS]
HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
H
G
F
X16455-062117
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 79
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Chapter 1: Packaging Overview
TIP: Bank 64 is labeled as 84/94 in some packages.
X-Ref Target - Figure 1-29
Figure 1-29: XCKU115 Banks in FLVB1760 Package
GTH Quad 133
X0Y36-X0Y39
M [L] (RCAL)
HP I/O Bank 53
O (Partial) HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
I [RN]
GTH Quad 132
X0Y32-X0Y35
L [L]
HP I/O Bank 52
NHP I/O Bank 72 PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
H [RN]
GTH Quad 131
X0Y28-X0Y31
K [L]
HP I/O Bank 51
MHP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
G [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50
LHR I/O Bank 70 Configuration
GTH Quad 230
X1Y24-X1Y27
F [RN]
HP I/O Bank 29 HP I/O Bank 49
KHR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
GTH Quad 128
X0Y16-X0Y19
J [L] (RCAL)
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
HP I/O Bank 47
I
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
G
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16456-012917
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 80
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Chapter 1: Packaging Overview
TIP: Bank 64 is labeled as 84/94 in some packages.
X-Ref Target - Figure 1-30
Figure 1-30: XCKU115 Banks in FLVD1924 Package
GTH Quad 133
X0Y36-X0Y39
M [LN] (RCAL)
HP I/O Bank 53
M
HP I/O Bank 73
Q
PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
G [RN]
GTH Quad 132
X0Y32-X0Y35
L [LN]
HP I/O Bank 52
L
HP I/O Bank 72
P
PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
F [RN]
GTH Quad 131
X0Y28-X0Y31
K [LN]
HP I/O Bank 51
K
HP I/O Bank 71
O
SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
E [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50
J
HR I/O Bank 70
NConfiguration GTH Quad 230
X1Y24-X1Y27
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
GTH Quad 128
X0Y16-X0Y19
J [LS] (RCAL)
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
GTH Quad 127
X0Y12-X0Y15
I [LS]
HP I/O Bank 47
I
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
H [LS]
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
G
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16457-012917
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 81
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-31
Figure 1-31: XCKU115 Banks in FLVF1924 Package and XQKU115 Banks in RLF1924 Package
GTH Quad 133
X0Y36-X0Y39
P [LN] (RCAL)
HP I/O Bank 53
L
HP I/O Bank 73
P
PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
J [RN]
GTH Quad 132
X0Y32-X0Y35
O [LN]
HP I/O Bank 52
K
HP I/O Bank 72
O
PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
I [RN]
GTH Quad 131
X0Y28-X0Y31
N [LN]
HP I/O Bank 51
J
HP I/O Bank 71
N
SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70
MConfiguration
GTH Quad 230
X1Y24-X1Y27
G [RN]
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
F [RN]
GTH Quad 128
X0Y16-X0Y19
M [LS] (RCAL)
HP I/O Bank 48 HP I/O Bank 68
F
PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
L [LS]
HP I/O Bank 47 HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
K [LS]
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
H
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
G
HR I/O Bank
84/94
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16458-012917
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 82
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Chapter 1: Packaging Overview
TIP: Bank 64 is labeled as 84/94 in some packages.
X-Ref Target - Figure 1-32
Figure 1-32: XCKU115 Banks in FLVA2104 Package
GTH Quad 133
X0Y36-X0Y39
M [LN] (RCAL)
HP I/O Bank 53
M
HP I/O Bank 73
Q
PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
G [RN]
GTH Quad 132
X0Y32-X0Y35
L [LN]
HP I/O Bank 52
L
HP I/O Bank 72
P
PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
F [RN]
GTH Quad 131
X0Y28-X0Y31
K [LN]
HP I/O Bank 51
K
HP I/O Bank 71
O
SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
E [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50
J
HR I/O Bank 70
NConfiguration GTH Quad 230
X1Y24-X1Y27
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
GTH Quad 128
X0Y16-X0Y19
J [LS] (RCAL)
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
GTH Quad 127
X0Y12-X0Y15
I [LS]
HP I/O Bank 47
I
HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
H [LS]
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
G
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16459-062117
(I XILINX, Send Feedback
UltraScale Device Packaging and Pinouts 83
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Chapter 1: Packaging Overview
TIP: Bank 64 is labeled as 84/94 in some packages.
X-Ref Target - Figure 1-33
Figure 1-33: XCKU115 Banks in FLVB2104 Package
GTH Quad 133
X0Y36-X0Y39
R [LN] (RCAL)
HP I/O Bank 53
L
HP I/O Bank 73
O
PCIe
X0Y5
GTH Quad 233
X1Y36-X1Y39
J [RN]
GTH Quad 132
X0Y32-X0Y35
Q [LN]
HP I/O Bank 52
K
HP I/O Bank 72
N
PCIe
X0Y4
GTH Quad 232
X1Y32-X1Y35
I [RN]
GTH Quad 131
X0Y28-X0Y31
P [LN]
HP I/O Bank 51
J
HP I/O Bank 71
M
SYSMON
Configuration
GTH Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration
GTH Quad 230
X1Y24-X1Y27
G [RN]
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X1Y20-X1Y23
F [RN]
GTH Quad 128
X0Y16-X0Y19
M [LS] (RCAL)
HP I/O Bank 48 HP I/O Bank 68
F (Partial)
PCIe
X0Y2
GTH Quad 228
X1Y16-X1Y19
E [RS]
GTH Quad 127
X0Y12-X0Y15
L [LS]
HP I/O Bank 47 HP I/O Bank 67
E
PCIe
X0Y1
GTH Quad 227
X1Y12-X1Y15
D [RS]
GTH Quad 126
X0Y8-X0Y11
K [LS]
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
HP I/O Bank 25 HP I/O Bank 45
H
HR I/O Bank 65
CConfiguration
GTH Quad 225
X1Y4-X1Y7
B [RS]
HP I/O Bank 24 HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16460-012917
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 84
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Chapter 1: Packaging Overview
XCVU065 Bank Diagrams
X-Ref Target - Figure 1-34
Figure 1-34: XCVU065 Banks
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
GTY Quad 126
X0Y8-X0Y11
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
(RCAL)
GTY Quad 125
X0Y4-X0Y7
(RCAL)
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65 Configuration GTH Quad 225
X0Y4-X0Y7
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X16466-012917
X-Ref Target - Figure 1-35
Figure 1-35: XCVU065 Banks in FFVC1517 Package
GTY Quad 128
X0Y16-X0Y19
J [L]
CMAC
X0Y2
HP I/O Bank 48
K
HP I/O Bank 68
F
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [R]
GTY Quad 127
X0Y12-X0Y15
I [L]
CMAC
X0Y1
HP I/O Bank 47
J
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [R]
GTY Quad 126
X0Y8-X0Y11
H [L]
ILKN
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R] (RCAL)
GTY Quad 125
X0Y4-X0Y7
G [L] (RCAL)
CMAC
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R]
GTY Quad 124
X0Y0-X0Y3
F [L]
ILKN
X0Y0
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16467-062117
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 85
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Chapter 1: Packaging Overview
XCVU080 Bank Diagrams
X-Ref Target - Figure 1-36
Figure 1-36: XCVU080 Banks
GTY Quad 131
X0Y28-X0Y31
CMAC
X0Y3 HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27
ILKN
X0Y4 HP I/O Bank 50 HP I/O Bank 70 ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
(RCAL)
CMAC
X0Y2 HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
ILKN
X0Y3 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
GTY Quad 126
X0Y8-X0Y11
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
GTY Quad 125
X0Y4-X0Y7
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65 Configuration
GTH Quad 225
X0Y4-X0Y7
(RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X16468-062117
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 86
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-37
Figure 1-37: XCVU080 Banks in FFVC1517 Package
GTY Quad 131
X0Y28-X0Y31
CMAC
X0Y3 HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27
ILKN
X0Y4 HP I/O Bank 50 HP I/O Bank 70 ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
J [L] (RCAL)
CMAC
X0Y2 HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
I [L]
ILKN
X0Y3
HP I/O Bank 48
K
HP I/O Bank 68
F
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [R]
GTY Quad 127
X0Y12-X0Y15
H [L]
CMAC
X0Y1
HP I/O Bank 47
J
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [R]
GTY Quad 126
X0Y8-X0Y11
G [L]
ILKN
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
GTY Quad 125
X0Y4-X0Y7
F [L]
CMAC
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16469-062117
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 87
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-38
Figure 1-38: XCVU080 Banks in FFVD1517 Package
GTY Quad 131
X0Y28-X0Y31
R [LN]
CMAC
X0Y3 HP I/O Bank 51 HP I/O Bank 71
H
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
ILKN
X0Y4 HP I/O Bank 50 HP I/O Bank 70
G
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
P [LN] (RCAL)
CMAC
X0Y2 HP I/O Bank 49 HP I/O Bank 69
F
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
O [LN]
ILKN
X0Y3 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
N [LS]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E (Partial)
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
L [LS]
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
K [LS]
ILKN
X0Y0 HP I/O Bank 44
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16470-062117
(I X|L|NXm Send Feed back
UltraScale Device Packaging and Pinouts 88
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-39
Figure 1-39: XCVU080 Banks in FFVB1760 Package
GTY Quad 131
X0Y28-X0Y31
M [L]
CMAC
X0Y3
HP I/O Bank 51
O (Partial)
HP I/O Bank 71
L
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
L [L]
ILKN
X0Y4
HP I/O Bank 50
N
HP I/O Bank 70
K
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
K [L] (RCAL)
CMAC
X0Y2
HP I/O Bank 49
MHP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
J [L]
ILKN
X0Y3
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
ILKN
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
CMAC
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16471-062117
(I XILINXa G [RN] F [RN] E [RN] D [RS] C [RS] B [RS] (RCAL) A [RS] Send Feed back
UltraScale Device Packaging and Pinouts 89
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-40
Figure 1-40: XCVU080 Banks in FFVA2104 Package
GTY Quad 131
X0Y28-X0Y31
CMAC
X0Y3
HP I/O Bank 51
M
HP I/O Bank 71
Q
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27
M [LN]
ILKN
X0Y4
HP I/O Bank 50
L
HP I/O Bank 70
P
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
L [LN] (RCAL)
CMAC
X0Y2
HP I/O Bank 49
K
HP I/O Bank 69
O
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
K [LN]
ILKN
X0Y3
HP I/O Bank 48
J
HP I/O Bank 68
N
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RN]
GTY Quad 127
X0Y12-X0Y15
J [LS]
CMAC
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
I [LS]
ILKN
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
H [LS]
CMAC
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16472-062117
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 90
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-41
Figure 1-41: XCVU080 Banks in FFVB2104 Package
GTY Quad 131
X0Y28-X0Y31
R [LN]
CMAC
X0Y3
HP I/O Bank 51
L
HP I/O Bank 71
O
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
ILKN
X0Y4
HP I/O Bank 50
K
HP I/O Bank 70
N
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
P [LN] (RCAL)
CMAC
X0Y2
HP I/O Bank 49
J
HP I/O Bank 69
M
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
O [LN]
ILKN
X0Y3 HP I/O Bank 48 HP I/O Bank 68
F (Partial)
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
N [LS]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
ILKN
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
L [LS]
CMAC
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
K [LS]
ILKN
X0Y0
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16473-062117
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
XCVU095 Bank Diagrams
X-Ref Target - Figure 1-42
Figure 1-42: XCVU095 Banks
GTY Quad 131
X0Y28-X0Y31
CMAC
X0Y3 HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27
ILKN
X0Y4 HP I/O Bank 50 HP I/O Bank 70 ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
(RCAL)
CMAC
X0Y2 HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
ILKN
X0Y3 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
GTY Quad 126
X0Y8-X0Y11
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
GTY Quad 125
X0Y4-X0Y7
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65 Configuration
GTH Quad 225
X0Y4-X0Y7
(RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X16474-062117
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-43
Figure 1-43: XCVU095 Banks in FFVC1517 Package
GTY Quad 131
X0Y28-X0Y31
CMAC
X0Y3 HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27
ILKN
X0Y4 HP I/O Bank 50 HP I/O Bank 70 ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
J [L] (RCAL)
CMAC
X0Y2 HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
I [L]
ILKN
X0Y3
HP I/O Bank 48
K
HP I/O Bank 68
F
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [R]
GTY Quad 127
X0Y12-X0Y15
H [L]
CMAC
X0Y1
HP I/O Bank 47
J
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [R]
GTY Quad 126
X0Y8-X0Y11
G [L]
ILKN
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R]
GTY Quad 125
X0Y4-X0Y7
F [L]
CMAC
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R] (RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X16475-062117
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-44
Figure 1-44: XCVU095 Banks in FFVD1517 Package
GTY Quad 131
X0Y28-X0Y31
R [LN]
CMAC
X0Y3 HP I/O Bank 51 HP I/O Bank 71
H
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
ILKN
X0Y4 HP I/O Bank 50 HP I/O Bank 70
G
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
P [LN] (RCAL)
CMAC
X0Y2 HP I/O Bank 49 HP I/O Bank 69
F
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
O [LN]
ILKN
X0Y3 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
N [LS]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E (Partial)
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
L [LS]
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
K [LS]
ILKN
X0Y0 HP I/O Bank 44
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16476-062117
(I X|L|NXm Send Feed back
UltraScale Device Packaging and Pinouts 94
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-45
Figure 1-45: XCVU095 Banks in FFVB1760 Package
GTY Quad 131
X0Y28-X0Y31
M [L]
CMAC
X0Y3
HP I/O Bank 51
O (Partial)
HP I/O Bank 71
L
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
L [L]
ILKN
X0Y4
HP I/O Bank 50
N
HP I/O Bank 70
K
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
K [L] (RCAL)
CMAC
X0Y2
HP I/O Bank 49
MHP I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
J [L]
ILKN
X0Y3
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
ILKN
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
CMAC
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16477-062117
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 95
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-46
Figure 1-46: XCVU095 Banks in FFVA2104 Package
GTY Quad 131
X0Y28-X0Y31
CMAC
X0Y3
HP I/O Bank 51
M
HP I/O Bank 71
Q
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y24-X0Y27
M [LN]
ILKN
X0Y4
HP I/O Bank 50
L
HP I/O Bank 70
P
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
L [LN] (RCAL)
CMAC
X0Y2
HP I/O Bank 49
K
HP I/O Bank 69
O
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
K [LN]
ILKN
X0Y3
HP I/O Bank 48
J
HP I/O Bank 68
N
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RN]
GTY Quad 127
X0Y12-X0Y15
J [LS]
CMAC
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
I [LS]
ILKN
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
H [LS]
CMAC
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16478-062117
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-47
Figure 1-47: XCVU095 Banks in FFVB2104 Package
GTY Quad 131
X0Y28-X0Y31
R [LN]
CMAC
X0Y3
HP I/O Bank 51
L
HP I/O Bank 71
O
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
ILKN
X0Y4
HP I/O Bank 50
K
HP I/O Bank 70
N
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
P [LN] (RCAL)
CMAC
X0Y2
HP I/O Bank 49
J
HP I/O Bank 69
M
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
O [LN]
ILKN
X0Y3 HP I/O Bank 48 HP I/O Bank 68
F (Partial)
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
N [LS]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
ILKN
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
L [LS]
CMAC
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
K [LS]
ILKN
X0Y0
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X16479-062117
{I XILINXo Send Feedback
UltraScale Device Packaging and Pinouts 97
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-48
Figure 1-48: XCVU095 Banks in FFVC2104 Package
GTY Quad 131
X0Y28-X0Y31
U [LN]
CMAC
X0Y3 HP I/O Bank 51 HP I/O Bank 71
I
PCIe
X0Y3
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
T [LN]
ILKN
X0Y4 HP I/O Bank 50 HP I/O Bank 70
H
ILKN
X1Y4
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
S [LN] (RCAL)
CMAC
X0Y2 HP I/O Bank 49 HP I/O Bank 69
G
PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
R [LC]
ILKN
X0Y3 HP I/O Bank 48 HP I/O Bank 68
F
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RC]
GTY Quad 127
X0Y12-X0Y15
Q [LC]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RC]
GTY Quad 126
X0Y8-X0Y11
P [LC]
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RC]
GTY Quad 125
X0Y4-X0Y7
O [LC]
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RC] (RCAL)
GTY Quad 124
X0Y0-X0Y3
N [LC]
ILKN
X0Y0 HP I/O Bank 44
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RC]
X16480-062117
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Chapter 1: Packaging Overview
XCVU125 Bank Diagrams
X-Ref Target - Figure 1-49
Figure 1-49: XCVU125 Banks
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y3
GTH Quad 233
X0Y36-X0Y39
GTY Quad 132
X0Y32-X0Y35
CMAC
X0Y4 HP I/O Bank 52 HP I/O Bank 72 ILKN
X1Y5
GTH Quad 232
X0Y32-X0Y35
GTY Quad 131
X0Y28-X0Y31
ILKN
X0Y4 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X0Y28-X0Y31
(RCAL)
GTY Quad 130
X0Y24-X0Y27
(RCAL)
CMAC
X0Y3 HP I/O Bank 50 HP I/O Bank 70 Configuration GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
ILKN
X0Y3 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
GTY Quad 126
X0Y8-X0Y11
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
(RCAL)
GTY Quad 125
X0Y4-X0Y7
(RCAL)
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65 Configuration GTH Quad 225
X0Y4-X0Y7
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
SLR Crossing
X16481-012917
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-50
Figure 1-50: XCVU125 Banks in FLVD1517 Package
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73
H
PCIe
X0Y3
GTH Quad 233
X0Y36-X0Y39
J [RN]
GTY Quad 132
X0Y32-X0Y35
R [LN]
CMAC
X0Y4 HP I/O Bank 52 HP I/O Bank 72
G
ILKN
X1Y5
GTH Quad 232
X0Y32-X0Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
Q [LN]
ILKN
X0Y4 HP I/O Bank 51 HP I/O Bank 71
F
SYSMON
Configuration
GTH Quad 231
X0Y28-X0Y31
H [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
P [LN] (RCAL)
CMAC
X0Y3 HP I/O Bank 50 HP I/O Bank 70 Configuration
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
O [LN]
ILKN
X0Y3 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
N [LS]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E (Partial)
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
L [LS] (RCAL)
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
K [LS]
ILKN
X0Y0 HP I/O Bank 44
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
SLR Crossing
X16482-012917
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-51
Figure 1-51: XCVU125 Banks in FLVB1760 Package
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5
HP I/O Bank 53
O (Partial) HP I/O Bank 73 PCIe
X0Y3
GTH Quad 233
X0Y36-X0Y39
I [RN]
GTY Quad 132
X0Y32-X0Y35
M [L]
CMAC
X0Y4
HP I/O Bank 52
NHP I/O Bank 72 ILKN
X1Y5
GTH Quad 232
X0Y32-X0Y35
H [RN]
GTY Quad 131
X0Y28-X0Y31
L [L]
ILKN
X0Y4
HP I/O Bank 51
MHP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X0Y28-X0Y31
G [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
K [L] (RCAL)
CMAC
X0Y3
HP I/O Bank 50
LHP I/O Bank 70 Configuration
GTH Quad 230
X0Y24-X0Y27
F [RN]
GTY Quad 129
X0Y20-X0Y23
J [L]
ILKN
X0Y3
HP I/O Bank 49
KHR I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2
HP I/O Bank 48
JHP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
ILKN
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
(RCAL)
CMAC
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
SLR Crossing
X16483-012917
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-52
Figure 1-52: XCVU125 Banks in FLVA2104 Package
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5
HP I/O Bank 53
M
HP I/O Bank 73
Q
PCIe
X0Y3
GTH Quad 233
X0Y36-X0Y39
G [RN]
GTY Quad 132
X0Y32-X0Y35
M [LN]
CMAC
X0Y4
HP I/O Bank 52
L
HP I/O Bank 72
P
ILKN
X1Y5
GTH Quad 232
X0Y32-X0Y35
F [RN]
GTY Quad 131
X0Y28-X0Y31
L [LN]
ILKN
X0Y4
HP I/O Bank 51
K
HP I/O Bank 71
O
SYSMON
Configuration
GTH Quad 231
X0Y28-X0Y31
E [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
K [LN] (RCAL)
CMAC
X0Y3
HP I/O Bank 50
J
HP I/O Bank 70
NConfiguration GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y20-X0Y23
ILKN
X0Y3 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y12-X0Y15
J [LS]
CMAC
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
I [LS]
ILKN
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
H [LS] (RCAL)
CMAC
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
ILKN
X0Y0
HP I/O Bank 44
F
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
SLR Crossing
X16484-062217
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UltraScale Device Packaging and Pinouts 102
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-53
Figure 1-53: XCVU125 Banks in FLVB2104 Package
GTY Quad 133
X0Y36-X0Y39
S [LN]
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y3
GTH Quad 233
X0Y36-X0Y39
J [RN]
GTY Quad 132
X0Y32-X0Y35
R [LN]
CMAC
X0Y4
HP I/O Bank 52
L
HP I/O Bank 72
O
ILKN
X1Y5
GTH Quad 232
X0Y32-X0Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
Q [LN]
ILKN
X0Y4
HP I/O Bank 51
K
HP I/O Bank 71
N
SYSMON
Configuration
GTH Quad 231
X0Y28-X0Y31
H [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
P [LN] (RCAL)
CMAC
X0Y3
HP I/O Bank 50
J
HP I/O Bank 70
MConfiguration
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
O [LN]
ILKN
X0Y3 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
N [LS]
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68
F (Partial)
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
M [LS]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
L [LS]
ILKN
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
K [LS] (RCAL)
CMAC
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
N [LC]
ILKN
X0Y0
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
SLR Crossing
X16485-012917
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 103
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-54
Figure 1-54: XCVU125 Banks in FLVC2104 Package
GTY Quad 133
X0Y36-X0Y39
W [LN]
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y3
GTH Quad 233
X0Y36-X0Y39
J [RN]
GTY Quad 132
X0Y32-X0Y35
V [LN]
CMAC
X0Y4 HP I/O Bank 52 HP I/O Bank 72
I
ILKN
X1Y5
GTH Quad 232
X0Y32-X0Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
U [LN]
ILKN
X0Y4 HP I/O Bank 51 HP I/O Bank 71
H
SYSMON
Configuration
GTH Quad 231
X0Y28-X0Y31
H [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
T [LN] (RCAL)
CMAC
X0Y3 HP I/O Bank 50 HP I/O Bank 70
GConfiguration
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
S [LN]
ILKN
X0Y3 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y2
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
R [LC]
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68
F
PCIe
X0Y1
GTH Quad 228
X0Y16-X0Y19
E [RC]
GTY Quad 127
X0Y12-X0Y15
Q [LC]
CMAC
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y2
GTH Quad 227
X0Y12-X0Y15
D [RC]
GTY Quad 126
X0Y8-X0Y11
P [LC]
ILKN
X0Y1 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RC] (RCAL)
GTY Quad 125
X0Y4-X0Y7
O [LC] (RCAL)
CMAC
X0Y0 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RC]
GTY Quad 124
X0Y0-X0Y3
N [LC]
ILKN
X0Y0 HP I/O Bank 44
HR I/O Bank
84/94
B
PCIe
X0Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RC]
SLR Crossing
X16486-012917
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 104
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Chapter 1: Packaging Overview
XCVU160 Bank Diagrams
X-Ref Target - Figure 1-55
Figure 1-55: XCVU160 Banks
GTY Quad 133
X0Y52-X0Y55
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y4
GTH Quad 233
X0Y52-X0Y55
GTY Quad 132
X0Y45-X0Y51
CMAC
X0Y7 HP I/O Bank 52 HP I/O Bank 72 ILKN
X1Y7
GTH Quad 232
X0Y45-X0Y51
GTY Quad 131
X0Y44-X0Y47
ILKN
X0Y6 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X0Y44-X0Y47
(RCAL)
GTY Quad 130
X0Y40-X0Y43
(RCAL)
CMAC
X0Y6 HP I/O Bank 50 HP I/O Bank 70 Configuration GTH Quad 230
X0Y40-X0Y43
GTY Quad 129
X0Y36-X0Y39
ILKN
X0Y5 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X0Y36-X0Y39
GTY Quad 128
X0Y32-X0Y35
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y2
GTH Quad 228
X0Y32-X0Y35
GTY Quad 127
X0Y28-X0Y31
CMAC
X0Y4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y4
GTH Quad 227
X0Y28-X0Y31
GTY Quad 126
X0Y24-X0Y27
ILKN
X0Y2 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y24-X0Y27
(RCAL)
GTY Quad 125
X0Y20-X0Y23
(RCAL)
CMAC
X0Y3 HP I/O Bank 45 HP I/O Bank 65 Configuration GTH Quad 225
X0Y20-X0Y23
GTY Quad 124
X0Y16-X0Y19
ILKN
X0Y2 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y1
(tandem)
GTH Quad 224
X0Y16-X0Y19
GTY Quad 123
X0Y12-X0Y15
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y0
GTH Quad 223
X0Y12-X0Y15
GTY Quad 122
X0Y8-X0Y11
CMAC
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y1
GTH Quad 222
X0Y8-X0Y11
GTY Quad 121
X0Y4-X0Y7
ILKN
X0Y0 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTH Quad 221
X0Y4-X0Y7
(RCAL)
GTY Quad 120
X0Y0-X0Y3
(RCAL)
CMAC
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration GTH Quad 220
X0Y0-X0Y3
SLR Crossing
SLR Crossing
X16488-012917
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UltraScale Device Packaging and Pinouts 105
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-56
Figure 1-56: XCVU160 Banks in FLGB2104 Package
GTY Quad 133
X0Y52-X0Y55
S [LN]
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y4
GTH Quad 233
X0Y52-X0Y55
J [RN]
GTY Quad 132
X0Y45-X0Y51
R [LN]
CMAC
X0Y7
HP I/O Bank 52
L
HP I/O Bank 72
O
ILKN
X1Y7
GTH Quad 232
X0Y45-X0Y51
I [RN]
GTY Quad 131
X0Y44-X0Y47
Q [LN]
ILKN
X0Y6
HP I/O Bank 51
K
HP I/O Bank 71
N
SYSMON
Configuration
GTH Quad 231
X0Y44-X0Y47
H [RN] (RCAL)
GTY Quad 130
X0Y40-X0Y43
P [LN] (RCAL)
CMAC
X0Y6
HP I/O Bank 50
J
HP I/O Bank 70
MConfiguration
GTH Quad 230
X0Y40-X0Y43
G [RN]
GTY Quad 129
X0Y36-X0Y39
O [LN]
ILKN
X0Y5 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X0Y36-X0Y39
F [RN]
GTY Quad 128
X0Y32-X0Y35
N [LS]
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68
F (Partial)
PCIe
X0Y2
GTH Quad 228
X0Y32-X0Y35
E [RS]
GTY Quad 127
X0Y28-X0Y31
M [LS]
CMAC
X0Y4 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y4
GTH Quad 227
X0Y28-X0Y31
D [RS]
GTY Quad 126
X0Y24-X0Y27
L [LS]
ILKN
X0Y2
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y24-X0Y27
C [RS] (RCAL)
GTY Quad 125
X0Y20-X0Y23
K [LS] (RCAL)
CMAC
X0Y3
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y20-X0Y23
B [RS]
GTY Quad 124
X0Y16-X0Y19
ILKN
X0Y2
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y1
(tandem)
GTH Quad 224
X0Y16-X0Y19
A [RS]
GTY Quad 123
X0Y12-X0Y15
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y0
GTH Quad 223
X0Y12-X0Y15
GTY Quad 122
X0Y8-X0Y11
CMAC
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y1
GTH Quad 222
X0Y8-X0Y11
GTY Quad 121
X0Y4-X0Y7
ILKN
X0Y0 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTH Quad 221
X0Y4-X0Y7
(RCAL)
GTY Quad 120
X0Y0-X0Y3
(RCAL)
CMAC
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration GTH Quad 220
X0Y0-X0Y3
SLR Crossing
SLR Crossing
X16489-012917
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UltraScale Device Packaging and Pinouts 106
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-57
Figure 1-57: XCVU160 Banks in FLGC2104 Package
GTY Quad 133
X0Y52-X0Y55
W [LN]
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y4
GTH Quad 233
X0Y52-X0Y55
J [RN]
GTY Quad 132
X0Y45-X0Y51
V [LN]
CMAC
X0Y7
HP I/O Bank 52
L
HP I/O Bank 72
I
ILKN
X1Y7
GTH Quad 232
X0Y45-X0Y51
I [RN]
GTY Quad 131
X0Y44-X0Y47
U [LN]
ILKN
X0Y6
HP I/O Bank 51
K
HP I/O Bank 71
H
SYSMON
Configuration
GTH Quad 231
X0Y44-X0Y47
H [RN] (RCAL)
GTY Quad 130
X0Y40-X0Y43
T [LN] (RCAL)
CMAC
X0Y6
HP I/O Bank 50
J
HP I/O Bank 70
GConfiguration
GTH Quad 230
X0Y40-X0Y43
G [RN]
GTY Quad 129
X0Y36-X0Y39
S [LN]
ILKN
X0Y5 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y3
GTH Quad 229
X0Y36-X0Y39
F [RN]
GTY Quad 128
X0Y32-X0Y35
R [LC]
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68
F
PCIe
X0Y2
GTH Quad 228
X0Y32-X0Y35
E [RC]
GTY Quad 127
X0Y28-X0Y31
Q [LC]
CMAC
X0Y4 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y4
GTH Quad 227
X0Y28-X0Y31
D [RC]
GTY Quad 126
X0Y24-X0Y27
P [LC]
ILKN
X0Y2
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y24-X0Y27
C [RC] (RCAL)
GTY Quad 125
X0Y20-X0Y23
O [LC] (RCAL)
CMAC
X0Y3
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y20-X0Y23
B [RC]
GTY Quad 124
X0Y16-X0Y19
N [LC]
ILKN
X0Y2
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y1
(tandem)
GTH Quad 224
X0Y16-X0Y19
A [RC]
GTY Quad 123
X0Y12-X0Y15
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y0
GTH Quad 223
X0Y12-X0Y15
GTY Quad 122
X0Y8-X0Y11
Z [LS]
CMAC
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y1
GTH Quad 222
X0Y8-X0Y11
M [RS]
GTY Quad 121
X0Y4-X0Y7
Y [LS]
ILKN
X0Y0 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTH Quad 221
X0Y4-X0Y7
L [RS] (RCAL)
GTY Quad 120
X0Y0-X0Y3
X [LS] (RCAL)
CMAC
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration
GTH Quad 220
X0Y0-X0Y3
K [RS]
SLR Crossing
SLR Crossing
X16490-012917
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UltraScale Device Packaging and Pinouts 107
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Chapter 1: Packaging Overview
XCVU190 Bank Diagrams
X-Ref Target - Figure 1-58
Figure 1-58: XCVU190 Banks
GTY Quad 133
X0Y56-X0Y59
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X0Y56-X0Y59
GTY Quad 132
X0Y52-X0Y55
CMAC
X0Y7 HP I/O Bank 52 HP I/O Bank 72 ILKN
X1Y8
GTH Quad 232
X0Y52-X0Y55
GTY Quad 131
X0Y48-X0Y51
ILKN
X0Y7 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X0Y48-X0Y51
(RCAL)
GTY Quad 130
X0Y44-X0Y47
(RCAL)
CMAC
X0Y6 HP I/O Bank 50 HP I/O Bank 70 Configuration GTH Quad 230
X0Y44-X0Y47
GTY Quad 129
X0Y40-X0Y43
ILKN
X0Y6 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y4
GTH Quad 229
X0Y40-X0Y43
GTY Quad 128
X0Y36-X0Y39
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y3
GTH Quad 228
X0Y36-X0Y39
GTY Quad 127
X0Y32-X0Y35
CMAC
X0Y4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y5
GTH Quad 227
X0Y32-X0Y35
GTY Quad 126
X0Y28-X0Y31
ILKN
X0Y4 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y28-X0Y31
(RCAL)
GTY Quad 125
X0Y24-X0Y27
(RCAL)
CMAC
X0Y3 HP I/O Bank 45 HP I/O Bank 65 Configuration GTH Quad 225
X0Y24-X0Y27
GTY Quad 124
X0Y20-X0Y23
ILKN
X0Y3 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y2
(tandem)
GTH Quad 224
X0Y20-X0Y23
GTY Quad 123
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y1
GTH Quad 223
X0Y16-X0Y19
GTY Quad 122
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y2
GTH Quad 222
X0Y12-X0Y15
GTY Quad 121
X0Y8-X0Y11
ILKN
X0Y1 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTH Quad 221
X0Y8-X0Y11
(RCAL)
GTY Quad 120
X0Y4-X0Y7
(RCAL)
CMAC
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration GTH Quad 220
X0Y4-X0Y7
GTY Quad 119
X0Y0-X0Y3
ILKN
X0Y0 HP I/O Bank 39 HR I/O Bank 59 PCIe
X0Y0
GTH Quad 219
X0Y0-X0Y3
SLR Crossing
SLR Crossing
X16491-012917
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UltraScale Device Packaging and Pinouts 108
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-59
Figure 1-59: XCVU190 Banks in FLGB2104 Package
GTY Quad 133
X0Y56-X0Y59
S [LN]
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X0Y56-X0Y59
J [RN]
GTY Quad 132
X0Y52-X0Y55
R [LN]
CMAC
X0Y7
HP I/O Bank 52
L
HP I/O Bank 72
O
ILKN
X1Y8
GTH Quad 232
X0Y52-X0Y55
I [RN]
GTY Quad 131
X0Y48-X0Y51
Q [LN]
ILKN
X0Y7
HP I/O Bank 51
K
HP I/O Bank 71
N
SYSMON
Configuration
GTH Quad 231
X0Y48-X0Y51
H [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
P [LN] (RCAL)
CMAC
X0Y6
HP I/O Bank 50
J
HP I/O Bank 70
MConfiguration
GTH Quad 230
X0Y44-X0Y47
G [RN]
GTY Quad 129
X0Y40-X0Y43
O [LN]
ILKN
X0Y6 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y4
GTH Quad 229
X0Y40-X0Y43
F [RN]
GTY Quad 128
X0Y36-X0Y39
N [LS]
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68
F (Partial)
PCIe
X0Y3
GTH Quad 228
X0Y36-X0Y39
E [RS]
GTY Quad 127
X0Y32-X0Y35
M [LS]
CMAC
X0Y4 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y5
GTH Quad 227
X0Y32-X0Y35
D [RS]
GTY Quad 126
X0Y28-X0Y31
L [LS]
ILKN
X0Y4
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y28-X0Y31
C [RS] (RCAL)
GTY Quad 125
X0Y24-X0Y27
K [LS] (RCAL)
CMAC
X0Y3
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y24-X0Y27
B [RS]
GTY Quad 124
X0Y20-X0Y23
ILKN
X0Y3
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y2
(tandem)
GTH Quad 224
X0Y20-X0Y23
A [RS]
GTY Quad 123
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y1
GTH Quad 223
X0Y16-X0Y19
GTY Quad 122
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y2
GTH Quad 222
X0Y12-X0Y15
GTY Quad 121
X0Y8-X0Y11
ILKN
X0Y1 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTH Quad 221
X0Y8-X0Y11
(RCAL)
GTY Quad 120
X0Y4-X0Y7
(RCAL)
CMAC
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration GTH Quad 220
X0Y4-X0Y7
GTY Quad 119
X0Y0-X0Y3
ILKN
X0Y0 HP I/O Bank 39 HR I/O Bank 59 PCIe
X0Y0
GTH Quad 219
X0Y0-X0Y3
SLR Crossing
SLR Crossing
X16492-012917
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-60
Figure 1-60: XCVU190 Banks in FLGC2104 Package
GTY Quad 133
X0Y56-X0Y59
W [LN]
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X0Y56-X0Y59
J [RN]
GTY Quad 132
X0Y52-X0Y55
V [LN]
CMAC
X0Y7
HP I/O Bank 52
L
HP I/O Bank 72
I
ILKN
X1Y8
GTH Quad 232
X0Y52-X0Y55
I [RN]
GTY Quad 131
X0Y48-X0Y51
U [LN]
ILKN
X0Y7
HP I/O Bank 51
K
HP I/O Bank 71
H
SYSMON
Configuration
GTH Quad 231
X0Y48-X0Y51
H [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
T [LN] (RCAL)
CMAC
X0Y6
HP I/O Bank 50
J
HP I/O Bank 70
GConfiguration
GTH Quad 230
X0Y44-X0Y47
G [RN]
GTY Quad 129
X0Y40-X0Y43
S [LN]
ILKN
X0Y6 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y4
GTH Quad 229
X0Y40-X0Y43
F [RN]
GTY Quad 128
X0Y36-X0Y39
R [LC]
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68
F
PCIe
X0Y3
GTH Quad 228
X0Y36-X0Y39
E [RC]
GTY Quad 127
X0Y32-X0Y35
Q [LC]
CMAC
X0Y4 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y5
GTH Quad 227
X0Y32-X0Y35
D [RC]
GTY Quad 126
X0Y28-X0Y31
P [LC]
ILKN
X0Y4
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y28-X0Y31
C [RC] (RCAL)
GTY Quad 125
X0Y24-X0Y27
O [LC] (RCAL)
CMAC
X0Y3
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y24-X0Y27
B [RC]
GTY Quad 124
X0Y20-X0Y23
N [LC]
ILKN
X0Y3
HP I/O Bank 44
G
HR I/O Bank
84/94
B
PCIe
X0Y2
(tandem)
GTH Quad 224
X0Y20-X0Y23
A [RC]
GTY Quad 123
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y1
GTH Quad 223
X0Y16-X0Y19
GTY Quad 122
X0Y12-X0Y15
Z [LS]
CMAC
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y2
GTH Quad 222
X0Y12-X0Y15
M [RS]
GTY Quad 121
X0Y8-X0Y11
Y [LS]
ILKN
X0Y1 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTH Quad 221
X0Y8-X0Y11
L [RS] (RCAL)
GTY Quad 120
X0Y4-X0Y7
X [LS] (RCAL)
CMAC
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration
GTH Quad 220
X0Y4-X0Y7
K [RS]
GTY Quad 119
X0Y0-X0Y3
ILKN
X0Y0 HP I/O Bank 39 HR I/O Bank 59 PCIe
X0Y0
GTH Quad 219
X0Y0-X0Y3
SLR Crossing
SLR Crossing
X16493-012917
(I XILINXG Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-61
Figure 1-61: XCVU190 Banks in FLGA2577 Package
GTY Quad 133
X0Y56-X0Y59
Z [LN]
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X0Y56-X0Y59
J [RN]
GTY Quad 132
X0Y52-X0Y55
Y [LN]
CMAC
X0Y7 HP I/O Bank 52 HP I/O Bank 72
K
ILKN
X1Y8
GTH Quad 232
X0Y52-X0Y55
I [RN]
GTY Quad 131
X0Y48-X0Y51
X [LN]
ILKN
X0Y7 HP I/O Bank 51 HP I/O Bank 71
J
SYSMON
Configuration
GTH Quad 231
X0Y48-X0Y51
H [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
W [LUC] (RCAL)
CMAC
X0Y6 HP I/O Bank 50 HP I/O Bank 70
IConfiguration
GTH Quad 230
X0Y44-X0Y47
G [RUC]
GTY Quad 129
X0Y40-X0Y43
V [LUC]
ILKN
X0Y6 HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y4
GTH Quad 229
X0Y40-X0Y43
F [RUC]
GTY Quad 128
X0Y36-X0Y39
U [LUC]
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68
H (Partial)
PCIe
X0Y3
GTH Quad 228
X0Y36-X0Y39
E [RUC]
GTY Quad 127
X0Y32-X0Y35
T [LUC]
CMAC
X0Y4 HP I/O Bank 47 HP I/O Bank 67
G
ILKN
X1Y5
GTH Quad 227
X0Y32-X0Y35
D [RUC]
GTY Quad 126
X0Y28-X0Y31
S [LLC]
ILKN
X0Y4 HP I/O Bank 46 HP I/O Bank 66
B (Partial)
SYSMON
Configuration
GTH Quad 226
X0Y28-X0Y31
C [RLC] (RCAL)
GTY Quad 125
X0Y24-X0Y27
R [LLC] (RCAL)
CMAC
X0Y3 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y24-X0Y27
B [RLC]
GTY Quad 124
X0Y20-X0Y23
Q [LLC]
ILKN
X0Y3 HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y2
(tandem)
GTH Quad 224
X0Y20-X0Y23
A [RLC]
GTY Quad 123
X0Y16-X0Y19
AF [LLC]
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63
F
PCIe
X0Y1
GTH Quad 223
X0Y16-X0Y19
P [RLC]
GTY Quad 122
X0Y12-X0Y15
AE [LS]
CMAC
X0Y1 HP I/O Bank 42 HP I/O Bank 62
E
ILKN
X1Y2
GTH Quad 222
X0Y12-X0Y15
O [RS]
GTY Quad 121
X0Y8-X0Y11
AD [LS]
ILKN
X0Y1 HP I/O Bank 41 HP I/O Bank 61
D
SYSMON
Configuration
GTH Quad 221
X0Y8-X0Y11
N [RS] (RCAL)
GTY Quad 120
X0Y4-X0Y7
AC [LS] (RCAL)
CMAC
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration
GTH Quad 220
X0Y4-X0Y7
M [RS]
GTY Quad 119
X0Y0-X0Y3
AB [LS]
ILKN
X0Y0 HP I/O Bank 39 HR I/O Bank 59 PCIe
X0Y0
GTH Quad 219
X0Y0-X0Y3
L [RS]
SLR Crossing
SLR Crossing
X16494-012917
XILINXG Send Feed back
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Chapter 1: Packaging Overview
XCVU440 Bank Diagrams
X-Ref Target - Figure 1-62
Figure 1-62: XCVU440 Banks
HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y5
GTH Quad 233
X0Y56-X0Y59
HP I/O Bank 52 HP I/O Bank 72 CMAC
X0Y2
GTH Quad 232
X0Y52-X0Y55
HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTH Quad 231
X0Y48-X0Y51
(RCAL)
HP I/O Bank 50 HP I/O Bank 70 Configuration GTH Quad 230
X0Y44-X0Y47
HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y4
GTH Quad 229
X0Y40-X0Y43
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y3
GTH Quad 228
X0Y36-X0Y39
HP I/O Bank 47 HP I/O Bank 67 CMAC
X0Y1
GTH Quad 227
X0Y32-X0Y35
HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y28-X0Y31
(RCAL)
HP I/O Bank 45 HP I/O Bank 65 Configuration GTH Quad 225
X0Y24-X0Y27
HP I/O Bank 44 HR I/O Bank
84/94
PCIe
X0Y2
(tandem)
GTH Quad 224
X0Y20-X0Y23
HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y1
GTH Quad 223
X0Y16-X0Y19
HP I/O Bank 42 HP I/O Bank 62 CMAC
X0Y0
GTH Quad 222
X0Y12-X0Y15
HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTH Quad 221
X0Y8-X0Y11
(RCAL)
HP I/O Bank 40 HP I/O Bank 60 Configuration GTH Quad 220
X0Y4-X0Y7
HP I/O Bank 39 HR I/O Bank 59 PCIe
X0Y0
GTH Quad 219
X0Y0-X0Y3
SLR Crossing
SLR Crossing
X16497-012917
XILINXG Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-63
Figure 1-63: XCVU440 Banks in FLGB2377 Package
HP I/O Bank 53
V
HP I/O Bank 73
Z
PCIe
X0Y5
GTH Quad 233
X0Y56-X0Y59
F [RN]
HP I/O Bank 52
U
HP I/O Bank 72
Y
CMAC
X0Y2
GTH Quad 232
X0Y52-X0Y55
E [RN]
HP I/O Bank 51
T
HP I/O Bank 71
X
SYSMON
Configuration
GTH Quad 231
X0Y48-X0Y51
D [RN] (RCAL)
HP I/O Bank 50
S
HP I/O Bank 70
WConfiguration GTH Quad 230
X0Y44-X0Y47
HP I/O Bank 49 HR I/O Bank 69 PCIe
X0Y4
GTH Quad 229
X0Y40-X0Y43
HP I/O Bank 48
R
HP I/O Bank 68
F
PCIe
X0Y3
GTH Quad 228
X0Y36-X0Y39
HP I/O Bank 47
Q
HP I/O Bank 67
E
CMAC
X0Y1
GTH Quad 227
X0Y32-X0Y35
HP I/O Bank 46
P
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y28-X0Y31
C [RC] (RCAL)
HP I/O Bank 45
O
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y24-X0Y27
B [RC]
HP I/O Bank 44
HR I/O Bank
84/94
B
PCIe
X0Y2
(tandem)
GTH Quad 224
X0Y20-X0Y23
A [RC]
HP I/O Bank 43
N
HP I/O Bank 63
J
PCIe
X0Y1
GTH Quad 223
X0Y16-X0Y19
I [RS]
HP I/O Bank 42
M
HP I/O Bank 62
I
CMAC
X0Y0
GTH Quad 222
X0Y12-X0Y15
H [RS]
HP I/O Bank 41
L
HP I/O Bank 61
H
SYSMON
Configuration
GTH Quad 221
X0Y8-X0Y11
G [RS] (RCAL)
HP I/O Bank 40
K
HP I/O Bank 60
GConfiguration GTH Quad 220
X0Y4-X0Y7
HP I/O Bank 39 HR I/O Bank 59 PCIe
X0Y0
GTH Quad 219
X0Y0-X0Y3
SLR Crossing
SLR Crossing
X16498-012917
XILINXG Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-64
Figure 1-64: XCVU440 Banks in FLGA2892 Package
HP I/O Bank 53
Y
HP I/O Bank 73
AC
PCIe
X0Y5
GTH Quad 233
X0Y56-X0Y59
HP I/O Bank 52
X
HP I/O Bank 72
AB
CMAC
X0Y2
GTH Quad 232
X0Y52-X0Y55
H [RN]
HP I/O Bank 51
W
HP I/O Bank 71
AA
SYSMON
Configuration
GTH Quad 231
X0Y48-X0Y51
G [RN] (RCAL)
HP I/O Bank 50
V
HP I/O Bank 70
ZConfiguration
GTH Quad 230
X0Y44-X0Y47
F [RN]
HP I/O Bank 49
UHR I/O Bank 69 PCIe
X0Y4
GTH Quad 229
X0Y40-X0Y43
E [RN]
HP I/O Bank 48
T
HP I/O Bank 68
F
PCIe
X0Y3
GTH Quad 228
X0Y36-X0Y39
HP I/O Bank 47
S
HP I/O Bank 67
E
CMAC
X0Y1
GTH Quad 227
X0Y32-X0Y35
D [RC]
HP I/O Bank 46
R
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y28-X0Y31
C [RC] (RCAL)
HP I/O Bank 45
Q
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y24-X0Y27
B [RC]
HP I/O Bank 44
P
HR I/O Bank
84/94
B
PCIe
X0Y2
(tandem)
GTH Quad 224
X0Y20-X0Y23
A [RC]
HP I/O Bank 43
O
HP I/O Bank 63
J
PCIe
X0Y1
GTH Quad 223
X0Y16-X0Y19
HP I/O Bank 42
N
HP I/O Bank 62
I
CMAC
X0Y0
GTH Quad 222
X0Y12-X0Y15
L [RS]
HP I/O Bank 41
M
HP I/O Bank 61
H
SYSMON
Configuration
GTH Quad 221
X0Y8-X0Y11
K [RS] (RCAL)
HP I/O Bank 40
L
HP I/O Bank 60
GConfiguration
GTH Quad 220
X0Y4-X0Y7
J [RS]
HP I/O Bank 39
KHR I/O Bank 59 PCIe
X0Y0
GTH Quad 219
X0Y0-X0Y3
I [RS]
SLR Crossing
SLR Crossing
X16496-012917
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 114
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Chapter 1: Packaging Overview
XCKU3P Bank Diagrams
X-Ref Target - Figure 1-65
Figure 1-65: XCKU3P Banks
X-Ref Target - Figure 1-66
Figure 1-66: XCKU3P Banks in FFVA676 Package
X-Ref Target - Figure 1-67
Figure 1-67: XCKU3P Banks in FFVB676 Package
HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
HP I/O Bank 66 HD I/O Bank 86 SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
HP I/O Bank 65 HD I/O Bank 85 Configuration
GTY Quad 225
X0Y4-X0Y7
(RCAL)
HP I/O Bank 64 HD I/O Bank 84
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
X15536-020817
HP I/O Bank 67
GHD I/O Bank 87 CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
DHD I/O Bank 86 SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 65
C
HD I/O Bank 85
RConfiguration
GTY Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 64
E
HD I/O Bank 84
R
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
A [R]
X15538-020817
HP I/O Bank 67
E
HD I/O Bank 87
G
CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
HD I/O Bank 86
F
SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 65
CHD I/O Bank 85 Configuration
GTY Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 64
B
HD I/O Bank 84
A
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
A [R]
X16502-020817
(I XILINX. Send Feedback
UltraScale Device Packaging and Pinouts 115
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-68
Figure 1-68: XCKU3P Banks in SFVB784 Package
X-Ref Target - Figure 1-69
Figure 1-69: XCKU3P Banks in FFVD900 Package
HP I/O Bank 67
F
HD I/O Bank 87
K
CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
HD I/O Bank 86
L
SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 65
C
HD I/O Bank 85
JConfiguration
GTY Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 64
E
HD I/O Bank 84
I
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
A [R]
X16503-020817
XILINXG Send Feed back
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Chapter 1: Packaging Overview
XCKU5P and XQKU5P Bank Diagrams
X-Ref Target - Figure 1-70
Figure 1-70: XCKU5P and XQKU5P Banks
X-Ref Target - Figure 1-71
Figure 1-71: XCKU5P Banks in FFVA676 Package
X-Ref Target - Figure 1-72
Figure 1-72: XCKU5P Banks in FFVB676 Package and XQKU5P Banks in FFRB676 Package
HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
HP I/O Bank 66 HD I/O Bank 86 SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
HP I/O Bank 65 HD I/O Bank 85 Configuration
GTY Quad 225
X0Y4-X0Y7
(RCAL)
HP I/O Bank 64 HD I/O Bank 84
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
X15539-020817
HP I/O Bank 67
GHD I/O Bank 87 CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
DHD I/O Bank 86 SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 65
C
HD I/O Bank 85
RConfiguration
GTY Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 64
E
HD I/O Bank 84
R
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
A [R]
X15588-020817
HP I/O Bank 67
E
HD I/O Bank 87
G
CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
HD I/O Bank 86
F
SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 65
CHD I/O Bank 85 Configuration
GTY Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 64
B
HD I/O Bank 84
A
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
A [R]
X15586-020817
(I XILINX. Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-73
Figure 1-73: XCKU5P Banks in SFVB784 Package and XQKU5P Banks in SFRB784 Package
X-Ref Target - Figure 1-74
Figure 1-74: XCKU5P Banks in FFVD900 Package
HP I/O Bank 67
E
HD I/O Bank 87
F
CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
HD I/O Bank 86
G
SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 65
C
HD I/O Bank 85
IConfiguration
GTY Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 64
B
HD I/O Bank 84
H
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
A [R]
X15587-020817
HP I/O Bank 67
F
HD I/O Bank 87
K
CMAC
X0Y0
GTY Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
HD I/O Bank 86
L
SYSMON
Configuration
GTY Quad 226
X0Y8-X0Y11
C [R]
HP I/O Bank 65
C
HD I/O Bank 85
JConfiguration
GTY Quad 225
X0Y4-X0Y7
B [R] (RCAL)
HP I/O Bank 64
E
HD I/O Bank 84
I
PCIE4
X0Y0
(tandem)
GTY Quad 224
X0Y0-X0Y3
A [R]
X15589-020817
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
XCKU9P Bank Diagrams
X-Ref Target - Figure 1-75
Figure 1-75: XCKU9P Banks
GTH Quad 130
X0Y12-X0Y15 HD I/O Bank 50 GTH Quad 230
X1Y12-X1Y15
GTH Quad 129
X0Y8-X0Y11 HD I/O Bank 49 GTH Quad 229
X1Y8-X1Y11
GTH Quad 128
X0Y4-X0Y7
(RCAL)
HD I/O Bank 48
GTH Quad 228
X1Y4-X1Y7
(RCAL)
GTH Quad 127
X0Y0-X0Y3 HD I/O Bank47 HP I/O Bank 67
SYSMON
Configuration HP I/O Bank 66
Configuration HP I/O Bank 65
HD I/O Bank 44 HP I/O Bank 64
X15591-062217
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-76
Figure 1-76: XCKU9P Banks in FFVE900 Package
GTH Quad 130
X0Y12-X0Y15
G [L]
HD I/O Bank 50
GTH Quad 230
X1Y12-X1Y15
C [R]
GTH Quad 129
X0Y8-X0Y11
F [L]
HD I/O Bank 49
O
GTH Quad 229
X1Y8-X1Y11
B [R]
GTH Quad 128
X0Y4-X0Y7
E [L] (RCAL)
HD I/O Bank 48
N
GTH Quad 228
X1Y4-X1Y7
A [R] (RCAL)
GTH Quad 127
X0Y0-X0Y3
D [L]
HD I/O Bank47
G
HP I/O Bank 67
E
SYSMON
Configuration
HP I/O Bank 66
D
Configuration HP I/O Bank 65
C
HD I/O Bank 44
F
HP I/O Bank 64
B
X15592-062217
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
XCKU11P Bank Diagrams
X-Ref Target - Figure 1-77
Figure 1-77: XCKU11P Banks
GTY Quad 131
X0Y16-X0Y19
PCIE4
X0Y3 HP I/O Bank 71 HD I/O Bank 91 GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y8-X0Y11
(RCAL)
ILKN
X0Y0 HP I/O Bank 69 HD I/O Bank 89 GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y4-X0Y7
PCIE4
X0Y2 HP I/O Bank 68 HD I/O Bank 88 GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 67 PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
(RCAL)
HP I/O Bank 65 Configuration GTH Quad 225
X0Y4-X0Y7
HP I/O Bank 64
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X15593-020817
{I XILINXo Send Feedback
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X-Ref Target - Figure 1-78
Figure 1-78: XCKU11P Banks in FFVD900 Package
GTY Quad 131
X0Y16-X0Y19
PCIE4
X0Y3 HP I/O Bank 71 HD I/O Bank 91
K
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y12-X0Y15
CMAC
X0Y1
HP I/O Bank 70
H
HD I/O Bank 90
L
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y8-X0Y11
(RCAL)
ILKN
X0Y0
HP I/O Bank 69
G
HD I/O Bank 89
J
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y4-X0Y7
PCIE4
X0Y2
HP I/O Bank 68
F
HD I/O Bank 88
I
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 67
E
PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R] (RCAL)
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R]
HP I/O Bank 64
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
X15594-020817
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-79
Figure 1-79: XCKU11P Banks in FFVA1156 Package
GTY Quad 131
X0Y16-X0Y19
PCIE4
X0Y3
HP I/O Bank 71
FHD I/O Bank 91 GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y12-X0Y15 CMAC
X0Y1
HP I/O Bank 70
EHD I/O Bank 90 GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y8-X0Y11
F [L] (RCAL)
ILKN
X0Y0
HP I/O Bank 69
K
HD I/O Bank 89
R
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y4-X0Y7
PCIE4
X0Y2
HP I/O Bank 68
J
HD I/O Bank 88
R
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 67
G
PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R] (RCAL)
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R]
HP I/O Bank 64
H
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
G[L]
E [R]
X15595-062217
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-80
Figure 1-80: XCKU11P Banks in FFVE1517 Package
GTY Quad 131
X0Y16-X0Y19
M [L]
PCIE4
X0Y3
HP I/O Bank 71
R
HD I/O Bank 91
N
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y12-X0Y15
L [L]
CMAC
X0Y1
HP I/O Bank 70
S
HD I/O Bank 90
O
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y8-X0Y11
K [L] (RCAL)
ILKN
X0Y0
HP I/O Bank 69
T
HD I/O Bank 89
P
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y4-X0Y7
J [L]
PCIE4
X0Y2
HP I/O Bank 68
G
HD I/O Bank 88
Q
GTH Quad 228
X0Y16-X0Y19
E [RN]
GTY Quad 127
X0Y0-X0Y3
I [L]
CMAC
X0Y0
HP I/O Bank 67
F
PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
D [RS]
HP I/O Bank 66
E
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
HP I/O Bank 64
D
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X15597-020817
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
XCKU13P Bank Diagrams
X-Ref Target - Figure 1-81
Figure 1-81: XCKU13P Banks
GTH Quad 130
X0Y12-X0Y15 HD I/O Bank 50 GTH Quad 230
X1Y12-X1Y15
GTH Quad 129
X0Y8-X0Y11 HD I/O Bank 49 GTH Quad 229
X1Y8-X1Y11
GTH Quad 128
X0Y4-X0Y7
(RCAL)
HD I/O Bank 48
GTH Quad 228
X1Y4-X1Y7
(RCAL)
GTH Quad 127
X0Y0-X0Y3 HD I/O Bank47 HP I/O Bank 67
SYSMON
Configuration HP I/O Bank 66
Configuration HP I/O Bank 65
HD I/O Bank 44 HP I/O Bank 64
X15598-062217
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-82
Figure 1-82: XCKU13P Banks in FFVE900 Package
GTH Quad 130
X0Y12-X0Y15
G [L]
HD I/O Bank 50
GTH Quad 230
X1Y12-X1Y15
C [R]
GTH Quad 129
X0Y8-X0Y11
F [L]
HD I/O Bank 49
O
GTH Quad 229
X1Y8-X1Y11
B [R]
GTH Quad 128
X0Y4-X0Y7
E [L] (RCAL)
HD I/O Bank 48
N
GTH Quad 228
X1Y4-X1Y7
A [R] (RCAL)
GTH Quad 127
X0Y0-X0Y3
D [L]
HD I/O Bank47
G
HP I/O Bank 67
E
SYSMON
Configuration
HP I/O Bank 66
D
Configuration HP I/O Bank 65
C
HD I/O Bank 44
F
HP I/O Bank 64
B
X15599-062217
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
XCKU15P and XQKU15P Bank Diagrams
X-Ref Target - Figure 1-83
Figure 1-83: XCKU15P and XQKU15P Banks
GTY Quad 134
X0Y28-X0Y31
CMAC
X0Y3 HP I/O Bank 74 HD I/O Bank 94 GTH Quad 234
X0Y40-X0Y43
GTY Quad 133
X0Y24-X0Y27
ILKN
X0Y2 HP I/O Bank 73 HD I/O Bank 93 GTH Quad 233
X0Y36-X0Y39
GTY Quad 132
X0Y20-X0Y23
CMAC
X0Y2 HP I/O Bank 72 ILKN
X1Y1
GTH Quad 232
X0Y32-X0Y35
GTY Quad 131
X0Y16-X0Y19
PCIE4
X0Y3 HP I/O Bank 71 HD I/O Bank 91 GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y12-X0Y15
CMAC
X0Y1 HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y8-X0Y11
(RCAL)
ILKN
X0Y0 HP I/O Bank 69 ILKN
X1Y0
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y4-X0Y7
PCIE4
X0Y2 HP I/O Bank 68 PCIE4
X1Y2
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 67 PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
HP I/O Bank 66 SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
(RCAL)
HP I/O Bank 65 Configuration GTH Quad 225
X0Y4-X0Y7
HP I/O Bank 64
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
X15600-062217
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-84
Figure 1-84: XCKU15P Banks in FFVA1156 Package and XQKU15P in FFRA1156 Package
GTY Quad 134
X0Y28-X0Y31
CMAC
X0Y3 HP I/O Bank 74 HD I/O Bank 94 GTH Quad 234
X0Y40-X0Y43
GTY Quad 133
X0Y24-X0Y27
ILKN
X0Y2 HP I/O Bank 73 HD I/O Bank 93 GTH Quad 233
X0Y36-X0Y39
GTY Quad 132
X0Y20-X0Y23
CMAC
X0Y2
HP I/O Bank 72
F
ILKN
X1Y1
GTH Quad 232
X0Y32-X0Y35
GTY Quad 131
X0Y16-X0Y19
PCIE4
X0Y3
HP I/O Bank 71
E
HD I/O Bank 91
R
GTH Quad 231
X0Y28-X0Y31
GTY Quad 130
X0Y12-X0Y15 CMAC
X0Y1
HP I/O Bank 70
K
HD I/O Bank 90
R
GTH Quad 230
X0Y24-X0Y27
GTY Quad 129
X0Y8-X0Y11
F[L] (RCAL)
ILKN
X0Y0
HP I/O Bank 69
J
ILKN
X1Y0
GTH Quad 229
X0Y20-X0Y23
GTY Quad 128
X0Y4-X0Y7
PCIE4
X0Y2
HP I/O Bank 68
I
PCIE4
X1Y2
GTH Quad 228
X0Y16-X0Y19
GTY Quad 127
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 67
G
PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
D [R]
HP I/O Bank 66
D
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [R] (RCAL)
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [R]
HP I/O Bank 64
H
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [R]
G[L]
E [R]
X15601-062217
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-85
Figure 1-85: XCKU15P Banks in FFVE1517 Package and XQKU15P Banks in FFRE1517 Package
GTY Quad 134
X0Y28-X0Y31
CMAC
X0Y3 HP I/O Bank 74 HD I/O Bank 94
N
GTH Quad 234
X0Y40-X0Y43
GTY Quad 133
X0Y24-X0Y27
ILKN
X0Y2 HP I/O Bank 73 HD I/O Bank 93
O
GTH Quad 233
X0Y36-X0Y39
GTY Quad 132
X0Y20-X0Y23
N [L]
CMAC
X0Y2 HP I/O Bank 72 ILKN
X1Y1
GTH Quad 232
X0Y32-X0Y35
GTY Quad 131
X0Y16-X0Y19
M [L]
PCIE4
X0Y3
HP I/O Bank 71
R
HD I/O Bank 91
P
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y12-X0Y15
L [L]
CMAC
X0Y1
HP I/O Bank 70
S
HD I/O Bank 90
Q
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y8-X0Y11
K [L] (RCAL)
ILKN
X0Y0
HP I/O Bank 69
T
ILKN
X1Y0
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y4-X0Y7
J [L]
PCIE4
X0Y2
HP I/O Bank 68
G
PCIE4
X1Y2
GTH Quad 228
X0Y16-X0Y19
E [RN]
GTY Quad 127
X0Y0-X0Y3
I [L]
CMAC
X0Y0
HP I/O Bank 67
F
PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
D [RS]
HP I/O Bank 66
E
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
HP I/O Bank 64
D
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X15602-062217
{I XILINXo Send Feedback
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-86
Figure 1-86: XCKU15P Banks in FFVA1760 Package
GTY Quad 134
X0Y28-X0Y31
S [LN]
CMAC
X0Y3 HP I/O Bank 74 HD I/O Bank 94
N
GTH Quad 234
X0Y40-X0Y43
K [RN]
GTY Quad 133
X0Y24-X0Y27
R [LN]
ILKN
X0Y2 HP I/O Bank 73 HD I/O Bank 93
O
GTH Quad 233
X0Y36-X0Y39
J [RN]
GTY Quad 132
X0Y20-X0Y23
Q [LN]
CMAC
X0Y2
HP I/O Bank 72
R
ILKN
X1Y1
GTH Quad 232
X0Y32-X0Y35
I [RN]
GTY Quad 131
X0Y16-X0Y19
P [LN]
PCIE4
X0Y3
HP I/O Bank 71
S
HD I/O Bank 91
P
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y12-X0Y15
O [LS]
CMAC
X0Y1
HP I/O Bank 70
T
HD I/O Bank 90
Q
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y8-X0Y11
N [LS] (RCAL)
ILKN
X0Y0 HP I/O Bank 69 ILKN
X1Y0
GTH Quad 229
X0Y20-X0Y23
F [RS]
GTY Quad 128
X0Y4-X0Y7
M [LS]
PCIE4
X0Y2
HP I/O Bank 68
G
PCIE4
X1Y2
GTH Quad 228
X0Y16-X0Y19
E [RS]
GTY Quad 127
X0Y0-X0Y3
L [LS]
CMAC
X0Y0
HP I/O Bank 67
F
PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
D [RS]
HP I/O Bank 66
E
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
HP I/O Bank 64
D
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X15604-062217
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-87
Figure 1-87: XCKU15P Banks in FFVE1760 Package
GTY Quad 134
X0Y28-X0Y31
CMAC
X0Y3
HP I/O Bank 74
R
HD I/O Bank 94
N
GTH Quad 234
X0Y40-X0Y43
GTY Quad 133
X0Y24-X0Y27
ILKN
X0Y2
HP I/O Bank 73
S
HD I/O Bank 93
O
GTH Quad 233
X0Y36-X0Y39
GTY Quad 132
X0Y20-X0Y23
N [L]
CMAC
X0Y2
HP I/O Bank 72
T
ILKN
X1Y1
GTH Quad 232
X0Y32-X0Y35
GTY Quad 131
X0Y16-X0Y19
M [L]
PCIE4
X0Y3
HP I/O Bank 71
U
HD I/O Bank 91
P
GTH Quad 231
X0Y28-X0Y31
H [RN]
GTY Quad 130
X0Y12-X0Y15
L [L]
CMAC
X0Y1
HP I/O Bank 70
V
HD I/O Bank 90
Q
GTH Quad 230
X0Y24-X0Y27
G [RN]
GTY Quad 129
X0Y8-X0Y11
K [L] (RCAL)
ILKN
X0Y0
HP I/O Bank 69
H
ILKN
X1Y0
GTH Quad 229
X0Y20-X0Y23
F [RN]
GTY Quad 128
X0Y4-X0Y7
J [L]
PCIE4
X0Y2
HP I/O Bank 68
G
PCIE4
X1Y2
GTH Quad 228
X0Y16-X0Y19
E [RN]
GTY Quad 127
X0Y0-X0Y3
I [L]
CMAC
X0Y0
HP I/O Bank 67
F
PCIE4
X1Y1
GTH Quad 227
X0Y12-X0Y15
D [RS]
HP I/O Bank 66
E
SYSMON
Configuration
GTH Quad 226
X0Y8-X0Y11
C [RS] (RCAL)
HP I/O Bank 65
CConfiguration
GTH Quad 225
X0Y4-X0Y7
B [RS]
HP I/O Bank 64
D
PCIE4
X1Y0
(tandem)
GTH Quad 224
X0Y0-X0Y3
A [RS]
X15603-062217
XILINXG Send Feed back
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Chapter 1: Packaging Overview
XCVU3P and XQVU3P Bank Diagrams
X-Ref Target - Figure 1-88
Figure 1-88: XCVU3P and XQVU3P Banks
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
GTY Quad 127
X0Y12-X0Y15
PCIE4
X0Y1 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
GTY Quad 126
X0Y8-X0Y11
(RCAL)
CMAC
X0Y1 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
(RCAL)
GTY Quad 125
X0Y4-X0Y7
ILKN
X0Y0 HP I/O Bank 45 HP I/O Bank 65 Configuration GTY Quad 225
X1Y4-X1Y7
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 44 HP I/O Bank 64
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
X15605-020817
X-Ref Target - Figure 1-89
Figure 1-89: XCVU3P Banks in FFVC1517 Package and XQVU3P Banks in FFRC1517 Package
GTY Quad 128
X0Y16-X0Y19
J [L]
CMAC
X0Y2
HP I/O Bank 48
K
HP I/O Bank 68
F
ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
E [R]
GTY Quad 127
X0Y12-X0Y15
I [L]
PCIE4
X0Y1
HP I/O Bank 47
J
HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [R]
GTY Quad 126
X0Y8-X0Y11
H [L] (RCAL)
CMAC
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [R] (RCAL)
GTY Quad 125
X0Y4-X0Y7
G [L]
ILKN
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [R]
GTY Quad 124
X0Y0-X0Y3
F [L]
CMAC
X0Y0
HP I/O Bank 44
G
HP I/O Bank 64
B
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [R]
X15606-020817
XILINXG Send Feed back
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Chapter 1: Packaging Overview
XCVU5P Bank Diagrams
X-Ref Target - Figure 1-90
Figure 1-90: XCVU5P Banks
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
GTY Quad 132
X0Y32-X0Y35
PCIE4
X0Y3 HP I/O Bank 52 HP I/O Bank 72 ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
GTY Quad 131
X0Y28-X0Y31
(RCAL)
CMAC
X0Y4 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
(RCAL)
GTY Quad 130
X0Y24-X0Y27
ILKN
X0Y3 HP I/O Bank 50 HP I/O Bank 70 Configuration GTY Quad 230
X1Y24-X1Y27
GTY Quad 129
X0Y20-X0Y23
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
GTY Quad 127
X0Y12-X0Y15
PCIE4
X0Y1 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
GTY Quad 126
X0Y8-X0Y11
(RCAL)
CMAC
X0Y1 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y1
(RCAL)
GTY Quad 125
X0Y4-X0Y7
ILKN
X0Y0 HP I/O Bank 45 HP I/O Bank 65 Configuration GTY Quad 225
X1Y4-X1Y7
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 44 HP I/O Bank 64
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
SLR Crossing
X18708-020817
(I XILINXa Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-91
Figure 1-91: XCVU5P Banks in FLVA2104 Package
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5
HP I/O Bank 53
M
HP I/O Bank 73
Q
ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
G [RN]
GTY Quad 132
X0Y32-X0Y35
M [LN]
PCIE4
X0Y3
HP I/O Bank 52
L
HP I/O Bank 72
P
ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
F [RN]
GTY Quad 131
X0Y28-X0Y31
L [LN] (RCAL)
CMAC
X0Y4
HP I/O Bank 51
K
HP I/O Bank 71
O
SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
E [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
K [LN]
ILKN
X0Y3
HP I/O Bank 50
J
HP I/O Bank 70
NConfiguration GTY Quad 230
X1Y24-X1Y27
GTY Quad 129
X0Y20-X0Y23
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
GTY Quad 127
X0Y12-X0Y15
J [LS]
PCIE4
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
I [LS] (RCAL)
CMAC
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
H [LS]
ILKN
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 44
F
HP I/O Bank 64
B
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X18709-020817
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 134
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-92
Figure 1-92: XCVU5P Banks in FLVB2104 Package
GTY Quad 133
X0Y36-X0Y39
S [LN]
CMAC
X0Y5 HP I/O Bank 53
J
HP I/O Bank 73 ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
J [RN]
GTY Quad 132
X0Y32-X0Y35
R [LN]
PCIE4
X0Y3
HP I/O Bank 52
L
HP I/O Bank 72
O
ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
Q [LN] (RCAL)
CMAC
X0Y4
HP I/O Bank 51
K
HP I/O Bank 71
N
SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
P [LN]
ILKN
X0Y3
HP I/O Bank 50 HP I/O Bank 70
MConfiguration
GTY Quad 230
X1Y24-X1Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
O [LN]
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
N [LS]
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68
F (Partial)
ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
M [LS]
PCIE4
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
L [LS] (RCAL)
CMAC
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
K [LS]
ILKN
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 44
G
HP I/O Bank 64
B
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X16504-020817
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 135
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-93
Figure 1-93: XCVU5P Banks in FLVC2104 Package
GTY Quad 133
X0Y36-X0Y39
W [LN]
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
J [RN]
GTY Quad 132
X0Y32-X0Y35
V [LN]
PCIE4
X0Y3 HP I/O Bank 52 HP I/O Bank 72
I
ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
U [LN] (RCAL)
CMAC
X0Y4 HP I/O Bank 51 HP I/O Bank 71
H
SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
T [LN]
ILKN
X0Y3 HP I/O Bank 50 HP I/O Bank 70
GConfiguration
GTY Quad 230
X1Y24-X1Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
S [LN]
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
R [LC]
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68
F
ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
E [RC]
GTY Quad 127
X0Y12-X0Y15
Q [LC]
PCIE4
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RC]
GTY Quad 126
X0Y8-X0Y11
P [LC] (RCAL)
CMAC
X0Y1 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RC] (RCAL)
GTY Quad 125
X0Y4-X0Y7
O [LC]
ILKN
X0Y0 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RC]
GTY Quad 124
X0Y0-X0Y3
N [LC]
CMAC
X0Y0 HP I/O Bank 44 HP I/O Bank 64
B
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RC]
SLR Crossing
X16505-020817
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 136
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Chapter 1: Packaging Overview
XCVU7P and XQVU7P Bank Diagrams
X-Ref Target - Figure 1-94
Figure 1-94: XCVU7P and XQVU7P Banks
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
GTY Quad 132
X0Y32-X0Y35
PCIE4
X0Y3 HP I/O Bank 52 HP I/O Bank 72 ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
GTY Quad 131
X0Y28-X0Y31
(RCAL)
CMAC
X0Y4 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
(RCAL)
GTY Quad 130
X0Y24-X0Y27
ILKN
X0Y3 HP I/O Bank 50 HP I/O Bank 70 Configuration GTY Quad 230
X1Y24-X1Y27
GTY Quad 129
X0Y20-X0Y23
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
GTY Quad 127
X0Y12-X0Y15
PCIE4
X0Y1 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
GTY Quad 126
X0Y8-X0Y11
(RCAL)
CMAC
X0Y1 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
(RCAL)
GTY Quad 125
X0Y4-X0Y7
ILKN
X0Y0 HP I/O Bank 45 HP I/O Bank 65 Configuration GTY Quad 225
X1Y4-X1Y7
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 44 HP I/O Bank 64
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
SLR Crossing
X15607-020817
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 137
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-95
Figure 1-95: XCVU7P Banks in FLVA2104 Package and XQVU7P in FLRA2104 Package
GTY Quad 133
X0Y36-X0Y39
CMAC
X0Y5
HP I/O Bank 53
M
HP I/O Bank 73
Q
ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
G [RN]
GTY Quad 132
X0Y32-X0Y35
M [LN]
PCIE4
X0Y3
HP I/O Bank 52
L
HP I/O Bank 72
P
ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
F [RN]
GTY Quad 131
X0Y28-X0Y31
L [LN] (RCAL)
CMAC
X0Y4
HP I/O Bank 51
K
HP I/O Bank 71
O
SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
E [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
K [LN]
ILKN
X0Y3
HP I/O Bank 50
J
HP I/O Bank 70
NConfiguration GTY Quad 230
X1Y24-X1Y27
GTY Quad 129
X0Y20-X0Y23
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68 ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
GTY Quad 127
X0Y12-X0Y15
J [LS]
PCIE4
X0Y1
HP I/O Bank 47
I
HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
I [LS] (RCAL)
CMAC
X0Y1
HP I/O Bank 46
H
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
H [LS]
ILKN
X0Y0
HP I/O Bank 45
G
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 44
F
HP I/O Bank 64
B
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X15608-020817
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 138
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-96
Figure 1-96: XCVU7P Banks in FLVB2104 Package and XQVU7P in FLRB2104 Package
GTY Quad 133
X0Y36-X0Y39
S [LN]
CMAC
X0Y5 HP I/O Bank 53
J
HP I/O Bank 73 ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
J [RN]
GTY Quad 132
X0Y32-X0Y35
R [LN]
PCIE4
X0Y3
HP I/O Bank 52
L
HP I/O Bank 72
O
ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
Q [LN] (RCAL)
CMAC
X0Y4
HP I/O Bank 51
K
HP I/O Bank 71
N
SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
P [LN]
ILKN
X0Y3
HP I/O Bank 50 HP I/O Bank 70
MConfiguration
GTY Quad 230
X1Y24-X1Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
O [LN]
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
N [LS]
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68
F (Partial)
ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
M [LS]
PCIE4
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y08-X0Y11
L [LS] (RCAL)
CMAC
X0Y1
HP I/O Bank 46
I
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS] (RCAL)
GTY Quad 125
X0Y4-X0Y7
K [LS]
ILKN
X0Y0
HP I/O Bank 45
H
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS]
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 44
G
HP I/O Bank 64
B
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
X15609-020817
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 139
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-97
Figure 1-97: XCVU7P Banks in FLVC2104 Package
GTY Quad 133
X0Y36-X0Y39
W [LN]
CMAC
X0Y5 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y5
GTY Quad 233
X1Y36-X1Y39
J [RN]
GTY Quad 132
X0Y32-X0Y35
V [LN]
PCIE4
X0Y3 HP I/O Bank 52 HP I/O Bank 72
I
ILKN
X1Y4
GTY Quad 232
X1Y32-X1Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
U [LN] (RCAL)
CMAC
X0Y4 HP I/O Bank 51 HP I/O Bank 71
H
SYSMON
Configuration
GTY Quad 231
X1Y28-X1Y31
H [RN] (RCAL)
GTY Quad 130
X0Y24-X0Y27
T [LN]
ILKN
X0Y3 HP I/O Bank 50 HP I/O Bank 70
GConfiguration
GTY Quad 230
X1Y24-X1Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
S [LN]
CMAC
X0Y3 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y2
GTY Quad 229
X1Y20-X1Y23
F [RN]
GTY Quad 128
X0Y16-X0Y19
R [LC]
CMAC
X0Y2 HP I/O Bank 48 HP I/O Bank 68
F
ILKN
X1Y2
GTY Quad 228
X1Y16-X1Y19
E [RC]
GTY Quad 127
X0Y12-X0Y15
Q [LC]
PCIE4
X0Y1 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RC]
GTY Quad 126
X0Y8-X0Y11
P [LC] (RCAL)
CMAC
X0Y1 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RC] (RCAL)
GTY Quad 125
X0Y4-X0Y7
O [LC]
ILKN
X0Y0 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RC]
GTY Quad 124
X0Y0-X0Y3
N [LC]
CMAC
X0Y0 HP I/O Bank 44 HP I/O Bank 64
B
PCIE4
X1Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RC]
SLR Crossing
X15610-020817
(I XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 140
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Chapter 1: Packaging Overview
XCVU9P Bank Diagrams
X-Ref Target - Figure 1-98
Figure 1-98: XCVU9P Banks
GTY Quad 133
X0Y56-X0Y59
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y8
GTY Quad 233
X1Y56-X1Y59
GTY Quad 132
X0Y52-X0Y55
PCIE4
X0Y5 HP I/O Bank 52 HP I/O Bank 72 ILKN
X1Y7
GTY Quad 232
X1Y52-X1Y55
GTY Quad 131
X0Y48-X0Y51
(RCAL)
CMAC
X0Y7 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTY Quad 231
X1Y48-X1Y51
(RCAL)
GTY Quad 130
X0Y44-X0Y47
ILKN
X0Y6 HP I/O Bank 50 HP I/O Bank 70 Configuration GTY Quad 230
X1Y44-X1Y47
GTY Quad 129
X0Y40-X0Y43
CMAC
X0Y6 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y4
GTY Quad 229
X1Y40-X1Y43
GTY Quad 128
X0Y36-X0Y39
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68 ILKN
X1Y5
GTY Quad 228
X1Y36-X1Y39
GTY Quad 127
X0Y32-X0Y35
PCIE4
X0Y3 HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y4
GTY Quad 227
X1Y32-X1Y35
GTY Quad 126
X0Y28-X0Y31
(RCAL)
CMAC
X0Y4 HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y28-X1Y31
(RCAL)
GTY Quad 125
X0Y24-X0Y27
ILKN
X0Y3 HP I/O Bank 45 HP I/O Bank 65 Configuration GTY Quad 225
X1Y24-X1Y27
GTY Quad 124
X0Y20-X0Y23
CMAC
X0Y3 HP I/O Bank 44 HP I/O Bank 64
PCIE4
X1Y2
(tandem)
GTY Quad 224
X1Y20-X1Y23
GTY Quad 123
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 ILKN
X1Y2
GTY Quad 223
X1Y16-X1Y19
GTY Quad 122
X0Y12-X0Y15
PCIE4
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y1
GTY Quad 222
X1Y12-X1Y15
GTY Quad 121
X0Y8-X0Y11
(RCAL)
CMAC
X0Y1 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTY Quad 221
X1Y8-X1Y11
(RCAL)
GTY Quad 120
X0Y4-X0Y7
ILKN
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration GTY Quad 220
X1Y4-X1Y7
GTY Quad 119
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 39 HP I/O Bank 59 PCIE4
X1Y0
GTY Quad 219
X1Y0-X1Y3
SLR Crossing
SLR Crossing
X15611-020817
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 141
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-99
Figure 1-99: XCVU9P Banks in FLGA2104 Package
GTY Quad 133
X0Y56-X0Y59
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73
Q
ILKN
X1Y8
GTY Quad 233
X1Y56-X1Y59
G [RN]
GTY Quad 132
X0Y52-X0Y55
PCIE4
X0Y5 HP I/O Bank 52 HP I/O Bank 72
P
ILKN
X1Y7
GTY Quad 232
X1Y52-X1Y55
F [RN]
GTY Quad 131
X0Y48-X0Y51
(RCAL)
CMAC
X0Y7 HP I/O Bank 51 HP I/O Bank 71
O
SYSMON
Configuration
GTY Quad 231
X1Y48-X1Y51
E [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
ILKN
X0Y6 HP I/O Bank 50 HP I/O Bank 70
NConfiguration GTY Quad 230
X1Y44-X1Y47
GTY Quad 129
X0Y40-X0Y43
CMAC
X0Y6 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y4
GTY Quad 229
X1Y40-X1Y43
GTY Quad 128
X0Y36-X0Y39
CMAC
X0Y5
HP I/O Bank 48
MHP I/O Bank 68 ILKN
X1Y5
GTY Quad 228
X1Y36-X1Y39
GTY Quad 127
X0Y32-X0Y35
M [LN]
PCIE4
X0Y3
HP I/O Bank 47
L
HP I/O Bank 67
E
ILKN
X1Y4
GTY Quad 227
X1Y32-X1Y35
D [RS]
GTY Quad 126
X0Y28-X0Y31
L [LN] (RCAL)
CMAC
X0Y4
HP I/O Bank 46
K
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y28-X1Y31
C [RS] (RCAL)
GTY Quad 125
X0Y24-X0Y27
K [LN]
ILKN
X0Y3
HP I/O Bank 45
J
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y24-X1Y27
B [RS]
GTY Quad 124
X0Y20-X0Y23
CMAC
X0Y3 HP I/O Bank 44 HP I/O Bank 64
B
PCIE4
X1Y2
(tandem)
GTY Quad 224
X1Y20-X1Y23
A [RS]
GTY Quad 123
X0Y16-X0Y19
CMAC
X0Y2
HP I/O Bank 43
IHP I/O Bank 63 ILKN
X1Y2
GTY Quad 223
X1Y16-X1Y19
GTY Quad 122
X0Y12-X0Y15
J [LS]
PCIE4
X0Y1
HP I/O Bank 42
HHP I/O Bank 62 ILKN
X1Y1
GTY Quad 222
X1Y12-X1Y15
GTY Quad 121
X0Y8-X0Y11
I [LS] (RCAL)
CMAC
X0Y1
HP I/O Bank 41
GHP I/O Bank 61 SYSMON
Configuration
GTY Quad 221
X1Y8-X1Y11
(RCAL)
GTY Quad 120
X0Y4-X0Y7
H [LS]
ILKN
X0Y0
HP I/O Bank 40
FHP I/O Bank 60 Configuration GTY Quad 220
X1Y4-X1Y7
GTY Quad 119
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 39 HP I/O Bank 59 PCIE4
X1Y0
GTY Quad 219
X1Y0-X1Y3
SLR Crossing
SLR Crossing
X15612-020817
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 142
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-100
Figure 1-100: XCVU9P Banks in FLGB2104 Package
GTY Quad 133
X0Y56-X0Y59
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y8
GTY Quad 233
X1Y56-X1Y59
J [RN]
GTY Quad 132
X0Y52-X0Y55
PCIE4
X0Y5 HP I/O Bank 52 HP I/O Bank 72
O
ILKN
X1Y7
GTY Quad 232
X1Y52-X1Y55
I [RN]
GTY Quad 131
X0Y48-X0Y51
(RCAL)
CMAC
X0Y7 HP I/O Bank 51 HP I/O Bank 71
N
SYSMON
Configuration
GTY Quad 231
X1Y48-X1Y51
H [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
ILKN
X0Y6 HP I/O Bank 50 HP I/O Bank 70
MConfiguration
GTY Quad 230
X1Y44-X1Y47
G [RN]
GTY Quad 129
X0Y40-X0Y43
CMAC
X0Y6 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y4
GTY Quad 229
X1Y40-X1Y43
F [RN]
GTY Quad 128
X0Y36-X0Y39
S [LN]
CMAC
X0Y5
HP I/O Bank 48
L
HP I/O Bank 68
F (Partial)
ILKN
X1Y5
GTY Quad 228
X1Y36-X1Y39
E [RS]
GTY Quad 127
X0Y32-X0Y35
R [LN]
PCIE4
X0Y3
HP I/O Bank 47
K
HP I/O Bank 67
E
ILKN
X1Y4
GTY Quad 227
X1Y32-X1Y35
D [RS]
GTY Quad 126
X0Y28-X0Y31
Q [LN] (RCAL)
CMAC
X0Y4
HP I/O Bank 46
J
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y28-X1Y31
C [RS] (RCAL)
GTY Quad 125
X0Y24-X0Y27
P [LN]
ILKN
X0Y3 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y24-X1Y27
B [RS]
GTY Quad 124
X0Y20-X0Y23
O [LN]
CMAC
X0Y3 HP I/O Bank 44 HP I/O Bank 64
B
PCIE4
X1Y2
(tandem)
GTY Quad 224
X1Y20-X1Y23
A [RS]
GTY Quad 123
X0Y16-X0Y19
N [LS]
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 ILKN
X1Y2
GTY Quad 223
X1Y16-X1Y19
GTY Quad 122
X0Y12-X0Y15
M [LS]
PCIE4
X0Y1
HP I/O Bank 42
IHP I/O Bank 62 ILKN
X1Y1
GTY Quad 222
X1Y12-X1Y15
GTY Quad 121
X0Y8-X0Y11
L [LS] (RCAL)
CMAC
X0Y1
HP I/O Bank 41
HHP I/O Bank 61 SYSMON
Configuration
GTY Quad 221
X1Y8-X1Y11
(RCAL)
GTY Quad 120
X0Y4-X0Y7
K [LS]
ILKN
X0Y0
HP I/O Bank 40
GHP I/O Bank 60 Configuration GTY Quad 220
X1Y4-X1Y7
GTY Quad 119
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 39 HP I/O Bank 59 PCIE4
X1Y0
GTY Quad 219
X1Y0-X1Y3
SLR Crossing
SLR Crossing
X15613-020817
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 143
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-101
Figure 1-101: XCVU9P Banks in FLGC2104 Package
GTY Quad 133
X0Y56-X0Y59
W [LN]
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y8
GTY Quad 233
X1Y56-X1Y59
J [RN]
GTY Quad 132
X0Y52-X0Y55
V [LN]
PCIE4
X0Y5 HP I/O Bank 52 HP I/O Bank 72
I
ILKN
X1Y7
GTY Quad 232
X1Y52-X1Y55
I [RN]
GTY Quad 131
X0Y48-X0Y51
U [LN] (RCAL)
CMAC
X0Y7 HP I/O Bank 51 HP I/O Bank 71
H
SYSMON
Configuration
GTY Quad 231
X1Y48-X1Y51
H [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
T [LN]
ILKN
X0Y6 HP I/O Bank 50 HP I/O Bank 70
GConfiguration
GTY Quad 230
X1Y44-X1Y47
G [RN]
GTY Quad 129
X0Y40-X0Y43
S [LN]
CMAC
X0Y6 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y4
GTY Quad 229
X1Y40-X1Y43
F [RN]
GTY Quad 128
X0Y36-X0Y39
R [LC]
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68
F
ILKN
X1Y5
GTY Quad 228
X1Y36-X1Y39
E [RC]
GTY Quad 127
X0Y32-X0Y35
Q [LC]
PCIE4
X0Y3 HP I/O Bank 47 HP I/O Bank 67
E
ILKN
X1Y4
GTY Quad 227
X1Y32-X1Y35
D [RC]
GTY Quad 126
X0Y28-X0Y31
P [LC] (RCAL)
CMAC
X0Y4 HP I/O Bank 46 HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y28-X1Y31
C [RC] (RCAL)
GTY Quad 125
X0Y24-X0Y27
O [LC]
ILKN
X0Y3 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y24-X1Y27
B [RC]
GTY Quad 124
X0Y20-X0Y23
N [LC]
CMAC
X0Y3 HP I/O Bank 44 HP I/O Bank 64
B
PCIE4
X1Y2
(tandem)
GTY Quad 224
X1Y20-X1Y23
A [RC]
GTY Quad 123
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 ILKN
X1Y2
GTY Quad 223
X1Y16-X1Y19
GTY Quad 122
X0Y12-X0Y15
Z [LS]
PCIE4
X0Y1 HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y1
GTY Quad 222
X1Y12-X1Y15
M [RS]
GTY Quad 121
X0Y8-X0Y11
Y [LS] (RCAL)
CMAC
X0Y1 HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTY Quad 221
X1Y8-X1Y11
L [RS] (RCAL)
GTY Quad 120
X0Y4-X0Y7
X [LS]
ILKN
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration
GTY Quad 220
X1Y4-X1Y7
K [RS]
GTY Quad 119
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 39 HP I/O Bank 59 PCIE4
X1Y0
GTY Quad 219
X1Y0-X1Y3
SLR Crossing
SLR Crossing
X15614-020817
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 144
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-102
Figure 1-102: XCVU9P Banks in FSGD2104 Package
GTY Quad 133
X0Y56-X0Y59
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y8
GTY Quad 233
X1Y56-X1Y59
GTY Quad 132
X0Y52-X0Y55
PCIE4
X0Y5 HP I/O Bank 52 HP I/O Bank 72 ILKN
X1Y7
GTY Quad 232
X1Y52-X1Y55
GTY Quad 131
X0Y48-X0Y51
S [LN] (RCAL)
CMAC
X0Y7 HP I/O Bank 51 HP I/O Bank 71 SYSMON
Configuration
GTY Quad 231
X1Y48-X1Y51
H [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
ILKN
X0Y6 HP I/O Bank 50 HP I/O Bank 70 Configuration
GTY Quad 230
X1Y44-X1Y47
GTY Quad 129
X0Y40-X0Y43
CMAC
X0Y6 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y4
GTY Quad 229
X1Y40-X1Y43
GTY Quad 128
X0Y36-X0Y39
CMAC
X0Y5
HP I/O Bank 48 HP I/O Bank 68 ILKN
X1Y5
GTY Quad 228
X1Y36-X1Y39
GTY Quad 127
X0Y32-X0Y35 PCIE4
X0Y3
HP I/O Bank 47 HP I/O Bank 67 ILKN
X1Y4
GTY Quad 227
X1Y32-X1Y35
GTY Quad 126
X0Y28-X0Y31
Q [LN] (RCAL)
CMAC
X0Y4
HP I/O Bank 46 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y28-X1Y31
C [RS] (RCAL)
GTY Quad 125
X0Y24-X0Y27 ILKN
X0Y3 HP I/O Bank 45 HP I/O Bank 65 Configuration
GTY Quad 225
X1Y24-X1Y27
GTY Quad 124
X0Y20-X0Y23 CMAC
X0Y3 HP I/O Bank 44 HP I/O Bank 64 PCIE4
X1Y2
(tandem)
GTY Quad 224
X1Y20-X1Y23
GTY Quad 123
X0Y16-X0Y19
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63 ILKN
X1Y2
GTY Quad 223
X1Y16-X1Y19
GTY Quad 122
X0Y12-X0Y15 PCIE4
X0Y1
HP I/O Bank 42 HP I/O Bank 62 ILKN
X1Y1
GTY Quad 222
X1Y12-X1Y15
GTY Quad 121
X0Y8-X0Y11
L [LS](RCAL)
CMAC
X0Y1
HP I/O Bank 41 HP I/O Bank 61 SYSMON
Configuration
GTY Quad 221
X1Y8-X1Y11
GTY Quad 120
X0Y4-X0Y7 ILKN
X0Y0
HP I/O Bank 40 HP I/O Bank 60 Configuration GTY Quad 220
X1Y4-X1Y7
GTY Quad 119
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 39 HP I/O Bank 59 PCIE4
X1Y0
GTY Quad 219
X1Y0-X1Y3
SLR Crossing
SLR Crossing
J [RN]
I [RN]
G [RN]
F [RN]
O
N
M
E
D
C
B
E [RS]
R [LN] D [RS]
P [LN] B [RS]
O [LN] A [RS]
M [LS]
K [LS]
N [LS]
L
K
J
H
G
F
X18713-020817
XILINXG III Send Feed back
UltraScale Device Packaging and Pinouts 145
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-103
Figure 1-103: XCVU9P Banks in FLGA2577 Package
GTY Quad 133
X0Y56-X0Y59
Z [LN]
CMAC
X0Y8 HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y8
GTY Quad 233
X1Y56-X1Y59
J [RN]
GTY Quad 132
X0Y52-X0Y55
Y [LN]
PCIE4
X0Y5 HP I/O Bank 52 HP I/O Bank 72
K
ILKN
X1Y7
GTY Quad 232
X1Y52-X1Y55
I [RN]
GTY Quad 131
X0Y48-X0Y51
X [LN] (RCAL)
CMAC
X0Y7 HP I/O Bank 51 HP I/O Bank 71
J
SYSMON
Configuration
GTY Quad 231
X1Y48-X1Y51
H [RN] (RCAL)
GTY Quad 130
X0Y44-X0Y47
W [LUC]
ILKN
X0Y6 HP I/O Bank 50 HP I/O Bank 70
IConfiguration
GTY Quad 230
X1Y44-X1Y47
G [RUC]
GTY Quad 129
X0Y40-X0Y43
V [LUC]
CMAC
X0Y6 HP I/O Bank 49 HP I/O Bank 69 PCIE4
X1Y4
GTY Quad 229
X1Y40-X1Y43
F [RUC]
GTY Quad 128
X0Y36-X0Y39
U [LUC]
CMAC
X0Y5 HP I/O Bank 48 HP I/O Bank 68
H (Partial)
ILKN
X1Y5
GTY Quad 228
X1Y36-X1Y39
E [RUC]
GTY Quad 127
X0Y32-X0Y35
T [LUC]
PCIE4
X0Y3 HP I/O Bank 47 HP I/O Bank 67
G
ILKN
X1Y4
GTY Quad 227
X1Y32-X1Y35
D [RUC]
GTY Quad 126
X0Y28-X0Y31
S [LLC] (RCAL)
CMAC
X0Y4 HP I/O Bank 46 HP I/O Bank 66
B (Partial)
SYSMON
Configuration
GTY Quad 226
X1Y28-X1Y31
C [RLC] (RCAL)
GTY Quad 125
X0Y24-X0Y27
R [LLC]
ILKN
X0Y3 HP I/O Bank 45 HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y24-X1Y27
B [RLC]
GTY Quad 124
X0Y20-X0Y23
Q [LLC]
CMAC
X0Y3 HP I/O Bank 44 HP I/O Bank 64
PCIE4
X1Y2
(tandem)
GTY Quad 224
X1Y20-X1Y23
A [RLC]
GTY Quad 123
X0Y16-X0Y19
AF [LLC]
CMAC
X0Y2 HP I/O Bank 43 HP I/O Bank 63
F
ILKN
X1Y2
GTY Quad 223
X1Y16-X1Y19
P [RLC]
GTY Quad 122
X0Y12-X0Y15
AE [LS]
PCIE4
X0Y1 HP I/O Bank 42 HP I/O Bank 62
E
ILKN
X1Y1
GTY Quad 222
X1Y12-X1Y15
O [RS]
GTY Quad 121
X0Y8-X0Y11
AD [LS] (RCAL)
CMAC
X0Y1 HP I/O Bank 41 HP I/O Bank 61
D
SYSMON
Configuration
GTY Quad 221
X1Y8-X1Y11
N [RS] (RCAL)
GTY Quad 120
X0Y4-X0Y7
AC [LS]
ILKN
X0Y0 HP I/O Bank 40 HP I/O Bank 60 Configuration
GTY Quad 220
X1Y4-X1Y7
M [RS]
GTY Quad 119
X0Y0-X0Y3
AB [LS]
CMAC
X0Y0 HP I/O Bank 39 HP I/O Bank 59 PCIE4
X1Y0
GTY Quad 219
X1Y0-X1Y3
L [RS]
SLR Crossing
SLR Crossing
X15615-020817
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 146
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Chapter 1: Packaging Overview
XCVU11P and XQVU11P Bank Diagrams
X-Ref Target - Figure 1-104
Figure 1-104: XCVU11P and XQVU11P Banks
GTY Quad 135
X0Y44-X0Y47
CMAC
X0Y8 HP I/O Bank 75 ILKN
X1Y5
GTY Quad 235
X1Y44-X1Y47
GTY Quad 134
X0Y40-X0Y43
CMAC
X0Y7 HP I/O Bank 74 SYSMON
Configuration
GTY Quad 234
X1Y40-X1Y43
GTY Quad 133
X0Y36-X0Y39
(RCAL)
ILKN
X0Y4 HP I/O Bank 73 Configuration
GTY Quad 233
X1Y36-X1Y39
(RCAL)
GTY Quad 132
X0Y32-X0Y35
CMAC
X0Y6 HP I/O Bank 72 PCIE4
X0Y2
GTY Quad 232
X1Y32-X1Y35
GTY Quad 131
X0Y28-X0Y31
CMAC
X0Y5 HP I/O Bank 71 ILKN
X1Y3
GTY Quad 231
X1Y28-X1Y31
GTY Quad 130
X0Y24-X0Y27
CMAC
X0Y4 HP I/O Bank 70 SYSMON
Configuration
GTY Quad 230
X1Y24-X1Y27
GTY Quad 129
X0Y20-X0Y23
(RCAL)
ILKN
X0Y2 HP I/O Bank 69 Configuration
GTY Quad 229
X1Y20-X1Y23
(RCAL)
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y3 HP I/O Bank 68 PCIE4
X0Y1
GTY Quad 228
X1Y16-X1Y19
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y2 HP I/O Bank 67 ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
GTY Quad 126
X0Y8-X0Y11
CMAC
X0Y1 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
GTY Quad 125
X0Y4-X0Y7
(RCAL)
ILKN
X0Y0 HP I/O Bank 65 Configuration
GTY Quad 225
X1Y4-X1Y7
(RCAL)
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 64
PCIE4
X0Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
SLR Crossing
SLR Crossing
X15616-020817
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 147
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-105
Figure 1-105: XCVU11P Banks in FLGF1924 Package
GTY Quad 135
X0Y44-X0Y47
CMAC
X0Y8
HP I/O Bank 75
P
ILKN
X1Y5
GTY Quad 235
X1Y44-X1Y47
GTY Quad 134
X0Y40-X0Y43
CMAC
X0Y7
HP I/O Bank 74
O
SYSMON
Configuration
GTY Quad 234
X1Y40-X1Y43
GTY Quad 133
X0Y36-X0Y39
(RCAL)
ILKN
X0Y4
HP I/O Bank 73
NConfiguration
GTY Quad 233
X1Y36-X1Y39
J [RN] (RCAL)
GTY Quad 132
X0Y32-X0Y35
CMAC
X0Y6
HP I/O Bank 72
M
PCIE4
X0Y2
GTY Quad 232
X1Y32-X1Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
P [LN]
CMAC
X0Y5
HP I/O Bank 71
L
ILKN
X1Y3
GTY Quad 231
X1Y28-X1Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
CMAC
X0Y4
HP I/O Bank 70
K
SYSMON
Configuration
GTY Quad 230
X1Y24-X1Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
N [LN] (RCAL)
ILKN
X0Y2
HP I/O Bank 69
JConfiguration
GTY Quad 229
X1Y20-X1Y23
F [RN] (RCAL)
GTY Quad 128
X0Y16-X0Y19
CMAC
X0Y3
HP I/O Bank 68
F
PCIE4
X0Y1
GTY Quad 228
X1Y16-X1Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
M [LS]
CMAC
X0Y2
HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
L [LS]
CMAC
X0Y1
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
K [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 64
G
PCIE4
X0Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
SLR Crossing
X15620-020817
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 148
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-106
Figure 1-106: XCVU11P Banks in FLGB2104 Package
GTY Quad 135
X0Y44-X0Y47
CMAC
X0Y8 HP I/O Bank 75 ILKN
X1Y5
GTY Quad 235
X1Y44-X1Y47
GTY Quad 134
X0Y40-X0Y43
CMAC
X0Y7
HP I/O Bank 74
O
SYSMON
Configuration
GTY Quad 234
X1Y40-X1Y43
GTY Quad 133
X0Y36-X0Y39
S [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 73
NConfiguration
GTY Quad 233
X1Y36-X1Y39
J [RN] (RCAL)
GTY Quad 132
X0Y32-X0Y35
CMAC
X0Y6
HP I/O Bank 72
M
PCIE4
X0Y2
GTY Quad 232
X1Y32-X1Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
R [LN]
CMAC
X0Y5
HP I/O Bank 71
L
ILKN
X1Y3
GTY Quad 231
X1Y28-X1Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
CMAC
X0Y4
HP I/O Bank 70
K
SYSMON
Configuration
GTY Quad 230
X1Y24-X1Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
P [LN] (RCAL)
ILKN
X0Y2
HP I/O Bank 69
JConfiguration
GTY Quad 229
X1Y20-X1Y23
F [RN] (RCAL)
GTY Quad 128
X0Y16-X0Y19
O [LN]
CMAC
X0Y3
HP I/O Bank 68
G
PCIE4
X0Y1
GTY Quad 228
X1Y16-X1Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
N [LS]
CMAC
X0Y2
HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
CMAC
X0Y1
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
L [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
K [LS]
CMAC
X0Y0
HP I/O Bank 64
B
PCIE4
X0Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
SLR Crossing
X15617-020817
XILINXG Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-107
Figure 1-107: XCVU11P Banks in FLGC2104 Package and XQVU11P Banks in FLRC2104 Package
GTY Quad 135
X0Y44-X0Y47
W [LN]
CMAC
X0Y8 HP I/O Bank 75 ILKN
X1Y5
GTY Quad 235
X1Y44-X1Y47
J [RN]
GTY Quad 134
X0Y40-X0Y43
V [LN]
CMAC
X0Y7 HP I/O Bank 74 SYSMON
Configuration
GTY Quad 234
X1Y40-X1Y43
I [RN]
GTY Quad 133
X0Y36-X0Y39
U [LN] (RCAL)
ILKN
X0Y4 HP I/O Bank 73 Configuration
GTY Quad 233
X1Y36-X1Y39
H [RN] (RCAL)
GTY Quad 132
X0Y32-X0Y35
T [LN]
CMAC
X0Y6 HP I/O Bank 72 PCIE4
X0Y2
GTY Quad 232
X1Y32-X1Y35
G [RN]
GTY Quad 131
X0Y28-X0Y31
S [LN]
CMAC
X0Y5
HP I/O Bank 71
I
ILKN
X1Y3
GTY Quad 231
X1Y28-X1Y31
F [RN]
GTY Quad 130
X0Y24-X0Y27
R [LC]
CMAC
X0Y4
HP I/O Bank 70
H
SYSMON
Configuration
GTY Quad 230
X1Y24-X1Y27
E [RC]
GTY Quad 129
X0Y20-X0Y23
Q [LC] (RCAL)
ILKN
X0Y2
HP I/O Bank 69
GConfiguration
GTY Quad 229
X1Y20-X1Y23
D [RC] (RCAL)
GTY Quad 128
X0Y16-X0Y19
P [LC]
CMAC
X0Y3
HP I/O Bank 68
F
PCIE4
X0Y1
GTY Quad 228
X1Y16-X1Y19
C [RC]
GTY Quad 127
X0Y12-X0Y15
O [LC]
CMAC
X0Y2
HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
B [RC]
GTY Quad 126
X0Y8-X0Y11
N [LC]
CMAC
X0Y1
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
A [RC]
GTY Quad 125
X0Y4-X0Y7
Z [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
M [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
Y [LS]
CMAC
X0Y0
HP I/O Bank 64
B
PCIE4
X0Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
L [RS]
SLR Crossing
SLR Crossing
X15618-020817
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-108
Figure 1-108: XCVU11P Banks in FSGD2104 Package
GTY Quad 135
X0Y44-X0Y47
CMAC
X0Y8 HP I/O Bank 75 ILKN
X1Y5
GTY Quad 235
X1Y44-X1Y47
GTY Quad 134
X0Y40-X0Y43
CMAC
X0Y7
HP I/O Bank 74
O
SYSMON
Configuration
GTY Quad 234
X1Y40-X1Y43
GTY Quad 133
X0Y36-X0Y39
S [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 73
NConfiguration
GTY Quad 233
X1Y36-X1Y39
J [RN] (RCAL)
GTY Quad 132
X0Y32-X0Y35
CMAC
X0Y6
HP I/O Bank 72
M
PCIE4
X0Y2
GTY Quad 232
X1Y32-X1Y35
I [RN]
GTY Quad 131
X0Y28-X0Y31
R [LN]
CMAC
X0Y5
HP I/O Bank 71
L
ILKN
X1Y3
GTY Quad 231
X1Y28-X1Y31
H [RN]
GTY Quad 130
X0Y24-X0Y27
Q [LN]
CMAC
X0Y4
HP I/O Bank 70
K
SYSMON
Configuration
GTY Quad 230
X1Y24-X1Y27
G [RN]
GTY Quad 129
X0Y20-X0Y23
P [LN] (RCAL)
ILKN
X0Y2
HP I/O Bank 69
JConfiguration
GTY Quad 229
X1Y20-X1Y23
F [RN] (RCAL)
GTY Quad 128
X0Y16-X0Y19
O [LN]
CMAC
X0Y3
HP I/O Bank 68
F
PCIE4
X0Y1
GTY Quad 228
X1Y16-X1Y19
E [RS]
GTY Quad 127
X0Y12-X0Y15
N [LS]
CMAC
X0Y2
HP I/O Bank 67
E
ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
M [LS]
CMAC
X0Y1
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
L [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
K [LS]
CMAC
X0Y0
HP I/O Bank 64
B
PCIE4
X0Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
SLR Crossing
SLR Crossing
;
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-109
Figure 1-109: XCVU11P Banks in FLGA2577 Package
GTY Quad 135
X0Y44-X0Y47
AA [LN]
CMAC
X0Y8
HP I/O Bank 75
K
ILKN
X1Y5
GTY Quad 235
X1Y44-X1Y47
K [RN]
GTY Quad 134
X0Y40-X0Y43
Z [LN]
CMAC
X0Y7
HP I/O Bank 74
J
SYSMON
Configuration
GTY Quad 234
X1Y40-X1Y43
J [RN]
GTY Quad 133
X0Y36-X0Y39
Y [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 73
IConfiguration
GTY Quad 233
X1Y36-X1Y39
I [RN] (RCAL)
GTY Quad 132
X0Y32-X0Y35
X [LN]
CMAC
X0Y6
HP I/O Bank 72
H (Partial)
PCIE4
X0Y2
GTY Quad 232
X1Y32-X1Y35
H [RN]
GTY Quad 131
X0Y28-X0Y31
W [LUC]
CMAC
X0Y5
HP I/O Bank 71
G
ILKN
X1Y3
GTY Quad 231
X1Y28-X1Y31
G [RUC]
GTY Quad 130
X0Y24-X0Y27
V [LUC]
CMAC
X0Y4
HP I/O Bank 70
F
SYSMON
Configuration
GTY Quad 230
X1Y24-X1Y27
F [RUC]
GTY Quad 129
X0Y20-X0Y23
U [LUC] (RCAL)
ILKN
X0Y2
HP I/O Bank 69
EConfiguration
GTY Quad 229
X1Y20-X1Y23
E [RUC] (RCAL)
GTY Quad 128
X0Y16-X0Y19
T [LUC]
CMAC
X0Y3
HP I/O Bank 68
D
PCIE4
X0Y1
GTY Quad 228
X1Y16-X1Y19
D [RUC]
GTY Quad 127
X0Y12-X0Y15
S [LLC]
CMAC
X0Y2 HP I/O Bank 67 ILKN
X1Y1
GTY Quad 227
X1Y12-X1Y15
C [RLC]
GTY Quad 126
X0Y8-X0Y11
R [LLC]
CMAC
X0Y1
HP I/O Bank 66
B (Partial)
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
B [RLC]
GTY Quad 125
X0Y4-X0Y7
Q [LLC] (RCAL)
ILKN
X0Y0
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
A [RLC] (RCAL)
GTY Quad 124
X0Y0-X0Y3
AF [LLC]
CMAC
X0Y0 HP I/O Bank 64
PCIE4
X0Y0
(tandem)
GTY Quad 224
X1Y0-X1Y3
P [RLC]
SLR Crossing
SLR Crossing
X15619-020817
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Chapter 1: Packaging Overview
XCVU13P Bank Diagrams
X-Ref Target - Figure 1-110
Figure 1-110: XCVU13P Banks
GTY Quad 135
X0Y60-X0Y63
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTY Quad 235
X1Y60-X1Y63
GTY Quad 134
X0Y56-X0Y59
CMAC
X0Y10 HP I/O Bank 74 SYSMON
Configuration
GTY Quad 234
X1Y56-X1Y59
GTY Quad 133
X0Y52-X0Y55
(RCAL)
ILKN
X0Y6 HP I/O Bank 73 Configuration
GTY Quad 233
X1Y52-X1Y55
(RCAL)
GTY Quad 132
X0Y48-X0Y51
CMAC
X0Y9 HP I/O Bank 72 PCIE4
X0Y3
GTY Quad 232
X1Y48-X1Y51
GTY Quad 131
X0Y44-X0Y47
CMAC
X0Y8 HP I/O Bank 71 ILKN
X1Y5
GTY Quad 231
X1Y44-X1Y47
GTY Quad 130
X0Y40-X0Y43
CMAC
X0Y7 HP I/O Bank 70 SYSMON
Configuration
GTY Quad 230
X1Y40-X1Y43
GTY Quad 129
X0Y36-X0Y39
(RCAL)
ILKN
X0Y4 HP I/O Bank 69 Configuration
GTY Quad 229
X1Y36-X1Y39
(RCAL)
GTY Quad 128
X0Y32-X0Y35
CMAC
X0Y6 HP I/O Bank 68 PCIE4
X0Y2
GTY Quad 228
X1Y32-X1Y35
GTY Quad 127
X0Y28-X0Y31
CMAC
X0Y5 HP I/O Bank 67 ILKN
X1Y3
GTY Quad 227
X1Y28-X1Y31
GTY Quad 126
X0Y24-X0Y27
CMAC
X0Y4 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y24-X1Y27
GTY Quad 125
X0Y20-X0Y23
(RCAL)
ILKN
X0Y2 HP I/O Bank 65 Configuration
GTY Quad 225
X1Y20-X1Y23
(RCAL)
GTY Quad 124
X0Y16-X0Y19
CMAC
X0Y3 HP I/O Bank 64
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y16-X1Y19
GTY Quad 123
X0Y12-X0Y15
CMAC
X0Y2 HP I/O Bank 63 ILKN
X1Y1
GTY Quad 223
X1Y12-X1Y15
GTY Quad 122
X0Y8-X0Y11
CMAC
X0Y1 HP I/O Bank 62 SYSMON
Configuration
GTY Quad 222
X1Y8-X1Y11
GTY Quad 121
X0Y4-X0Y7
(RCAL)
ILKN
X0Y0 HP I/O Bank 61 Configuration
GTY Quad 221
X1Y4-X1Y7
(RCAL)
GTY Quad 120
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 60 PCIE4
X0Y0
GTY Quad 220
X1Y0-X1Y3
SLR Crossing
SLR Crossing
SLR Crossing
X15621-020817
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-111
Figure 1-111: XCVU13P Banks in FHGA2104 Package
GTY Quad 135
X0Y60-X0Y63
CMAC
X0Y11
HP I/O Bank 75
Q
ILKN
X1Y7
GTY Quad 235
X1Y60-X1Y63
GTY Quad 134
X0Y56-X0Y59
CMAC
X0Y10
HP I/O Bank 74
P
SYSMON
Configuration
GTY Quad 234
X1Y56-X1Y59
GTY Quad 133
X0Y52-X0Y55
(RCAL)
ILKN
X0Y6
HP I/O Bank 73
OConfiguration
GTY Quad 233
X1Y52-X1Y55
(RCAL)
GTY Quad 132
X0Y48-X0Y51
CMAC
X0Y9
HP I/O Bank 72
N
PCIE4
X0Y3
GTY Quad 232
X1Y48-X1Y51
GTY Quad 131
X0Y44-X0Y47
M [LN]
CMAC
X0Y8
HP I/O Bank 71
M
ILKN
X1Y5
GTY Quad 231
X1Y44-X1Y47
G [RN]
GTY Quad 130
X0Y40-X0Y43
L [LN]
CMAC
X0Y7
HP I/O Bank 70
L
SYSMON
Configuration
GTY Quad 230
X1Y40-X1Y43
F [RN]
GTY Quad 129
X0Y36-X0Y39
K [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 69
KConfiguration
GTY Quad 229
X1Y36-X1Y39
E [RN] (RCAL)
GTY Quad 128
X0Y32-X0Y35
CMAC
X0Y6
HP I/O Bank 68
J
PCIE4
X0Y2
GTY Quad 228
X1Y32-X1Y35
GTY Quad 127
X0Y28-X0Y31
J [LS]
CMAC
X0Y5
HP I/O Bank 67
E
ILKN
X1Y3
GTY Quad 227
X1Y28-X1Y31
D [RS]
GTY Quad 126
X0Y24-X0Y27
I [LS]
CMAC
X0Y4
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y24-X1Y27
C [RS]
GTY Quad 125
X0Y20-X0Y23
H [LS] (RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y20-X1Y23
B [RS] (RCAL)
GTY Quad 124
X0Y16-X0Y19
CMAC
X0Y3
HP I/O Bank 64
B
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y16-X1Y19
A [RS]
GTY Quad 123
X0Y12-X0Y15
CMAC
X0Y2
HP I/O Bank 63
I
ILKN
X1Y1
GTY Quad 223
X1Y12-X1Y15
GTY Quad 122
X0Y8-X0Y11
CMAC
X0Y1
HP I/O Bank 62
H
SYSMON
Configuration
GTY Quad 222
X1Y8-X1Y11
GTY Quad 121
X0Y4-X0Y7
(RCAL)
ILKN
X0Y0
HP I/O Bank 61
GConfiguration
GTY Quad 221
X1Y4-X1Y7
(RCAL)
GTY Quad 120
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 60
F
PCIE4
X0Y0
GTY Quad 220
X1Y0-X1Y3
SLR Crossing
SLR Crossing
SLR Crossing
X15622-020817
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-112
Figure 1-112: XCVU13P Banks in FHGB2104 Package
GTY Quad 135
X0Y60-X0Y63
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTY Quad 235
X1Y60-X1Y63
GTY Quad 134
X0Y56-X0Y59
CMAC
X0Y10
HP I/O Bank 74
O
SYSMON
Configuration
GTY Quad 234
X1Y56-X1Y59
GTY Quad 133
X0Y52-X0Y55
S [LN] (RCAL)
ILKN
X0Y6
HP I/O Bank 73
NConfiguration
GTY Quad 233
X1Y52-X1Y55
J [RN] (RCAL)
GTY Quad 132
X0Y48-X0Y51
CMAC
X0Y9
HP I/O Bank 72
MPCIE4
X0Y3
GTY Quad 232
X1Y48-X1Y51
I [RN]
GTY Quad 131
X0Y44-X0Y47
R [LN]
CMAC
X0Y8
HP I/O Bank 71
L
ILKN
X1Y5
GTY Quad 231
X1Y44-X1Y47
H [RN]
GTY Quad 130
X0Y40-X0Y43
Q [LN]
CMAC
X0Y7
HP I/O Bank 70
K
SYSMON
Configuration
GTY Quad 230
X1Y40-X1Y43
G [RN]
GTY Quad 129
X0Y36-X0Y39
P [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 69
JConfiguration
GTY Quad 229
X1Y36-X1Y39
F [RN] (RCAL)
GTY Quad 128
X0Y32-X0Y35
O [LN]
CMAC
X0Y6
HP I/O Bank 68
F (Partial)
PCIE4
X0Y2
GTY Quad 228
X1Y32-X1Y35
E [RS]
GTY Quad 127
X0Y28-X0Y31
N [LS]
CMAC
X0Y5
HP I/O Bank 67
E
ILKN
X1Y3
GTY Quad 227
X1Y28-X1Y31
D [RS]
GTY Quad 126
X0Y24-X0Y27
M [LS]
CMAC
X0Y4
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y24-X1Y27
C [RS]
GTY Quad 125
X0Y20-X0Y23
L [LS] (RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y20-X1Y23
B [RS] (RCAL)
GTY Quad 124
X0Y16-X0Y19
K [LS]
CMAC
X0Y3
HP I/O Bank 64
B
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y16-X1Y19
A [RS]
GTY Quad 123
X0Y12-X0Y15
CMAC
X0Y2
HP I/O Bank 63
IILKN
X1Y1
GTY Quad 223
X1Y12-X1Y15
GTY Quad 122
X0Y8-X0Y11
CMAC
X0Y1
HP I/O Bank 62
H
SYSMON
Configuration
GTY Quad 222
X1Y8-X1Y11
GTY Quad 121
X0Y4-X0Y7
(RCAL)
ILKN
X0Y0
HP I/O Bank 61
GConfiguration
GTY Quad 221
X1Y4-X1Y7
(RCAL)
GTY Quad 120
X0Y0-X0Y3
CMAC
X0Y0
HP I/O Bank 60
FPCIE4
X0Y0
GTY Quad 220
X1Y0-X1Y3
SLR Crossing
SLR Crossing
SLR Crossing
X15623-020817
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-113
Figure 1-113: XCVU13P Banks in FHGC2104 Package
GTY Quad 135
X0Y60-X0Y63
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTY Quad 235
X1Y60-X1Y63
GTY Quad 134
X0Y56-X0Y59
CMAC
X0Y10 HP I/O Bank 74 SYSMON
Configuration
GTY Quad 234
X1Y56-X1Y59
GTY Quad 133
X0Y52-X0Y55
W [LN] (RCAL)
ILKN
X0Y6 HP I/O Bank 73 Configuration
GTY Quad 233
X1Y52-X1Y55
J [RN] (RCAL)
GTY Quad 132
X0Y48-X0Y51
V [LN]
CMAC
X0Y9 HP I/O Bank 72 PCIE4
X0Y3
GTY Quad 232
X1Y48-X1Y51
I [RN]
GTY Quad 131
X0Y44-X0Y47
U [LN]
CMAC
X0Y8
HP I/O Bank 71
I
ILKN
X1Y5
GTY Quad 231
X1Y44-X1Y47
H [RN]
GTY Quad 130
X0Y40-X0Y43
T [LN]
CMAC
X0Y7
HP I/O Bank 70
H
SYSMON
Configuration
GTY Quad 230
X1Y40-X1Y43
G [RN]
GTY Quad 129
X0Y36-X0Y39
S [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 69
GConfiguration
GTY Quad 229
X1Y36-X1Y39
F [RN] (RCAL)
GTY Quad 128
X0Y32-X0Y35
R [LC]
CMAC
X0Y6
HP I/O Bank 68
F
PCIE4
X0Y2
GTY Quad 228
X1Y32-X1Y35
E [RC]
GTY Quad 127
X0Y28-X0Y31
Q [LC]
CMAC
X0Y5
HP I/O Bank 67
E
ILKN
X1Y3
GTY Quad 227
X1Y28-X1Y31
D [RC]
GTY Quad 126
X0Y24-X0Y27
P [LC]
CMAC
X0Y4
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y24-X1Y27
C [RC]
GTY Quad 125
X0Y20-X0Y23
O [LC] (RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y20-X1Y23
B [RC] (RCAL)
GTY Quad 124
X0Y16-X0Y19
N [LC]
CMAC
X0Y3
HP I/O Bank 64
B
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y16-X1Y19
A [RC]
GTY Quad 123
X0Y12-X0Y15
Z [LS]
CMAC
X0Y2 HP I/O Bank 63 ILKN
X1Y1
GTY Quad 223
X1Y12-X1Y15
M [RS]
GTY Quad 122
X0Y8-X0Y11
Y [LS]
CMAC
X0Y1 HP I/O Bank 62 SYSMON
Configuration
GTY Quad 222
X1Y8-X1Y11
L [RS]
GTY Quad 121
X0Y4-X0Y7
X [LS] (RCAL)
ILKN
X0Y0 HP I/O Bank 61 Configuration
GTY Quad 221
X1Y4-X1Y7
K [RS] (RCAL)
GTY Quad 120
X0Y0-X0Y3
CMAC
X0Y0 HP I/O Bank 60 PCIE4
X0Y0
GTY Quad 220
X1Y0-X1Y3
SLR Crossing
SLR Crossing
SLR Crossing
X15624-020817
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-114
Figure 1-114: XCVU13P Banks in FIGD2104 Package
GTY Quad 135
X0Y60-X0Y63
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTY Quad 235
X1Y60-X1Y63
GTY Quad 134
X0Y56-X0Y59
CMAC
X0Y10
HP I/O Bank 74 SYSMON
Configuration
GTY Quad 234
X1Y56-X1Y59
GTY Quad 133
X0Y52-X0Y55
S [LN] (RCAL)
ILKN
X0Y6
HP I/O Bank 73 Configuration
GTY Quad 233
X1Y52-X1Y55
J [RN] (RCAL)
GTY Quad 132
X0Y48-X0Y51
CMAC
X0Y9
HP I/O Bank 72 PCIE4
X0Y3
GTY Quad 232
X1Y48-X1Y51
I [RN]
GTY Quad 131
X0Y44-X0Y47
R [LN]
CMAC
X0Y8
HP I/O Bank 71
L
ILKN
X1Y5
GTY Quad 231
X1Y44-X1Y47
H [RN]
GTY Quad 130
X0Y40-X0Y43
Q [LN]
CMAC
X0Y7
HP I/O Bank 70
K
SYSMON
Configuration
GTY Quad 230
X1Y40-X1Y43
G [RN]
GTY Quad 129
X0Y36-X0Y39
P [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 69
JConfiguration
GTY Quad 229
X1Y36-X1Y39
F [RN] (RCAL)
GTY Quad 128
X0Y32-X0Y35
O [LC]
CMAC
X0Y6 HP I/O Bank 68 PCIE4
X0Y2
GTY Quad 228
X1Y32-X1Y35
E [RC]
GTY Quad 127
X0Y28-X0Y31
CMAC
X0Y5
HP I/O Bank 67
E
ILKN
X1Y3
GTY Quad 227
X1Y28-X1Y31
D [RC]
GTY Quad 126
X0Y24-X0Y27
CMAC
X0Y4
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y24-X1Y27
C [RC]
GTY Quad 125
X0Y20-X0Y23
(RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y20-X1Y23
B [RC] (RCAL)
GTY Quad 124
X0Y16-X0Y19
CMAC
X0Y3
HP I/O Bank 64
B
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y16-X1Y19
A [RC]
GTY Quad 123
X0Y12-X0Y15
N [LS]
CMAC
X0Y2
HP I/O Bank 63 ILKN
X1Y1
GTY Quad 223
X1Y12-X1Y15
GTY Quad 122
X0Y8-X0Y11
M [LS]
CMAC
X0Y1
HP I/O Bank 62 SYSMON
Configuration
GTY Quad 222
X1Y8-X1Y11
GTY Quad 121
X0Y4-X0Y7
L [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 61 Configuration
GTY Quad 221
X1Y4-X1Y7
(RCAL)
GTY Quad 120
X0Y0-X0Y3 CMAC
X0Y0 HP I/O Bank 60 PCIE4
X0Y0
GTY Quad 220
X1Y0-X1Y3
SLR Crossing
SLR Crossing
SLR Crossing
O
N
M
H
G
F
K [LS]
;
XILINXG II II Send Feed back
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-115
Figure 1-115: XCVU13P Banks in FLGA2577 and FSGA2577 Packages
GTY Quad 135
X0Y60-X0Y63
AA [LN]
CMAC
X0Y11
HP I/O Bank 75
KILKN
X1Y7
GTY Quad 235
X1Y60-X1Y63
K [RN]
GTY Quad 134
X0Y56-X0Y59
Z [LN]
CMAC
X0Y10
HP I/O Bank 74
J
SYSMON
Configuration
GTY Quad 234
X1Y56-X1Y59
J [RN]
GTY Quad 133
X0Y52-X0Y55
Y [LN] (RCAL)
ILKN
X0Y6
HP I/O Bank 73
IConfiguration
GTY Quad 233
X1Y52-X1Y55
I [RN] (RCAL)
GTY Quad 132
X0Y48-X0Y51
X [LN]
CMAC
X0Y9 HP I/O Bank 72 PCIE4
X0Y3
GTY Quad 232
X1Y48-X1Y51
H [RN]
GTY Quad 131
X0Y44-X0Y47
W [LUC]
CMAC
X0Y8
HP I/O Bank 71
H (Partial)
ILKN
X1Y5
GTY Quad 231
X1Y44-X1Y47
G [RUC]
GTY Quad 130
X0Y40-X0Y43
V [LUC]
CMAC
X0Y7
HP I/O Bank 70
G
SYSMON
Configuration
GTY Quad 230
X1Y40-X1Y43
F [RUC]
GTY Quad 129
X0Y36-X0Y39
U [LUC] (RCAL)
ILKN
X0Y4 HP I/O Bank 69 Configuration
GTY Quad 229
X1Y36-X1Y39
E [RUC] (RCAL)
GTY Quad 128
X0Y32-X0Y35
T [LUC]
CMAC
X0Y6 HP I/O Bank 68 PCIE4
X0Y2
GTY Quad 228
X1Y32-X1Y35
D [RUC]
GTY Quad 127
X0Y28-X0Y31
S [LLC]
CMAC
X0Y5 HP I/O Bank 67 ILKN
X1Y3
GTY Quad 227
X1Y28-X1Y31
C [RLC]
GTY Quad 126
X0Y24-X0Y27
R [LLC]
CMAC
X0Y4
HP I/O Bank 66
B (Partial)
SYSMON
Configuration
GTY Quad 226
X1Y24-X1Y27
B [RLC]
GTY Quad 125
X0Y20-X0Y23
Q [LLC] (RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y20-X1Y23
A [RLC] (RCAL)
GTY Quad 124
X0Y16-X0Y19
AF [LLC]
CMAC
X0Y3 HP I/O Bank 64
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y16-X1Y19
P [RLC]
GTY Quad 123
X0Y12-X0Y15
AE [LS]
CMAC
X0Y2
HP I/O Bank 63
FILKN
X1Y1
GTY Quad 223
X1Y12-X1Y15
O [RS]
GTY Quad 122
X0Y8-X0Y11
AD [LS]
CMAC
X0Y1
HP I/O Bank 62
E
SYSMON
Configuration
GTY Quad 222
X1Y8-X1Y11
N [RS]
GTY Quad 121
X0Y4-X0Y7
AC [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 61
DConfiguration
GTY Quad 221
X1Y4-X1Y7
M [RS] (RCAL)
GTY Quad 120
X0Y0-X0Y3
AB [LS]
CMAC
X0Y0 HP I/O Bank 60 PCIE4
X0Y0
GTY Quad 220
X1Y0-X1Y3
L [RS]
SLR Crossing
SLR Crossing
SLR Crossing
X15625-020817
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 158
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Chapter 1: Packaging Overview
XCVU27P Bank Diagrams
X-Ref Target - Figure 1-116
Figure 1-116: XCVU27P Banks
GTM Dual 135
X0Y11
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTM Dual 235
X1Y11
GTM Dual 134
X0Y10
CMAC
X0Y10 HP I/O Bank 74 SYSMON
Configuration
GTM Dual 234
X1Y10
GTM Dual 133
X0Y9
(RCAL)
ILKN
X0Y6 HP I/O Bank 73 Configuration
GTM Dual 233
X1Y9
(RCAL)
GTM Dual 132
X0Y8
CMAC
X0Y9 HP I/O Bank 72 CMAC
X0Y9
GTM Dual 232
X1Y8
GTM Dual 131
X0Y7
CMAC
X0Y8 HP I/O Bank 71 ILKN
X1Y5
GTM Dual 231
X1Y7
GTM Dual 130
X0Y6
CMAC
X0Y7 HP I/O Bank 70 SYSMON
Configuration
GTM Dual 230
X1Y6
GTM Dual 129
X0Y5
(RCAL)
ILKN
X0Y4 HP I/O Bank 69 Configuration
GTM Dual 229
X1Y5
(RCAL)
GTM Dual 128
X0Y4
CMAC
X0Y6 HP I/O Bank 68 CMAC
X1Y6
GTM Dual 228
X1Y4
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y5 HP I/O Bank 67 ILKN
X1Y3
GTY Quad 227
X1Y12-X1Y15
GTY Quad 126
X0Y8-X0Y11
CMAC
X0Y4 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
GTY Quad 125
X0Y4-X0Y7
(RCAL)
ILKN
X0Y2 HP I/O Bank 65 Configuration
GTY Quad 225
X1Y4-X1Y7
(RCAL)
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y3 HP I/O Bank 64
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y0-X1Y3
GTM Dual 123
X0Y3
CMAC
X0Y2 HP I/O Bank 63 ILKN
X1Y1
GTM Dual 223
X1Y3
GTM Dual 122
X0Y2
CMAC
X0Y1 HP I/O Bank 62 SYSMON
Configuration
GTM Dual 222
X1Y2
GTM Dual 121
X0Y1
(RCAL)
ILKN
X0Y0 HP I/O Bank 61 Configuration
GTM Dual 221
X1Y1
(RCAL)
GTM Dual 120
X0Y0
CMAC
X0Y0 HP I/O Bank 60 CMAC
X1Y0
GTM Dual 220
X1Y0
SLR Crossing
SLR Crossing
SLR Crossing
X20507-031518
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UltraScale Device Packaging and Pinouts 159
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-117
Figure 1-117: XCVU27P Banks in FIGD2104 Package
GTM Dual 135
X0Y11
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTM Dual 235
X1Y11
GTM Dual 134
X0Y10
CMAC
X0Y10
HP I/O Bank 74
O
SYSMON
Configuration
GTM Dual 234
X1Y10
GTM Dual 133
X0Y9
S [LN] (RCAL)
ILKN
X0Y6
HP I/O Bank 73
NConfiguration
GTM Dual 233
X1Y9
J [RN] (RCAL)
GTM Dual 132
X0Y8
CMAC
X0Y9
HP I/O Bank 72
M
CMAC
X0Y9
GTM Dual 232
X1Y8
I [RN]
GTM Dual 131
X0Y7
R [LN]
CMAC
X0Y8
HP I/O Bank 71
L
ILKN
X1Y5
GTM Dual 231
X1Y7
H [RN]
GTM Dual 130
X0Y6
Q [LN]
CMAC
X0Y7
HP I/O Bank 70
K
SYSMON
Configuration
GTM Dual 230
X1Y6
G [RN]
GTM Dual 129
X0Y5
P [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 69
JConfiguration
GTM Dual 229
X1Y5
F [RN] (RCAL)
GTM Dual 128
X0Y4
O [LC]
CMAC
X0Y6 HP I/O Bank 68 CMAC
X1Y6
GTM Dual 228
X1Y4
E [RS]
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y5
HP I/O Bank 67
E
ILKN
X1Y3
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
CMAC
X0Y4
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
(RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y3
HP I/O Bank 64
B
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
GTM Dual 123
X0Y3
N [LS]
CMAC
X0Y2
HP I/O Bank 63
H
ILKN
X1Y1
GTM Dual 223
X1Y3
GTM Dual 122
X0Y2
M [LS]
CMAC
X0Y1
HP I/O Bank 62
G
SYSMON
Configuration
GTM Dual 222
X1Y2
GTM Dual 121
X0Y1
L [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 61
FConfiguration
GTM Dual 221
X1Y1
(RCAL)
GTM Dual 120
X0Y0
K [LS]
CMAC
X0Y0 HP I/O Bank 60 CMAC
X1Y0
GTM Dual 220
X1Y0
SLR Crossing
SLR Crossing
SLR Crossing
X20508-031518
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-118
Figure 1-118: XCVU27P Banks in FSGA2577 Package
GTM Dual 135
X0Y11
AA [LN]
CMAC
X0Y11
HP I/O Bank 75
K
ILKN
X1Y7
GTM Dual 235
X1Y11
K [RN]
GTM Dual 134
X0Y10
Z [LN]
CMAC
X0Y10
HP I/O Bank 74
J
SYSMON
Configuration
GTM Dual 234
X1Y10
J [RN]
GTM Dual 133
X0Y9
Y [LN] (RCAL)
ILKN
X0Y6
HP I/O Bank 73
IConfiguration
GTM Dual 233
X1Y9
I [RN] (RCAL)
GTM Dual 132
X0Y8
X [LN]
CMAC
X0Y9 HP I/O Bank 72 CMAC
X0Y9
GTM Dual 232
X1Y8
H [RN]
GTM Dual 131
X0Y7
W [LUC]
CMAC
X0Y8
HP I/O Bank 71
H (Partial)
ILKN
X1Y5
GTM Dual 231
X1Y7
G [RUC]
GTM Dual 130
X0Y6
V [LUC]
CMAC
X0Y7
HP I/O Bank 70
G
SYSMON
Configuration
GTM Dual 230
X1Y6
F [RUC]
GTM Dual 129
X0Y5
U [LUC] (RCAL)
ILKN
X0Y4 HP I/O Bank 69 Configuration
GTM Dual 229
X1Y5
E [RUC] (RCAL)
GTM Dual 128
X0Y4
T [LUC]
CMAC
X0Y6 HP I/O Bank 68 CMAC
X1Y6
GTM Dual 228
X1Y4
D [RUC]
GTY Quad 127
X0Y12-X0Y15
S [LLC]
CMAC
X0Y5 HP I/O Bank 67 ILKN
X1Y3
GTY Quad 227
X1Y12-X1Y15
C [RLC]
GTY Quad 126
X0Y8-X0Y11
R [LLC]
CMAC
X0Y4
HP I/O Bank 66
B (Partial)
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
B [RLC]
GTY Quad 125
X0Y4-X0Y7
Q [LLC] (RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
A [RLC] (RCAL)
GTY Quad 124
X0Y0-X0Y3
AF [LLC]
CMAC
X0Y3 HP I/O Bank 64
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y0-X1Y3
P [RLC]
GTM Dual 123
X0Y3
AE [LS]
CMAC
X0Y2
HP I/O Bank 63
F
ILKN
X1Y1
GTM Dual 223
X1Y3
O [RS]
GTM Dual 122
X0Y2
AD [LS]
CMAC
X0Y1
HP I/O Bank 62
E
SYSMON
Configuration
GTM Dual 222
X1Y2
N [RS]
GTM Dual 121
X0Y1
AC [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 61
DConfiguration
GTM Dual 221
X1Y1
M [RS] (RCAL)
GTM Dual 120
X0Y0
AB [LS]
CMAC
X0Y0 HP I/O Bank 60 CMAC
X1Y0
GTM Dual 220
X1Y0
L [RS]
SLR Crossing
SLR Crossing
SLR Crossing
X20509-031518
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UltraScale Device Packaging and Pinouts 161
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Chapter 1: Packaging Overview
XCVU29P Bank Diagrams
X-Ref Target - Figure 1-119
Figure 1-119: XCVU29P Banks
GTM Dual 135
X0Y11
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTM Dual 235
X1Y11
GTM Dual 134
X0Y10
CMAC
X0Y10 HP I/O Bank 74 SYSMON
Configuration
GTM Dual 234
X1Y10
GTM Dual 133
X0Y9
(RCAL)
ILKN
X0Y6 HP I/O Bank 73 Configuration
GTM Dual 233
X1Y9
(RCAL)
GTM Dual 132
X0Y8
CMAC
X0Y9 HP I/O Bank 72 CMAC
X0Y9
GTM Dual 232
X1Y8
GTM Dual 131
X0Y7
CMAC
X0Y8 HP I/O Bank 71 ILKN
X1Y5
GTM Dual 231
X1Y7
GTM Dual 130
X0Y6
CMAC
X0Y7 HP I/O Bank 70 SYSMON
Configuration
GTM Dual 230
X1Y6
GTM Dual 129
X0Y5
(RCAL)
ILKN
X0Y4 HP I/O Bank 69 Configuration
GTM Dual 229
X1Y5
(RCAL)
GTM Dual 128
X0Y4
CMAC
X0Y6 HP I/O Bank 68 CMAC
X1Y6
GTM Dual 228
X1Y4
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y5 HP I/O Bank 67 ILKN
X1Y3
GTY Quad 227
X1Y12-X1Y15
GTY Quad 126
X0Y8-X0Y11
CMAC
X0Y4 HP I/O Bank 66 SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
GTY Quad 125
X0Y4-X0Y7
(RCAL)
ILKN
X0Y2 HP I/O Bank 65 Configuration
GTY Quad 225
X1Y4-X1Y7
(RCAL)
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y3 HP I/O Bank 64
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y0-X1Y3
GTM Dual 123
X0Y3
CMAC
X0Y2 HP I/O Bank 63 ILKN
X1Y1
GTM Dual 223
X1Y3
GTM Dual 122
X0Y2
CMAC
X0Y1 HP I/O Bank 62 SYSMON
Configuration
GTM Dual 222
X1Y2
GTM Dual 121
X0Y1
(RCAL)
ILKN
X0Y0 HP I/O Bank 61 Configuration
GTM Dual 221
X1Y1
(RCAL)
GTM Dual 120
X0Y0
CMAC
X0Y0 HP I/O Bank 60 CMAC
X1Y0
GTM Dual 220
X1Y0
SLR Crossing
SLR Crossing
SLR Crossing
X20507-031518
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-120
Figure 1-120: XCVU29P Banks in FIGD2104 Package
GTM Dual 135
X0Y11
CMAC
X0Y11 HP I/O Bank 75 ILKN
X1Y7
GTM Dual 235
X1Y11
GTM Dual 134
X0Y10
CMAC
X0Y10
HP I/O Bank 74
O
SYSMON
Configuration
GTM Dual 234
X1Y10
GTM Dual 133
X0Y9
S [LN] (RCAL)
ILKN
X0Y6
HP I/O Bank 73
NConfiguration
GTM Dual 233
X1Y9
J [RN] (RCAL)
GTM Dual 132
X0Y8
CMAC
X0Y9
HP I/O Bank 72
M
CMAC
X0Y9
GTM Dual 232
X1Y8
I [RN]
GTM Dual 131
X0Y7
R [LN]
CMAC
X0Y8
HP I/O Bank 71
L
ILKN
X1Y5
GTM Dual 231
X1Y7
H [RN]
GTM Dual 130
X0Y6
Q [LN]
CMAC
X0Y7
HP I/O Bank 70
K
SYSMON
Configuration
GTM Dual 230
X1Y6
G [RN]
GTM Dual 129
X0Y5
P [LN] (RCAL)
ILKN
X0Y4
HP I/O Bank 69
JConfiguration
GTM Dual 229
X1Y5
F [RN] (RCAL)
GTM Dual 128
X0Y4
O [LC]
CMAC
X0Y6 HP I/O Bank 68 CMAC
X1Y6
GTM Dual 228
X1Y4
E [RS]
GTY Quad 127
X0Y12-X0Y15
CMAC
X0Y5
HP I/O Bank 67
E
ILKN
X1Y3
GTY Quad 227
X1Y12-X1Y15
D [RS]
GTY Quad 126
X0Y8-X0Y11
CMAC
X0Y4
HP I/O Bank 66
D
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
C [RS]
GTY Quad 125
X0Y4-X0Y7
(RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
B [RS] (RCAL)
GTY Quad 124
X0Y0-X0Y3
CMAC
X0Y3
HP I/O Bank 64
B
PCIE4
X0Y1
(tandem)
GTY Quad 224
X1Y0-X1Y3
A [RS]
GTM Dual 123
X0Y3
N [LS]
CMAC
X0Y2
HP I/O Bank 63
H
ILKN
X1Y1
GTM Dual 223
X1Y3
GTM Dual 122
X0Y2
M [LS]
CMAC
X0Y1
HP I/O Bank 62
G
SYSMON
Configuration
GTM Dual 222
X1Y2
GTM Dual 121
X0Y1
L [LS] (RCAL)
ILKN
X0Y0
HP I/O Bank 61
FConfiguration
GTM Dual 221
X1Y1
(RCAL)
GTM Dual 120
X0Y0
K [LS]
CMAC
X0Y0 HP I/O Bank 60 CMAC
X1Y0
GTM Dual 220
X1Y0
SLR Crossing
SLR Crossing
SLR Crossing
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-121
Figure 1-121: XCVU29P Banks in FSGA2577 Package
GTM Dual 135
X0Y11
AA [LN]
CMAC
X0Y11
HP I/O Bank 75
K
ILKN
X1Y7
GTM Dual 235
X1Y11
K [RN]
GTM Dual 134
X0Y10
Z [LN]
CMAC
X0Y10
HP I/O Bank 74
J
SYSMON
Configuration
GTM Dual 234
X1Y10
J [RN]
GTM Dual 133
X0Y9
Y [LN] (RCAL)
ILKN
X0Y6
HP I/O Bank 73
IConfiguration
GTM Dual 233
X1Y9
I [RN] (RCAL)
GTM Dual 132
X0Y8
X [LN]
CMAC
X0Y9 HP I/O Bank 72 CMAC
X0Y9
GTM Dual 232
X1Y8
H [RN]
GTM Dual 131
X0Y7
W [LUC]
CMAC
X0Y8
HP I/O Bank 71
H (Partial)
ILKN
X1Y5
GTM Dual 231
X1Y7
G [RUC]
GTM Dual 130
X0Y6
V [LUC]
CMAC
X0Y7
HP I/O Bank 70
G
SYSMON
Configuration
GTM Dual 230
X1Y6
F [RUC]
GTM Dual 129
X0Y5
U [LUC] (RCAL)
ILKN
X0Y4 HP I/O Bank 69 Configuration
GTM Dual 229
X1Y5
E [RUC] (RCAL)
GTM Dual 128
X0Y4
T [LUC]
CMAC
X0Y6 HP I/O Bank 68 CMAC
X1Y6
GTM Dual 228
X1Y4
D [RUC]
GTY Quad 127
X0Y12-X0Y15
S [LLC]
CMAC
X0Y5 HP I/O Bank 67 ILKN
X1Y3
GTY Quad 227
X1Y12-X1Y15
C [RLC]
GTY Quad 126
X0Y8-X0Y11
R [LLC]
CMAC
X0Y4
HP I/O Bank 66
B (Partial)
SYSMON
Configuration
GTY Quad 226
X1Y8-X1Y11
B [RLC]
GTY Quad 125
X0Y4-X0Y7
Q [LLC] (RCAL)
ILKN
X0Y2
HP I/O Bank 65
CConfiguration
GTY Quad 225
X1Y4-X1Y7
A [RLC] (RCAL)
GTY Quad 124
X0Y0-X0Y3
AF [LLC]
CMAC
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PCIE4
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(tandem)
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GTM Dual 123
X0Y3
AE [LS]
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X0Y2
HP I/O Bank 63
F
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X1Y3
O [RS]
GTM Dual 122
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AD [LS]
CMAC
X0Y1
HP I/O Bank 62
E
SYSMON
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GTM Dual 222
X1Y2
N [RS]
GTM Dual 121
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AC [LS] (RCAL)
ILKN
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DConfiguration
GTM Dual 221
X1Y1
M [RS] (RCAL)
GTM Dual 120
X0Y0
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CMAC
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X1Y0
GTM Dual 220
X1Y0
L [RS]
SLR Crossing
SLR Crossing
SLR Crossing
X20509-031518
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 164
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 1: Packaging Overview
XCVU31P Bank Diagrams
X-Ref Target - Figure 1-122
Figure 1-122: XCVU31P Banks
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X-Ref Target - Figure 1-123
Figure 1-123: XCVU31P Banks in FSVH1924 Package
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X19797-010619
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 165
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 1: Packaging Overview
XCVU33P Bank Diagrams
X-Ref Target - Figure 1-124
Figure 1-124: XCVU33P Banks
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X-Ref Target - Figure 1-125
Figure 1-125: XCVU33P Banks in FSVH2104 Package
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X19799-010619
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UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 1: Packaging Overview
XCVU35P Bank Diagrams
X-Ref Target - Figure 1-126
Figure 1-126: XCVU35P Banks
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X19800-010619
(I XILINXa Send Feed back
UltraScale Device Packaging and Pinouts 167
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-127
Figure 1-127: XCVU35P Banks in FSVH2104 Package
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-128
Figure 1-128: XCVU35P Banks in FSVH2892 Package
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XILINXG Send Feed back
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Chapter 1: Packaging Overview
XCVU37P Bank Diagrams
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Figure 1-129: XCVU37P Banks
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X19803-010619
XILINXG Send Feed back
UltraScale Device Packaging and Pinouts 170
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Chapter 1: Packaging Overview
X-Ref Target - Figure 1-130
Figure 1-130: XCVU37P Banks in FSVH2892 Package
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X19804-010619
(I X|L|NX.
UltraScale Device Packaging and Pinouts 171
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 2
Package Files
About ASCII Package Files
The ASCII package files for each package include a comma-separated-values (CSV) version
and a text version optimized for a browser or text editor in fixed-width fonts. The
information in each of the files includes:
• Device/Package name (family-device-package), with date and time of creation
• Seven columns containing data for each pin:
°Pin—Pin location on the package.
°Pin Name—The name of the assigned pin.
°Memory Byte Group—Memory byte group between 0 and 3 split into upper (U) and
lower (L) halves. For more information on the memory byte group, see the
UltraScale Architecture FPGAs Memory IP Product Guide (PG150) [Ref 13].
°Bank—Bank number.
°I/O Type—CONFIG, HD, HR, HP, or GT (GTH, GTY, or GTM) depending on the I/O
type. For more information on the I/O type, see the UltraScale Architecture SelectIO
Resources User Guide (UG571) [Ref 5].
°Super Logic Region—Number corresponding to the super logic region (SLR) in the
devices implemented with stacked silicon interconnect (SSI) technology.
°No-Connect—This list of devices is used for migration between devices that have
the same package size and are not connected at that specific pin.
• Total number of pins in the package.
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Chapter 2: Package Files
Package Specifications Designations
Package specifications are designated as evaluation only, engineering sample, or
production. Each designation is defined as follows.
Evaluation Only
These package specifications are based on initial device specifications, package routability
analysis and mechanical package construction. Package specifications with this designation
are not stable and package pinouts are likely to change and these specifications should
only be used for initial system level design feasibility.
Engineering Sample
These package specifications are based on a released package design and validated with ES
engineering sample (ES) devices. Package specifications with this designation are
considered stable, however some pinout and mechanical specifications might change prior
to the production release of the particular device. Package pinouts with this designation are
to be used for PCB and Vivado designs using ES devices.
Production
These package specifications are released coincident with production release of a particular
device. Customers receive formal notification of any subsequent changes.
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Chapter 2: Package Files
ASCII Pinout Files
Links to the ASCII pinout information by device/package are listed in Table 2-1. The pinouts
of XQ devices are identical to the pinouts of their equivalent XC devices in footprint
compatible package. Links in this table to XQ devices open the XC version of the pinout file.
For example, the link to RBA676-XQKU040 opens the FBVA676-XCKU040 pinout file.
Download all available Kintex UltraScale, Kintex UltraScale+, Virtex UltraScale, and Virtex
UltraScale+ FPGA package/device/pinout files at:
www.xilinx.com/support/package-pinout-files/ultrascale-pkgs.html
Note: All package files are ASCII files in TXT and CSV file format. Only the available files listed in
Table 2-1 are linked and consolidated in this ZIP file.
www.xilinx.com/support/packagefiles/usapackages/usaall.zip
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC, and the third digit in the package name is Q (for example: FFQA1156).
Table 2-1: Package/Device Pinout Files
Package Device
FBVA676 XCKU035
Production
XCKU040
Production
FFVA676 XCKU3P
Production
XCKU5P
Production
FFVB676 XCKU3P
Production
XCKU5P
Production
FFRB676 XQKU5P
Production
RBA676 XQKU040
Production
SFVA784 XCKU035
Production
XCKU040
Production
SFVB784 XCKU3P
Production
XCKU5P
Production
SFRB784 XQKU5P
Production
FBVA900 XCKU035
Production
XCKU040
Production
FFVD900 XCKU3P
Production
XCKU5P
Production
XCKU11P
Production
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Chapter 2: Package Files
FFVE900 XCKU9P
Production
XCKU13P
Production
FFVA1156 XCKU025
Production
XCKU035
Production
XCKU040
Production
XCKU060
Production
XCKU095
Production
XCKU11P
Production
XCKU15P
Production
FFRA1156 XQKU15P
Production
RFA1156 XQKU040
Production
XQKU060
Production
XQKU095
Production
FFVA1517 XCKU060
Production
FLVA1517 XCKU085
Production
XCKU115
Production
FFVC1517 XCKU095
Production
XCVU065
Production
XCVU080
Production
XCVU095
Production
XCVU3P
Production
FFRC1517 XQVU3P
Production
FFVD1517 XCVU080
Production
XCVU095
Production
FLVD1517 XCKU115
Production
XCVU125
Production
FFVE1517 XCKU11P
Production
XCKU15P
Production
FFRE1517 XQKU15P
Production
RLD1517 XQKU115
Production
FFVA1760 XCKU15P
Production
FFVB1760 XCKU095
Production
XCVU080
Production
XCVU095
Production
FLVB1760 XCKU085
Production
XCKU115
Production
XCVU125
Production
FFVE1760 XCKU15P
Production
FLVD1924 XCKU115
Production
Table 2-1: Package/Device Pinout Files (Cont’d)
Package Device
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Chapter 2: Package Files
FLVF1924 XCKU085
Production
XCKU115
Production
FLGF1924 XCVU11P
Production
RLF1924 XQKU115
Production
FSVH1924 XCVU31P
Production
FFVA2104 XCVU080
Production
XCVU095
Production
FLVA2104 XCKU115
Production
XCVU125
Production
XCVU5P
Production
XCVU7P
Production
FLRA2104 XQVU7P
Production
FLGA2104 XCVU9P
Production
FHGA2104 XCVU13P
Production
FFVB2104 XCKU095
Production
XCVU080
Production
XCVU095
Production
FLVB2104 XCKU115
Production
XCVU125
Production
XCVU5P
Production
XCVU7P
Production
FLRB2104 XQVU7P
Production
FLGB2104 XCVU160
Production
XCVU190
Production
XCVU9P
Production
XCVU11P
Production
FHGB2104 XCVU13P
Production
FFVC2104 XCVU095
Production
FLVC2104 XCVU125
Production
XCVU5P
Production
XCVU7P
Production
FLGC2104 XCVU160
Production
XCVU190
Production
XCVU9P
Production
XCVU11P
Production
FLRC2104 XQVU11P
Production
Table 2-1: Package/Device Pinout Files (Cont’d)
Package Device
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Chapter 2: Package Files
FHGC2104 XCVU13P
Production
FIGD2104 XCVU13P
Production
XCVU27P
Engineering
Sample
XCVU29P
Engineering
Sample
FSGD2104 XCVU9P
Production
XCVU11P
Production
FSVH2104 XCVU33P
Production
XCVU35P
Production
FLGB2377 XCVU440
Production
FLGA2577 XCVU190
Production
XCVU9P
Production
XCVU11P
Production
XCVU13P
Production
FSGA2577 XCVU13P
Production
XCVU27P
Engineering
Sample
XCVU27P
Engineering
Sample
FLGA2892 XCVU440
Production
FSVH2892 XCVU35P
Production
XCVU37P
Production
Table 2-1: Package/Device Pinout Files (Cont’d)
Package Device
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Chapter 3
Device Diagrams
Summary
The diagrams in this chapter show a top-view perspective of the package pinout of each
UltraScale and UltraScale+ device/package combination. Table 3-1 through Table 3-4
contain cross references to the device diagrams. The I/O-bank diagram shows the location
of each user I/O and GTH/GTY transceiver and the respective bank or GT quad. The
configuration-power diagram shows the location of every power pin and dedicated as well
as multi-function configuration pin in the package. See Package Specifications
Designations in Chapter 2 for definitions of Evaluation Only, Engineering Sample, and
Production device diagrams.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC, and the third digit in the package name is Q (for example: FFQA1156).
Table 3-1: Cross-Reference to Kintex UltraScale and XQ Kintex UltraScale Device Diagrams by
Package
Package Footprint Compatible Devices Package Status
FBVA676 XCKU035
page 183
XCKU040
page 183 Production
RBA676 XQKU040
page 183 Production
SFVA784 XCKU035
page 185
XCKU040
page 185 Production
FBVA900 XCKU035
page 187
XCKU040
page 187 Production
FFVA1156 XCKU025
page 189
XCKU035
page 191
XCKU040
page 193
XCKU060
page 195
XCKU095
page 197 Production
RFA1156 XQKU040
page 193
XQKU060
page 195
XQKU095
page 197 Production
FFVA1517 XCKU060
page 199 Production
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Chapter 3: Device Diagrams
FLVA1517 XCKU085
page 201
XCKU115
page 201 Production
FFVC1517 XCKU095
page 203 Production
FLVD1517 XCKU115
page 205 Production
RLD1517 XQKU115
page 205 Production
FFVB1760 XCKU095
page 207 Production
FLVB1760 XCKU085
page 209
XCKU115
page 211 Production
FLVD1924 XCKU115
page 213 Production
FLVF1924 XCKU085
page 215
XCKU115
page 217 Production
RLF1924 XQKU115
page 217 Production
FLVA2104 XCKU115
page 219 Production
FFVB2104 XCKU095
page 221 Production
FLVB2104 XCKU115
page 223 Production
Table 3-1: Cross-Reference to Kintex UltraScale and XQ Kintex UltraScale Device Diagrams by
Package (Cont’d)
Package Footprint Compatible Devices Package Status
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Chapter 3: Device Diagrams
Table 3-2: Cross-Reference to Virtex UltraScale Device Diagrams by Package
Package Footprint Compatible Devices Package Status
FFVC1517 XCVU065
page 225
XCVU080
page 227
XCVU095
page 227 Production
FFVD1517 XCVU080
page 229
XCVU095
page 229 Production
FLVD1517 XCVU125
page 231 Production
FFVB1760 XCVU080
page 233
XCVU095
page 233 Production
FLVB1760 XCVU125
page 235 Production
FFVA2104 XCVU080
page 237
XCVU095
page 237 Production
FLVA2104 XCVU125
page 239 Production
FFVB2104 XCVU080
page 241
XCVU095
page 241 Production
FLVB2104 XCVU125
page 243 Production
FLGB2104 XCVU160
page 245
XCVU190
page 245 Production
FFVC2104 XCVU095
page 247 Production
FLVC2104 XCVU125
page 249 Production
FLGC2104 XCVU160
page 251
XCVU190
page 251 Production
FLGB2377 XCVU440
page 253 Production
FLGA2577 XCVU190
page 255 Production
FLGA2892 XCVU440
page 257 Production
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Chapter 3: Device Diagrams
Table 3-3: Cross-Reference to Kintex UltraScale+ and XQ Kintex UltraScale+ Device Diagrams by
Package
Package Footprint Compatible Devices Package Status
FFVA676 XCKU3P
page 259
XCKU5P
page 259 Production
FFVB676 XCKU3P
page 261
XCKU5P
page 261 Production
FFRB676 XQKU5P
page 261 Production
SFVB784 XCKU3P
page 263
XCKU5P
page 263 Production
SFRB784 XQKU5P
page 263 Production
FFVD900 XCKU3P
page 265
XCKU5P
page 265
XCKU11P
page 267 Production
FFVE900 XCKU9P
page 269
XCKU13P
page 271 Production
FFVA1156 XCKU11P
page 273
XCKU15P
page 275 Production
FFRA1156 XQKU15P
page 275 Production
FFVE1517 XCKU11P
page 277
XCKU15P
page 279 Production
FFRE1517 XQKU15P
page 279 Production
FFVA1760 XCKU15P
page 281 Production
FFVE1760 XCKU15P
page 283 Production
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Chapter 3: Device Diagrams
Table 3-4: Cross-Reference to Virtex UltraScale+ and XQ Virtex UltraScale+ Device Diagrams by
Package
Package Footprint Compatible Devices Package Status
FFVC1517 XCVU3P
page 285 Production
FFRC1517 XQVU3P
page 285 Production
FLGF1924 XCVU11P
page 287 Production
FSVH1924 XCVU31P
page 289 Production
FLVA2104 XCVU5P
page 291
XCVU7P
page 291 Production
FFRA2104 XQVU7P
page 291 Production
FLGA2104 XCVU9P
page 293 Production
FHGA2104 XCVU13P
page 295 Production
FLVB2104 XCVU5P
page 297
XCVU7P
page 297 Production
FLRB2104 XQVU7P
page 297 Production
FLGB2104 XCVU9P
page 299
XCVU11P
page 301 Production
FHGB2104 XCVU13P
page 303 Production
FLVC2104 XCVU5P
page 305
XCVU7P
page 305 Production
FLGC2104 XCVU9P
page 307
XCVU11P
page 309 Production
FLRC2104 XQVU11P
page 309 Production
FHGC2104 XCVU13P
page 311 Production
FSGD2104 XCVU9P
page 313
XCVU11P
page 315 Production
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Chapter 3: Device Diagrams
FIGD2104 XCVU13P
page 317 Production
FIGD2104 XCVU27P
page 319
XCVU29P
page 321 Engineering Sample
FSVH2104 XCVU33P
page 323
XCVU35P
page 325 Production
FLGA2577 XCVU9P
page 327
XCVU11P
page 329
XCVU13P
page 331 Production
FSGA2577 XCVU13P
page 331 Production
FSGA2577 XCVU27P
page 333
XCVU29P
page 335 Engineering Sample
FSVH2892 XCVU35P
page 337
XCVU37P
page 339 Production
Table 3-4: Cross-Reference to Virtex UltraScale+ and XQ Virtex UltraScale+ Device Diagrams by
Package (Cont’d)
Package Footprint Compatible Devices Package Status
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Chapter 3: Device Diagrams
FBVA676 Package–XCKU035 and XCKU040 and
RBA676 Package–XQKU040
X-Ref Target - Figure 3-1
Figure 3-1: FBVA676 Package—XCKU035 and XCKU040 and
RBA676 Package—XQKU040 I/O Bank Diagram
ug575_c3_01_071314
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 64
Bank 65
Bank 66
Quad 224
Quad 225
Quad 226
Quad 227
24 24
S
23
23
22 22
21 21 20
2019
19
18
18
17 17
16 16
15
15
14
14
S13 13
12 12
S11
11
10
10
99
8877
66
5
54
4
3
32
2
1
1
24
24
S
23 23
22
22
21
21
20 20
19
19
18
18
17 17
16
16
15
15
14
14
S
13 13 12
12
S
11 11
10 10
9
9
8
8
77
6
6
5
5
4
4
3
3
2
2
11
24 24
S23 23
22
22
21 21
20
20
19
19
18
18
17
17 16
1615 15
14
14
S13
13
12 12
S11 11
10 10
998
877
6
6
5
5
4
4
33
22
11
2424
S
23
23
22
22
2121
2020
1919
18
18
17
17
16
16
1515
14
14S
13
13
1212 S
11
11 1010
9
9
8
8
7
7
66
5
54
4
3
3
2
2
1
1
2424
S
2323
2222
21
21
2020
1919
1818
17
17
16
16
15
15 14
14
S
1313
24 24
S
23
23
22
22
21 21
20
20
19
19
18 18
17
17
16 16
15
15
14 14
S13 13
1212
S
1111
1010
9
9
8
8
7
7
66
55
4
4
3
3
22
S1
1
12
12
S
11 11
10 10
998
8
7
7
66
5
5
44
33
2
2
S
1
1
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-2
Figure 3-2: FBVA676 Package—XCKU035 and XCKU040 and
RBA676 Package—XQKU040 Configuration/Power Diagram
ug575_c3_02_071314
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
1816
4
2
5
3
20
0
17
30 28
35
33
34
29
29
29 29
29
29
29
29
29 29
29
29
26 26
26
26
26 26
27 26 26
26
26
35
26 26
26 26
26 26 25
25
25
25
25 25
25
25
25 25
25 25
31
32
25
36
37
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
SFVA784 (XCKU035 and XCKU040)
X-Ref Target - Figure 3-3
Figure 3-3: SFVA784 Package—XCKU035 and XCKU040 I/O Bank Diagram
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Quad 224
Quad 225
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_03_070615
24
24
S23
23 22 22
21 21
20 20
19 19
18
18
17
17 16
1615 15
14 14 S
13
13
12
12
S
11 11
10
10
9
9
88
7
7
6
6
5
5
4
4
3
3
2
2
11
24 24
S
23
23
22 22
21 21
20
2019 19
18 18
17 17
16 16
15 15
14
14
S
13
13
12 12
S
11 11 10 10
99
88
77
66
55
4
4
33
2211
24
24S
23
23
22 22
21 21
20 20 19
19
18 18
17
17
16
16
15
15
14 14
S
13 13
12 12
S11
11 10 10
9
9
88
7
7
6
6
5
5
4
4
3
322
11
24
24
S23 23
22
22
21
21
20
20
19 19
18
18
17 17
16
1615 15
14
14
S
13
13
12 12
S11 11
10
1099
88
77
66
5
5
44
33
2
2
11
24
24
S
2323
22
22
21
21
20
20
19
19
1818
1717 1616
15
15
1414S
13
13
1212
S
1111 10
10
99
8
8
7
7
66
55
4
4
33
22
1
1
24
24
S23
23
2222
21
21
2020
1919
18181717
1616
15
15
1414
S
1313
1212
S
1111
1010
9
9
8
8
77
66
55
4
43
3
22
11
24
24S
23
23
22
22
2121
20
20 1919
18
18
1717
1616
15
15
14
14
S
13
1312
12
S
11
11
10
10
9
9
88
7
7
6
65
54
4
3
3
2
2
11
24
24
S
2323
22
22 2121
20
20
1919
18
18
17
17
16
16
15
15
1414 S
1313
1212
S
111110
10
99
88
7
7
66
5
5
443
3
22
S
1
1
24 24
S
23
23
22
2221
21
20 20
19
19 18
18
17
1716
16
15
15 14
14
S
13 13
12 12
S
11 11
10 10
998
8
7
7
6
655
4
4
33
22S
11
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
(I X|L|NXm u u I I u u u l l u u u I I u u I I I u D u l I l u u D u I I l u D l D I DEDDDDID u I u \ D l D 3-: EDDDDIDDDDE D D D D D D I] D D D E D D D B D D D a D D D u D D D I] D D D [I D D D l D D D D D D D D D D D D D D D Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-4
Figure 3-4: SFVA784 Package—XCKU035 and XCKU040 Configuration/Power Diagram
ug575_c3_04_070615
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30 28
35
33
34
29
2929
29
29 29
29
29 29
29
29
2926
26
26
26 26
26
27
26 26
26 26
35
26 26
26 26
26 2625
25
25
25
25
2525 25
25
25
25 25
31 3225
36 37
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
(I XILINXa m r D 6 D »»»» OQOQGO ®DD OOOOOS )5 Send Feed back
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Chapter 3: Device Diagrams
FBVA900 (XCKU035 and XCKU040)
X-Ref Target - Figure 3-5
Figure 3-5: FBVA900 Package—XCKU035 and XCKU040 I/O Bank Diagram
ug575_c3_05_100715
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
24 24
S
23
23
22 22
21
21
20 20
19 19
18
18
17 17
16 16
15 15
14
14
S
13
13
12 12
S11 11
10 10
9
9
8
8
77
6
6
55
4
4
33
2
21
1
24
24
S
23 23
22
22
21
2120
20 19
19
18 18
17
1716 16
15
15
14
14
S
13
13
12
12
S
11
11
10 10
99
8
8
77
66
5544
3
3
22
1
1
24 24
S
23
23
22 22
21
21
20 20
19
19
18 18
17
17
16 16
15 15
14 14
S
13 13
12 12
S
11 11
10
10
99
88
77
66
5
5
4
4
3
3
22
11
24
24
S23
23
22 22
21 21
20
20
19
19
18 18
17 17
16
16
15 15
14
14
S
13 13
12 12
S
11 11
10
10
9
9
8
8
77
665
5
4
43
3
2
211
24 24
S
23 23
22
22
21
21
20
20
19
19
18 18
17
17
16 16
15
15
14 14
S13 13
12 12
S
11 11
10 10
99
8
8
77
6
6
55
4
4
33
22
11
24
24S
2323
22
22
2121
2020
19
19 18
18
17
17 1616
15
15
14
14
S
1313
12
12
S
1111
10
109
9
8877
6
655
4433
221
1
2424
S
2323
22
22
2121
2020
1919
18
18
1717
16
16
1515
14
14S1313
1212
S
11
11
1010
9
9
8
877
6
6
55
4
4
33
2
2
11
2424 S2323
22222121
202019
19
18
18
17
17
1616
1515
1414
S
13
13
2424
S
23
23
22
222121
20201919
181817
17
16
16
15
15 1414
S1313
1212
S1111
1010
99
887
7
6
6
55
443
322
S
1
1
1212
S11
11
10
10
9
9
88
7
7
6
6
55
44
332
2
S
1
1
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Quad 224
Quad 225
Quad 226
Quad 227
(I XILINX¢ DEDDDDIDDD DDDDIDDDDED DIDDDDEDDDD DDDEDDDDIDD EDDDDIDDDDB DEIDDDDEDDD I ll DDDDDDDDDDDDD DDDDDDDDDD DDDDDDDDDDDDDDD BEEEEUIDDDD Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-6
Figure 3-6: FBVA900 Package—XCKU035 and XCKU040 Configuration/Power Diagram
ug575_c3_06_100715
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
3028
35
33
34
29
292929
29292929
292929
29
26
26
26
26 2626
272626
2626
3526
26
26
26
26
26
2525
25
25
25
25
2525
2525
2525 31
32
25
36
37
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
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Chapter 3: Device Diagrams
FFVA1156 (XCKU025)
X-Ref Target - Figure 3-7
Figure 3-7: FFVA1156 Package—XCKU025 I/O Bank Diagram
Bank 44
Bank 45
Bank 46
Bank 64
Bank 65
Bank 66
Quad 224
Quad 225
Quad 226
ug575_c3_07_032416
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
24
24
S
23 2322 22
21
21
20
20
19
19
18 1817 17
16
16
15
15
14 14 S
13
13
12 12
S
11 11
10
10
99
88
77
6
6
55
4
4
3
3
2
2
1
1
2424S
23
23
2222 21
212020
1919
1818 17
17
1616
1515
14
14
S1313
1212
S11
11
1010
9
98
8
7
7
66
55
44
3
32
2
1
1
24
24
S
23
23 22
22
21
21
20
20
19 19
18
18
17 17 16
1615 15
14 14
S
13
13
12
12 S
11
11
10
10
99
88
7
7
6
6
55
44
33
22
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
18
18
17
17
16
1615
15
14
14
S
13
1312
12
S
11
11
10
109
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
1818
1717 16
1615
15 14
14
S
13
13 12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
5
4
4
3
32
2
S
11
24 24 S
23
2322
22
21 21
20 20
19
19
18
18
17 17
16 16 15
15
14 14
S
13
1312
12
S
11 11
10
10
9
9
88
7
7
6
6
5
5
44
33
22
S1
1
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
(I XILINX¢ DIDIDIDIDIDIDIDIDDDIDDDDDDD I DDDDDDDDDI DDDIDDDIDDDIDD DDDDDDIDDD u DDDIDDDDDD ID EDDDDDI DDH EDDIDD B DDxDlDDDDu DIDDDDDDD l DDDDDDD I u DDEF ID 5 u DDIHHD B I DUDE DD31 l DDDIDDDDBDDBDIDDDDDDEDDI u IDDDDDDD DIDDDDDDDDDIDD u DDDDDDDDDDDDD DDDDDDDDDD DDDDDDDDDDDDDDD I BEBE IDDDD Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-8
Figure 3-8: FFVA1156 Package—XCKU025 Configuration/Power Diagram
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_08_032416
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30 28 35
33
3429
29
29 29
29 29
29
29
29
29
29 29
26 26 26
26
26 26
27
26
2626
26
35
26 26
26
26
26
26
25 25
25
25
25
25
25
25
25 25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n
n n
n
n n
n
nn
n
n n
n
n n
n
n n
n
n
n n
n
n n
n
n n
n
n
n n
n
n n
n
n n
n
n
nn
n
nn
n
nn
n
nnn n
nn
n
nn
n
n
n
n
n
n
n n
n
n
n n
n nn
n
n n
n n
n n
n
nn
n n
n n
n n
n
n
n
n
n
n n
n
n n n
n
n
n n
n
n
n n
n
n n
n n
n
n
n
n
n n
n
nn
n
n
n
n
n
n
n
n
n
n
n
n n
nn
n
n n
n
n n
n
n
n
n n
nn n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n n
n n
n
n
n n
n
n
n n
n n
n n
n
n
n
n
n
n
n
n
n
n
n
nn
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n
nnn
n
n nn
n
n nn
nn
nnnn
n
n
nn
nn
n
nn
nn
n
n
n nn
nn
n
nn
n nn
nn
n
nn
n nnn
n
n
n
n
nn
n
nn
n
nn
n
n
nn
n
nn
n
nn
n
1
1
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
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Chapter 3: Device Diagrams
FFVA1156 (XCKU035)
X-Ref Target - Figure 3-9
Figure 3-9: FFVA1156 Package—XCKU035 I/O Bank Diagram
24
24
S
23 2322 22
21
21
20
20
19
19
18 1817 17
16
16
15
15
14 14 S
13
13
12 12
S
11 11
10
10
99
88
77
6
6
55
4
4
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3
2
2
1
1
2424S
23
23
2222 21
212020
1919
1818 17
17
1616
1515
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14
S1313
1212
S11
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1010
9
98
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7
7
66
55
44
3
32
2
1
1
24
24
S
23
23 22
22
21
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19 19
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17 17 16
1615 15
14 14
S
13
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12 S
11
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10
99
88
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7
6
6
55
44
33
22
1
1
24
24
S
23
23
22 22
21
21
20 20
19 1918
18
17 17
16 16
15 15
14
14S
13 13
12 12
S11
11
10
10
9
9
88
7
766
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5
44
3
3
22
11
24
24
S
23
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22 22
21
2120
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14 14
S13
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12 12
S
11 11
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9
98
877
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2
2
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1
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S
2323
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1615
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S
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1312
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S
11
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109
9
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8
7
7
6
65
5
4
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3
3
2
2
1
1
24
24
S
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22 21 21
20 20
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18 18
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16 16
15 15
14 14
S
13
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S
11
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10
10
9
98
8
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7
66
5
5
4
4
3
3
2
2
1
1
2424S
23
23 2222
21
21 2020
1919
18181717
16
16
1515
1414
S
1313
1212
S
11
11 1010
99
8
87
766
55
4
43
322
1
1
24
24
S
2323
22
22
21
21
20
20
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19
1818
1717 16
1615
15 14
14
S
13
13
24 24 S
23
2322
22
21 21
20 20
19
19
18
18
17 17
16 16 15
15
14 14
S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
5
4
4
3
32
2
S
11
12
12
S
11 11
10
10
9
9
88
7
7
6
6
5
5
44
33
22
S1
1
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
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34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
ug575_c3_09_100715
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Quad 224
Quad 225
Quad 226
Quad 227
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-10
Figure 3-10: FFVA1156 Package—XCKU035 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30 28 35
33
3429
29
29 29
29 29
29
29
29
29
29 29
26 26 26
26
26 26
27
26
2626
26
35
26 26
26
26
26
26
25 25
25
25
25
25
25
25
25 25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
n n
n
n n
n
n n
n
nn
n
n n
n
n n
n
n n
n
n
n n
n
n n
n
n n
n
n
n n
n
n n
n
n n
n
n
nn
n
nn
n
nn
n
nnn n
nn
n
nn
n
1
1
2
2
3
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25
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31
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVA1156 (XCKU040) and RFA1156 (XQKU040)
X-Ref Target - Figure 3-11
Figure 3-11: FFVA1156 Package—XCKU040 and RFA1156 Package—XQKU040 I/O Bank Diagram
24
24
S
23 2322 22
21
21
20
20
19
19
18 1817 17
16
16
15
15
14 14 S
13
13
12 12
S
11 11
10
10
99
88
77
6
6
55
4
4
3
3
2
2
1
1
2424S
23
23
2222 21
212020
1919
1818 17
17
1616
1515
14
14
S1313
1212
S11
11
1010
9
98
8
7
7
66
55
44
3
32
2
1
1
24
24
S
23
23 22
22
21
21
20
20
19 19
18
18
17 17 16
1615 15
14 14
S
13
13
12
12 S
11
11
10
10
99
88
7
7
6
6
55
44
33
22
1
1
24
24
S
23
23
22 22
21
21
20 20
19 1918
18
17 17
16 16
15 15
14
14S
13 13
12 12
S11
11
10
10
9
9
88
7
766
5
5
44
3
3
22
11
24
24
S
23
23
22 22
21
2120
20
19
19
18
18
17
17
16
16
15
15
14 14
S13
13
12 12
S
11 11
10
10
9
98
877
6
6
5
5
4
4
3
3
2
2
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
18
18
17
17
16
1615
15
14
14
S
13
1312
12
S
11
11
10
109
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24
24
S
23
23
22
22 21 21
20 20
19
19
18 18
17
17
16 16
15 15
14 14
S
13
13
12
12
S
11
11
10
10
9
98
8
7
7
66
5
5
4
4
3
3
2
2
1
1
2424S
23
23 2222
21
21 2020
1919
18181717
16
16
1515
1414
S
1313
1212
S
11
11 1010
99
8
87
766
55
4
43
322
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
1818
1717 16
1615
15 14
14
S
13
13
24 24 S
23
2322
22
21 21
20 20
19
19
18
18
17 17
16 16 15
15
14 14
S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
5
4
4
3
32
2
S
11
12
12
S
11 11
10
10
9
9
88
7
7
6
6
5
5
44
33
22
S1
1
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-12
Figure 3-12: FFVA1156 Package—XCKU040 and RFA1156 Package—XQKU040
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30 28 35
33
3429
29
29 29
29 29
29
29
29
29
29 29
26 26 26
26
26 26
27
26
2626
26
35
26 26
26
26
26
26
25 25
25
25
25
25
25
25
25 25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
n n
n
n n
n
n n
n
nn
n
n n
n
n n
n
n n
n
n
n n
n
n n
n
n n
n
n
n n
n
n n
n
n n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVA1156 (XCKU060) and RFA1156 (XQKU060)
X-Ref Target - Figure 3-13
Figure 3-13: FFVA1156 Package—XCKU060 and RFA1156 Package—XQKU060 I/O Bank Diagram
24
24
S
23 2322 22
21
21
20
20
19
19
18 1817 17
16
16
15
15
14 14 S
13
13
12 12
S
11 11
10
10
99
88
77
6
6
55
4
4
3
3
2
2
1
1
2424S
23
23
2222 21
212020
1919
1818 17
17
1616
1515
14
14
S1313
1212
S11
11
1010
9
98
8
7
7
66
55
44
3
32
2
1
1
24
24
S
23
23 22
22
21
21
20
20
19 19
18
18
17 17 16
1615 15
14 14
S
13
13
12
12 S
11
11
10
10
99
88
7
7
6
6
55
44
33
22
1
1
24
24
S
23
23
22 22
21
21
20 20
19 1918
18
17 17
16 16
15 15
14
14S
13 13
12 12
S11
11
10
10
9
9
88
7
766
5
5
44
3
3
22
11
24
24
S
23
23
22 22
21
2120
20
19
19
18
18
17
17
16
16
15
15
14 14
S13
13
12 12
S
11 11
10
10
9
98
877
6
6
5
5
4
4
3
3
2
2
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
18
18
17
17
16
1615
15
14
14
S
13
1312
12
S
11
11
10
109
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24
24
S
23
23
22
22 21 21
20 20
19
19
18 18
17
17
16 16
15 15
14 14
S
13
13
12
12
S
11
11
10
10
9
98
8
7
7
66
5
5
4
4
3
3
2
2
1
1
2424S
23
23 2222
21
21 2020
1919
18181717
16
16
1515
1414
S
1313
1212
S
11
11 1010
99
8
87
766
55
4
43
322
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
1818
1717 16
1615
15 14
14
S
13
13
24 24 S
23
2322
22
21 21
20 20
19
19
18
18
17 17
16 16 15
15
14 14
S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
5
4
4
3
32
2
S
11
12
12
S
11 11
10
10
9
9
88
7
7
6
6
5
5
44
33
22
S1
1
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
0
0
0
127
0
127
3
3
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Quad 127
Quad 128
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-14
Figure 3-14: FFVA1156 Package—XCKU060 and RFA1156 Package—XQKU060
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30 28 35
33
3429
29
29 29
29 29
29
29
29
29
29 29
26 26 26
26
26 26
27
26
2626
26
35
26 26
26
26
26
26
25 25
25
25
25
25
25
25
25 25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVA1156 (XCKU095) and RFA1156 (XQKU095)
X-Ref Target - Figure 3-15
Figure 3-15: FFVA1156 Package—XCKU095 and RFA1156 Package—XQKU095 I/O Bank Diagram
24
24
S
23
23
22 22
21
2120
20
19
19
18
18
17
17
16
16
15
15
14 14
S13
13
12 12
S
11 11
10
10
9
98
877
6
6
5
5
4
4
3
3
2
2
1
1
24
24
S
23
23
22 22
21
21
20 20
19 1918
18
17 17
16 16
15 15
14
14S
13 13
12 12
S11
11
10
10
9
9
88
7
766
5
5
44
3
3
22
11
24
24
S
23
23 22
22
21
21
20
20
19 19
18
18
17 17 16
1615 15
14 14
S
13
13
12
12 S
11
11
10
10
99
88
7
7
6
6
55
44
33
22
1
1
24
24
S
23 2322 22
21
21
20
20
19
19
18 1817 17
16
16
15
15
14 14 S
13
13
12 12
S
11 11
10
10
99
88
77
6
6
55
4
4
3
3
2
2
1
1
2424S
23
23
2222 21
212020
1919
1818 17
17
1616
1515
14
14
S1313
1212
S11
11
1010
9
98
8
7
7
66
55
44
3
32
2
1
1
24
24
S
23
23
22
22 21 21
20 20
19
19
18 18
17
17
16 16
15 15
14 14
S
13
13
12
12
S
11
11
10
10
9
98
8
7
7
66
5
5
4
4
3
3
2
2
1
1
2424S
23
23 2222
21
21 2020
1919
18181717
16
16
1515
1414
S
1313
1212
S
11
11 1010
99
8
87
766
55
4
43
322
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
18
18
17
17
16
1615
15
14
14
S
13
1312
12
S
11
11
10
109
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24 24 S
23
2322
22
21 21
20 20
19
19
18
18
17 17
16 16 15
15
14 14
S
13
1312
12
S
11 11
10
10
9
9
88
7
7
6
6
5
5
44
33
22
1
1
24
24
S
2323
22
22
21
21
20
20
19
19
1818
1717 16
1615
15 14
14
S
13
13 12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
5
4
4
3
32
2
S
11
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
130
3
3
3
130
1
130
1
2
130
2
2
2
130
1
130
1
1
1
130
0
130
0
0
130
0
0
0
130
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Quad 129
Quad 130
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228 SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-16
Figure 3-16: FFVA1156 Package—XCKU095 and RFA1156 Package—XQKU095
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30 28 35
33
3429
29
29 29
29 29
29
29
29
29
29 29
26 26 26
26
26 26
27
26
2626
26
35
26 26
26
26
26
26
25 25
25
25
25
25
25
25
25 25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_16_100715
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Chapter 3: Device Diagrams
FFVA1517 (XCKU060)
X-Ref Target - Figure 3-17
Figure 3-17: FFVA1517 Package—XCKU060 I/O Bank Diagram
24
24
S
23
23
22
22
21
21
20 2019
19 18
18
17
17 16
16
15
15
14
14
S13
13 12
12S
11
11
10
10 99
88
7
7
66
5
5
44
33
2
2
1
1
24
24
S
23 23 22 22
21 21 20 20
19 19
18
18
17 17
16
16
15
15
14 14
S13
13 12
12
S
11
11 10
109
988
7
7
6
6
5
5
44
3
3
22
11
24 24
S
23
23
22 22 21
2120
20 19 19
18 18
17 17
16 16
15
15
14
14
S
13
13
12
12
S
11
11
10
10
9
9
88
7
7
6
6
55
4
43
3
2
2
1
1
24 24
S
23
2322
22
21
21
20
20
19
19
18
18
17
17
16 16
15
15
14 14
S13 13
12
12
S
11
11
10
10
9
9
88
77
66
5
5
44
3
3
22
1
1
24
24S
23
23
22
22
21
21
20
20
19
19
18
18
17 17
16
16
15
15
14
14
S13
13
12
12S
11
11
10 109
9
8
87
7
6
6
55
4
4
3
3
22
1
1
24
24S
23 23
22
22
21
21 20 20
19
19
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11
10 10
9
9
8
8
77
6
6
5
5
4
4
33
2
2
11
24
24 S
23 23
22 22
21 21
20 20
19
19
18 18
17
17
16
16 15
15
14
14
S
13 13
12 12
S
11
11
10
10
9
9
8
877
6
6
5
5
44
33
2
2
1
1
24
24
S
2323
22
22
2121
20
20
1919
1818 17
17
1616
1515
14
14
S
13
13
12
12S
1111
1010 9
9
88
7
7
66
5
5
4
4
3
3
22
1
1
2424
S
23
23
22
22 21
21
20
20
19
19
18
18
17
17
16
16
15
15
1414
S
13
13
12
12
S
1111
10
10
99
88
7
7
66
55
44
33
2
211
24
24
S
23
23
22
22 21
21
20
20
19
19
18
1817 17
16
16
15 15
14 14
S
13 13
12 12
S
11 11
10 10
9
9
88
7
7
6
6
5
5
44
3
3
2
2
1
1
24
24
S
23
23
22
22
21
21
2020
1919
1818
1717
1616
15
15
1414
S
13
13
2424
S23
23 22
22
21
21 20
2019
19
1818
17
17 16
16
15
15
1414 S13
13 12
12S1111
10109
98
8
77
6
6
55
4
4
33
22
S
11
12
12
S
1111
1010
9
9
8
87
76
65
5
4
4
3
3
2
2S
1
1
3
3
3
126
3
126
1
1
126
22
2
126
2
126
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
11
1
127
1
127
0
0
127
0
0
0
127
0
127
33
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
00
0
128
0
128
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
25
VCCO
25
VCCO
25
VCCO
25
VCCO
25
VCCO
25
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 24
Bank 25
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Quad 126
Quad 127
Quad 128
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
ug575_c3_17_100715
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-18
Figure 3-18: FFVA1517 Package—XCKU060 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5 3
20
0
17
3028
3533
34 29
29
29
29 29
2929
29
2929
29
29 26
26
26
26
2626 2726
26 26
26
35
2626
2626
26
26
25
2525
25 25
2525
25
25
25
25
25
31
3225
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n
n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVA1517 (XCKU085 and XCKU115)
X-Ref Target - Figure 3-19
Figure 3-19: FLVA1517 Package—XCKU085 and XCKU115 I/O Bank Diagram
24
24
S
23
23
22
22
21
21
20 2019
19 18
18
17
17 16
16
15
15
14
14
S13
13 12
12S
11
11
10
10 99
88
7
7
66
5
5
44
33
2
2
1
1
24
24
S
23 23 22 22
21 21 20 20
19 19
18
18
17 17
16
16
15
15
14 14
S13
13 12
12
S
11
11 10
109
988
7
7
6
6
5
5
44
3
3
22
11
24 24
S
23
23
22 22 21
2120
20 19 19
18 18
17 17
16 16
15
15
14
14
S
13
13
12
12
S
11
11
10
10
9
9
88
7
7
6
6
55
4
43
3
2
2
1
1
24 24
S
23
2322
22
21
21
20
20
19
19
18
18
17
17
16 16
15
15
14 14
S13 13
12
12
S
11
11
10
10
9
9
88
77
66
5
5
44
3
3
22
1
1
24
24S
23
23
22
22
21
21
20
20
19
19
18
18
17 17
16
16
15
15
14
14
S13
13
12
12S
11
11
10 109
9
8
87
7
6
6
55
4
4
3
3
22
1
1
24
24S
23 23
22
22
21
21 20 20
19
19
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11
10 10
9
9
8
8
77
6
6
5
5
4
4
33
2
2
11
24
24 S
23 23
22 22
21 21
20 20
19
19
18 18
17
17
16
16 15
15
14
14
S
13 13
12 12
S
11
11
10
10
9
9
8
877
6
6
5
5
44
33
2
2
1
1
2424
S23
23 22
22
21
21 20
2019
19
1818
17
17 16
16
15
15
1414 S13
13 12
12
S
1111
1010
9
9
8
87
76
65
5
4
4
3
3
2
2S
1
1
24
24
S
2323
22
22
2121
20
20
1919
1818 17
17
1616
1515
14
14
S
13
13
12
12S
1111
1010 9
9
88
7
7
66
5
5
4
4
3
3
22
1
1
2424
S
23
23
22
22 21
21
20
20
19
19
18
18
17
17
16
16
15
15
1414
S
13
13
12
12
S
1111
10
10
99
88
7
7
66
55
44
33
2
211
24
24
S
23
23
22
22 21
21
20
20
19
19
18
1817 17
16
16
15 15
14 14
S
13 13
12 12
S
11 11
10 10
9
9
88
7
7
6
6
5
5
44
3
3
2
2
1
1
24
24
S
23
23
22
22
21
21
2020
1919
1818
1717
1616
15
15
1414
S
13
13 12
12S1111
10109
98
8
77
6
6
55
4
4
33
22
S
11
3
3
3
126
3
126
1
1
126
22
2
126
2
126
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
11
1
127
1
127
0
0
127
0
0
0
127
0
127
33
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
00
0
128
0
128
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
24
VCCO
25
VCCO
25
VCCO
25
VCCO
25
VCCO
25
VCCO
25
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 24
Bank 25
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Quad 126
Quad 127
Quad 128
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
ug575_c3_19_100715
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-20
Figure 3-20: FLVA1517 Package—XCKU085 and XCKU115 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5 3
20
0
17
19
3028
3533
34 29
29
29
29 29
2929
29
2929
29
29 26
26
26
26
2626 2726
26 26
26
35
2626
2626
26
26
25
2525
25 25
2525
25
25
25
25
25
31
3225
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_20_100715
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Chapter 3: Device Diagrams
FFVC1517 (XCKU095)
X-Ref Target - Figure 3-21
Figure 3-21: FFVC1517 Package—XCKU095 I/O Bank Diagram
24
24
S
23 23
22
22
21
21
20 20
19
19
18
1817
17
16
1615 15
14
14 S
13 13
12
12
S11
11
10
10
99
88
77
665
5
44
3
3
22
11
24
24
S
23
23
22 22
21
21
20 20
19 19
18 18
17
17
16 16
15
15
14 14
S
13 13
12 12
S
11 11
10
10 99
8
8
77
66
5
5
4
4
3
322
11
2424
S
23
23
22
22
21
212020
1919
1818
17
17
1616
1515
1414
S
1313
1212
S
1111
10
10
9
98
8
7
7
6
6
5
54
4
33
2
2
1
12424
S23
2322
22
21
2120
20
19
19
18
1817
17
16
16 15
15
14
14
S
13
13
1212
S
11
11 10
10
99
88
7
7
66
55
4
4
33
2
2
11
24
24
S
23
23
22
22
21
21
202019
19
18
181717
16
16
1515
1414
S
1313
12
12 S
11
11
1010
9
9
8
8
7
7
6
6
55
44
3
3
22
1
1
24 24 S
23
23
22
22
21
21
20 20
19
19
18
18
17 17
16 1615
15 14
14 S
13
13
12 12 S
11 1110
10
99
88
7
76
6
5
5
4
4
3
3
22
112424
S
2323
222221
21
20
2019
19
1818
17
17
16
16
1515
1414
S
13
13
12
12
S
11
11
10
10 9
9
88
7
7
6
6
5
5
4
43
3
22
11
2424
S
23
23
22
22
21
21
2020
19
19
18
18
17
17
16
16
15
15
1414
S13
13
12
12
S
11
11
10
109
9
8
8
77
6
6
55
44
33
2
21
1
24
24
S2323
22
22
21
21
20
20
19
19
1818
17
17
1616
15
15
1414S
1313
1212 S
1111
10
10
9
98
8
77
6
6
5
5
4
43
32
2
1
1
24 24
S23
23
22 22
21
2120 20
19 19
18 1817
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
88
7
7
6
655
443
322
S
1
1
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
1
125
11
1
125
0
125
0
0
125
0
0
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
128
3
3
3
128
1
128
1
2
128
2
2
2
128
1
128
1
1
1
128
0
128
0
0
128
0
0
0
128
3
129
3
3
3
129
1
129
1
2
129
22
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 65
Bank 66
Bank 67
Bank 68
Bank 84
Bank 94
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-22
Figure 3-22: FFVC1517 Package—XCKU095 Configuration/Power Diagram
8 7
23
24 21
22
1011
9
12
1
15
13
6
14
19
18
16
4
2
5
320
0
17
30 28 35
33
34
29
29
29
29
29 29
29
29
29
29
29 29
26 2626
26 26
26 27
26
26
26 26 35
26 2626
26
26 26
25 25
25
25 25
25
25
25
25
25
25
25
31 32
25
36 37
E
E
E
E E
E
E
E
E
E
E
E
E E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVD1517 (XCKU115) and RLD1517 (XQKU115)
X-Ref Target - Figure 3-23
Figure 3-23: FLVD1517 Package—XCKU115 and RLD1517 Package—XQKU115 I/O Bank Diagram
24
24
S
23
23
22
2221
21
2020
1919
18
1817
17
16
16
1515
1414
S
1313
1212
S
11
11
1010 9
9
88
7
7
665
54
43
3
2
2
S
1
1
24 24 S23
23 22 22
21 21
20 20
19
19
18
18
17
17
16 16
15 15
14 14
S
13
13
12
12S11
11
10
1099
8877
66
5
5
4
4
33
22
11
12
12
S
11 11
10 10
99
887
76
6
55
443
3
22
1
1
24 24 S
23 2322 2221 21
20 20
19 19
18
18
17 17
16 16
15 15 14 14
S13 13
12 12
S
11 11
10 10
998
8
77
6
655
44
33
22
11
24
24
S
23
2322
22
21
21
20 20
19 19
18
18
17
17
16 16
15
15
14
14
S
13
13
12 12
S
11
11
10 10
9
9
88
7
7
6
65
544
33
2
2
1
1
24
24
S
23
23
22
22
2121
20
20
19
19
18
18
17
17
16
16
15
15
1414
S
1313
12
12
S
1111
1010
9
9
88
7
7
6
655
44
3
3
221
1
24
24
S
2323
22
22
2121
20
20
1919
1818
171716
16 151514
14S1313
12
12
S
11
11
1010
9
98
877
665
54
4
3
3
22
S
1
1
33
3
126
3
126
1
1
126
22
2
126
2
126
11
1
126
1
126
0
0
126
00
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
0
0
0
127
0
127
3
3
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3
131
3
131
1
1
131
2
2
2
131
2
131
1
1
1
131
1
131
0
0
131
0
0
0
131
0
131
33
3
132
3
132
1
1
132
22
2
132
2
132
11
1
132
1
132
0
0
132
00
0
132
0
132
3
3
3
133
3
133
1
1
133
2
2
2
133
2
133
G
V
1
1
1
133
1
133
0
0
133
0
0
0
133
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Bank 65
Bank 66
Bank 67
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 126
Quad 127
Quad 128
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_23_100715
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-24
Figure 3-24: FLVD1517 Package—XCKU115 and RLD1517 Package—XQKU115
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
1816
4
2
5
3
20 0
17
19
30
28
35
33
34
29
2929
29
2929
2929
29
2929
29
26
26
2626
2626
27
2626
2626
35
26
26
2626 26
26
2525
25
25
2525 25
2525
25 25
25
31
32
25
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E E
E
E E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E E
E
E E
E
E E
E
V V
V
V V
V
V V
V V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V
V V
V
V V
V
V V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
nn
n n
nn
nnn n
nn
n n
nn
nn
n n
nn
n n
nn
nn
n n
nn
n n
nn
nn
n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVB1760 (XCKU095)
X-Ref Target - Figure 3-25
Figure 3-25: FFVB1760 Package—XCKU095 I/O Bank Diagram
24 24 S
23
2322
22 21 21
20 20
19 19
18
18
17
17
16
16
15
15
14 14 S
13 13
12 12
S
11 11
10
10
998
877
66
5
5
44
3
3
22
11
24
24
S
23 23
22
22
21
21
20 20
19 19
18 18
17
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
8
87
7
66
55
4
4
33
22
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
1817 17
16 16
15 15 14 14
S13 13
12 12S
11 1110
10 99
88
7
7
66
5
5
4
43
32
2
1
1
24
24
S
23 23
22
22
21
21
20 20
19 19 18
18
17
17
16 16
15 15
14 14
S
13 13
12 12
S
11
11 10 10
9
9
8
87
7
66
55
443
322
11
24
24
S
23 23
22 22
21
21
20
20
19
19
18 18
17 17
16
1615
15
14 14
S
13
13
12
12
S
11
11
10 10
9
9
8
8
7
7
66
55
44
3
3
2
2
1
1
2424
S
2323
2222
2121
20
20 19
19
1818
1717
1616 15
15
1414
S
13
13
12
12
S
1111
10
10
9
9
8
8
7
7
66
55
4
4
3
3
2
2
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10 10
99
8
8
7
7
6
6
5
5
44
3
3
2
21
112
12
S
11
11
10
10
9
9
8
8
7
766
5
5
4
4
33
2
2
1
1
24
24
S
23
23
22 22
21
21
20 20 19
19
18 18
17 17
16
16
15
15
14 14
S
13
13
12
12
S
11 11
10 10
99
8
87
7
66
55
4
4
33
22
1
1
2424
S2323
2222
21
21
2020 1919
18
18
17
17
1616
15
15
14
14
S
1313
1212 S
1111 10
10
99
8
8
7
7
66
5
5
44
3
3
2
2
1
1
24
24
S
23 23
22
22
21
2120
20
19 19
18 18
17
17
16
16
15
15
14
14
S
13 13
12 12
S
11 11
10
10
9
9
88
7
7
66
5
5
4
4
3
322
11
2424
S
23
23
22
22 21
21
20
20
19
19
18
18
17
17
1616
15
15 1414
S
1313
1212
S
11
111010
9988
77
6
6
5
5
4
4
33
22
1
1
2424
S
2323
2222
21
21
20
20 1919
18
18 1717
1616
15
15
1414
S13
13
12
12
S
111110
10
9
9
8
8
7
7
66
5
5
4
433
2
2
1
1
2424
S2323
2222
21
21
2020
19
19
181817
17
16
16
1515
14
14
S
1313
1212
S
11
11
1010
9
9
8
877
6
6
5
544
33
2
2
S
1
1
3
128
3
3
3
128
1
128
1
2
128
2
2
2
128
1
128
1
1
1
128
0
128
0
0
128
0
0
0
128
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
130
3
3
3
130
1
130
1
2
130
22
2
130
1
130
1
1
1
130
0
130
0
0
130
0
0
0
130
3
131
3
3
3
131
1
131
1
2
131
22
2
131
1
131
1
1
1
131
0
131
0
0
131
0
0
0
131
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
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42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 49
Bank 50
Bank 51
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 84
Bank 94
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-26
Figure 3-26: FFVB1760 Package—XCKU095 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30
28
35
33
34
29 29
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29
29 29 29
29
29 29
29 29
26
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26
26 26
27
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26
26
26
35
26 26
26 26
26 26
25
25 25
25
25 25
25 25
25
25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
n n
nnn n
nn
nnn n
nnn n
nn
nnn n
1
1
2
2
3
3
4
4
5
5
6
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41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVB1760 (XCKU085)
X-Ref Target - Figure 3-27
Figure 3-27: FLVB1760 Package—XCKU085 I/O Bank Diagram
24 24 S
23
2322
22 21 21
20 20
19 19
18
18
17
17
16
16
15
15
14 14 S
13 13
12 12
S
11 11
10
10
998
877
66
5
5
44
3
3
22
11
24
24
S
23 23
22
22
21
21
20 20
19 19
18 18
17
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
8
87
7
66
55
4
4
33
22
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
1817 17
16 16
15 15 14 14
S13 13
12 12S
11 1110
10 99
88
7
7
66
5
5
4
43
32
2
1
1
24
24
S
23 23
22
22
21
21
20 20
19 19 18
18
17
17
16 16
15 15
14 14
S
13 13
12 12
S
11
11 10 10
9
9
8
87
7
66
55
443
322
11
24
24
S
23 23
22 22
21
21
20
20
19
19
18 18
17 17
16
1615
15
14 14
S
13
13
12
12
S
11
11
10 10
9
9
8
8
7
7
66
55
44
3
3
2
2
1
1
2424
S
23
23
22
22 21
21
20
20
19
19
18
18
17
17
1616
15
15 1414
S
1313
1212
S
11
111010
9988
77
6
6
5
5
4
4
33
22
1
1
2424
S
2323
2222
21
21
20
20 1919
18
18 1717
1616
15
15
1414
S13
13
12
12
S
111110
10
9
9
8
8
7
7
66
5
5
4
433
2
2
1
1
2424
S
2323
2222
2121
20
20 19
19
1818
1717
1616 15
15
1414
S
13
13
12
12
S
1111
10
10
9
9
8
8
7
7
66
55
4
4
3
3
2
2
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10 10
99
8
8
7
7
6
6
5
5
44
3
3
2
21
1
24
24
S
23
23
22 22
21
21
20 20 19
19
18 18
17 17
16
16
15
15
14 14
S
13
13
12
12
S
11 11
10 10
99
8
87
7
66
55
4
4
33
22
S1
1
2424
S2323
2222
21
21
2020 1919
18
18
17
17
1616
15
15
14
14
S
1313
1212 S
1111 10
10
99
8
8
7
7
66
5
5
44
3
3
2
2
1
1
24
24
S
23 23
22
22
21
2120
20
19 19
18 18
17
17
16
16
15
15
14
14
S
13 13
12 12
S
11 11
10
10
9
9
88
7
7
66
5
5
4
4
3
322
11
2424
S2323
2222
21
21
2020
19
19
181817
17
16
16
1515
14
14
S
1313
1212
S
11
11
1010
9
9
8
877
6
6
5
544
33
2
2
S
1
1
3
3
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3
131
3
131
1
1
131
2
2
2
131
2
131
1
1
1
131
1
131
0
0
131
0
0
0
131
0
131
3
3
3
132
3
132
1
1
132
22
2
132
2
132
1
1
1
132
1
132
0
0
132
0
0
0
132
0
132
G
V
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 49
Bank 50
Bank 51
Bank 52
Bank 65
Bank 66
Bank 67
Bank 84
Bank 94
Quad 128
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 230
Quad 231
Quad 232 SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-28
Figure 3-28: FLVB1760 Package—XCKU085 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
20
0
17
19
30
28
35
33
34
29 29
29
29
29 29 29
29
29 29
29 29
26
26
26
26
26 26
27
26
26
26
26
35
26 26
26 26
26 26
25
25 25
25
25 25
25 25
25
25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
n n
n
n n
n n nn
n
n n
n
n n
n
n n
n
nnn n
nn
nnn n
nnn n
nn
nnn n
n
n
n
n
n
n
n
n
n
n
n
n
nn n
n
n
n
n
n n
n
n
n n
n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVB1760 (XCKU115)
X-Ref Target - Figure 3-29
Figure 3-29: FLVB1760 Package—XCKU115 I/O Bank Diagram
24 24 S
23
2322
22 21 21
20 20
19 19
18
18
17
17
16
16
15
15
14 14 S
13 13
12 12
S
11 11
10
10
998
877
66
5
5
44
3
3
22
11
24
24
S
23 23
22
22
21
21
20 20
19 19
18 18
17
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
8
87
7
66
55
4
4
33
22
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
1817 17
16 16
15 15 14 14
S13 13
12 12S
11 1110
10 99
88
7
7
66
5
5
4
43
32
2
1
1
24
24
S
23 23
22
22
21
21
20 20
19 19 18
18
17
17
16 16
15 15
14 14
S
13 13
12 12
S
11
11 10 10
9
9
8
87
7
66
55
443
322
11
24
24
S
23 23
22 22
21
21
20
20
19
19
18 18
17 17
16
1615
15
14 14
S
13
13
12
12
S
11
11
10 10
9
9
8
8
7
7
66
55
44
3
3
2
2
1
1
2424
S
23
23
22
22 21
21
20
20
19
19
18
18
17
17
1616
15
15 1414
S
1313
1212
S
11
111010
9988
77
6
6
5
5
4
4
33
22
1
1
2424
S
2323
2222
21
21
20
20 1919
18
18 1717
1616
15
15
1414
S13
13
12
12
S
111110
10
9
9
8
8
7
7
66
5
5
4
433
2
2
1
1
2424
S
2323
2222
2121
20
20 19
19
1818
1717
1616 15
15
1414
S
13
13
12
12
S
1111
10
10
9
9
8
8
7
7
66
55
4
4
3
3
2
2
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10 10
99
8
8
7
7
6
6
5
5
44
3
3
2
21
112
12
S
11
11
10
10
9
9
8
8
7
766
5
5
4
4
33
2
2
1
1
24
24
S
23
23
22 22
21
21
20 20 19
19
18 18
17 17
16
16
15
15
14 14
S
13
13
12
12
S
11 11
10 10
99
8
87
7
66
55
4
4
33
22
S1
1
2424
S2323
2222
21
21
2020 1919
18
18
17
17
1616
15
15
14
14
S
1313
1212 S
1111 10
10
99
8
8
7
7
66
5
5
44
3
3
2
2
1
1
24
24
S
23 23
22
22
21
2120
20
19 19
18 18
17
17
16
16
15
15
14
14
S
13 13
12 12
S
11 11
10
10
9
9
88
7
7
66
5
5
4
4
3
322
11
2424
S2323
2222
21
21
2020
19
19
181817
17
16
16
1515
14
14
S
1313
1212
S
11
11
1010
9
9
8
877
6
6
5
544
33
2
2
S
1
1
3
3
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3
131
3
131
1
1
131
2
2
2
131
2
131
1
1
1
131
1
131
0
0
131
0
0
0
131
0
131
3
3
3
132
3
132
1
1
132
22
2
132
2
132
1
1
1
132
1
132
0
0
132
0
0
0
132
0
132
3
3
3
133
3
133
1
1
133
22
2
133
2
133
G
V
1
1
1
133
1
133
0
0
133
0
0
0
133
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 49
Bank 50
Bank 51
Bank 52
Bank 53
Bank 65
Bank 66
Bank 67
Bank 84
Bank 94
Quad 128
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_29_100715
(I XILINX¢ DI D E DDID ED IDDDDEDEDDI DBDDDDIDD u u IDDDDEDD I I DDEDDDDI DUDE-IEEEEU I DDDDDDDDDDDDDDD DDDDDDDDDD DUDUDDUDDUDUU Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-30
Figure 3-30: FLVB1760 Package—XCKU115 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
20
0
17
19
30
28
35
33
34
29 29
29
29
29 29 29
29
29 29
29 29
26
26
26
26
26 26
27
26
26
26
26
35
26 26
26 26
26 26
25
25 25
25
25 25
25 25
25
25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVD1924 (XCKU115)
X-Ref Target - Figure 3-31
Figure 3-31: FLVD1924 Package—XCKU115 I/O Bank Diagram
24 24
S
23
23
22 22
21 21
20
20
19
19
18
18
17
1716
16
15 15
14
14
S13
13
12 12S
11 11
10
10998
877
6
6
5
5
44
3
3
2
21
1
24
24
S
23 23
22
22
21 21
20
20
19 1918
18
17 17
16 16
15
15
14
14S
13 13
12
12
S11 11
10
10 9
988
7
7
665
54
4
3
3
22
1
1
24 24
S23 23
22 22
21
21
20 20
19 19
18 18
17
17
16 16 15 15
14 14
S13
13
12
12
S
11 11
10
10
9
98
87
766
5
54
4
33
2
2
1
1
24
24S
23 23 22
22
21
21 20
20
19
1918
18
17 17
16 1615
15
14
14
S
13 13 12 12
S
11
11
10
10
99
88
77
6
6
5
54
4
3
3
22
11
24
24
S
23
23
22
22
21
21
20 20
19
19
18
1817
17
16
16
15
15
14 14
S13
13
12
12
S
11
11
10
10
9
9
887
766
55
4
4
33
2
2
1
1
24 24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14 14
S
13
13
12 12
S11 11
10
10
9
9
8
8
7
7
66
5
5
4
4
3
3
2
2
11
24
24
S
23
23
22 22
21
21
20 20
19 19
18
18 17
17
16
16
15
15
14
14
S
13
13
12
12
S
11 11 10
10
99
8
8
7
7
66
554
4
33
2
2
11
24
24
S
23 23
22
22
21
21 20
20
19
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12S
11
11
10 10 9
9
8
8
77
6
6
5
5
4
4
3
3
2
2
1
1
24
24
S
2323
2222
21
21
2020
1919
181817
17
1616
15
15
1414
S
1313
12
12S11
1110
10 9
9
8
8
7
7
66
5
5
443
322S
1
1
24
24
S23
23 22
22
2121
2020
1919
1818
1717
1616
1515
1414S
13
13
1212
S
11
11
10
10
9
9
88
77
6
65
5
4
4
33
2
2
1
1
24
24
S
2323
22
22
2121
20
20
1919
18
18
1717 16
1615
15
14
14
S
13
13 1212
S
11
11
1010
9
9
88
7
76
6
5
5
4
43
3
2
2
11
24
24
S
23
23
22
22
21
21
202019
19
1818
17
171616
1515
1414
S
1313
12
12 S
11
11
10
10
9
9
8
8
77
6
6
5
54
43
3
22
S11
2424
S
2323
2222 2121
20
20
19
19
18
18
1717
16
16
1515
14
14
S
1313
1212
S
11
11
1010
99
8
8
77
66
5
54
4
3
3
2
2
1
1
24
24
S
2323
22
22 2121
2020
19
19
181817
17
16
16
1515
1414S
1313
12
12S
11
11
10
10
9
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24
24
S
2323
2222
2121
20
20
1919
18
18
17
1716
16 1515
1414
S1313
1212
S
11
11
10
10
9
9
8
87
7
6
6
55
44
33
2
2
11
24
24
S23
23 2222
21
21
2020
1919
18
18
1717
16
16
15
15
14
14
S13
13
1212
S
111110
10
9
9
88
77
6
6
55
4
4
3
3
2
2
S
1
1
3
3
3
126
3
126
1
1
126
2
2
2
126
2
126
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
0
0
0
127
0
127
33
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
00
0
128
0
128
3
3
3
131
3
131
1
1
131
22
2
131
2
131
1
1
1
131
1
131
0
0
131
0
0
0
131
0
131
3
3
3
132
3
132
1
1
132
2
2
2
132
2
132
1
1
1
132
1
132
0
0
132
0
0
0
132
0
132
3
3
3
133
3
133
1
1
133
2
2
2
133
2
133
G
V
1
1
1
133
1
133
0
0
133
0
0
0
133
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
GG
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
ug575_c3_31_100715
Bank 44
Bank 45
Bank 46
Bank 47
Bank 50
Bank 51
Bank 52
Bank 53
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 126
Quad 127
Quad 128
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-32
Figure 3-32: FLVD1924 Package—XCKU115 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
200
17
19
30
28
35
3334
2929
29
29
2929
2929
292929
29
2626
26
26
2626
27
2626
26
2635 26
2626
26 26
26
25
25
25
25
2525
25
25
2525 25
253132 25
36
37
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
GG
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
ug575_c3_32_100715
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVF1924 (XCKU085)
X-Ref Target - Figure 3-33
Figure 3-33: FLVF1924 Package—XCKU085 I/O Bank Diagram
24 24
S
23
23
22 22
21 21
20
20
19
19
18
18
17
1716
16
15 15
14
14
S13
13
12 12S
11 11
10
10998
877
6
6
5
5
44
3
3
2
21
1
24 24
S23 23
22 22
21
21
20 20
19 19
18 18
17
17
16 16 15 15
14 14
S13
13
12
12
S
11 11
10
10
9
98
87
766
5
54
4
33
2
2
1
1
24
24S
23 23 22
22
21
21 20
20
19
1918
18
17 17
16 1615
15
14
14
S
13 13 12 12
S
11
11
10
10
99
88
77
6
6
5
54
4
3
3
22
11
24
24
S
23
23
22
22
21
21
20 20
19
19
18
1817
17
16
16
15
15
14 14
S13
13
12
12
S
11
11
10
10
9
9
887
766
55
4
4
33
2
2
1
1
24 24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14 14
S
13
13
12 12
S11 11
10
10
9
9
8
8
7
7
66
5
5
4
4
3
3
2
2
11
24 24
S
23
23
22
22
21
21 20
20
19
19
18
18
17
17
16
16
15
15
14 14
S13
13
12 12
S11 11
10
10
9
98
8
7
7
66
5544
3
3
2
2
S
11
24
24
S
23
23
22
22
2121
2020
1919
1818 1717
1616
15
15
14
14 S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
66
5
5
44
33
2
2
1
1
2424
S
23
23
22
22
21
21
2020
19
19
18
18
17
17
16
16
15
151414
S
13
13
1212 S
1111
10109
988
77
66
5
5
4
4
33
2
2
1
1
2424
S
23
23
2222
21
21
2020
1919
18
18
17
17
16
16
15
15
1414
S
13
13
1212
S
1111
10
10
9
9
8
8
77
66
5
5
4
43
322
1
1
2424
S
23
23
2222
2121
2020
1919
18
18
1717
16
16 1515
1414
S13
13
12
12
S
111110
10 99
8877
6
6
55
4
4
3
3
22S
11
24
24
S
23
23
22
22
212120
20
19
19
1818
171716
16 15
151414
S
131312
12
S
11
11
1010
9
9
8
87
7
66
5
5
44
33
2
2
1
1
24 24
S
23
23
22
22
21
21
20 20
19
19
18 18
17 17
16
16
15
15
14 14 S
13 13
12 12
S11
11
10
10
9
988
77
6
65
5
4
43
3
2
21
1
3
3
3
126
3
126
1
1
126
2
2
2
126
2
126
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
0
0
0
127
0
127
33
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
00
0
128
0
128
3
3
3
131
3
131
1
1
131
22
2
131
2
131
1
1
1
131
1
131
0
0
131
0
0
0
131
0
131
3
3
3
132
3
132
1
1
132
2
2
2
132
2
132
1
1
1
132
1
132
0
0
132
0
0
0
132
0
132
G
V
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
GG
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
Bank 44
Bank 45
Bank 46
Bank 51
Bank 52
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Quad 126
Quad 127
Quad 128
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_33_100715
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-34
Figure 3-34: FLVF1924 Package—XCKU085 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
200
17
19
30 28
35
33
34
29
29
29
29 29
29
29
29
29
29
29
29
26
26
26
26
26 26
27 26
26
26 26
3526 26
26
26
26
2625
25
25
25
25 25
25 2525 25
25
25
31
32
25
36 37
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E E
E
E E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E E
E E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V
V
V
V
V
V
V
V
V
n
n
n
n
n
n n
n
n
n n
n n
n
n n
n
n
n
n
n
n
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n
n n n
n
n n
n
n
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n n
n n n
n
n n
n
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n
n n
n
nn
n
n
nnn
n
n
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n
nn
n
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n
nn
n n
nnnn
nn
n
n
n nn
nn
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n n
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nnn
nn
n
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n n
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n n
n
n n
n
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n n
n
n n
n
n n
n
nnn n
nn
n
nn
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nn
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n
1
1
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVF1924 (XCKU115) and RLF1924 (XQKU115)
X-Ref Target - Figure 3-35
Figure 3-35: FLVF1924 Package—XCKU115 and RLF1924 Package—XQKU115 I/O Bank Diagram
24 24
S
23
23
22 22
21 21
20
20
19
19
18
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17
1716
16
15 15
14
14
S13
13
12 12S
11 11
10
10998
877
6
6
5
5
44
3
3
2
21
1
24 24
S23 23
22 22
21
21
20 20
19 19
18 18
17
17
16 16 15 15
14 14
S13
13
12
12
S
11 11
10
10
9
98
87
766
5
54
4
33
2
2
1
1
24
24S
23 23 22
22
21
21 20
20
19
1918
18
17 17
16 1615
15
14
14
S
13 13 12 12
S
11
11
10
10
99
88
77
6
6
5
54
4
3
3
22
11
24
24
S
23
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20 20
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1817
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14 14
S13
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12
12
S
11
11
10
10
9
9
887
766
55
4
4
33
2
2
1
1
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S
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22 22
21
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14 14
S
13
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12 12
S11 11
10
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9
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8
7
7
66
5
5
4
4
3
3
2
2
11
24
24
S
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23
22 22
21
21
20 20
19 19
18
18 17
17
16
16
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15
14
14
S
13
13
12
12
S
11 11 10
10
99
8
8
7
7
66
554
4
33
2
2
11
24 24
S
23
23
22
22
21
21 20
20
19
19
18
18
17
17
16
16
15
15
14 14
S13
13
12 12
S11 11
10
10
9
98
8
7
7
66
5544
3
3
2
2
S
11
24
24
S
23
23
22
22
2121
2020
1919
1818 1717
1616
15
15
14
14 S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
66
5
5
44
33
2
2
1
1
2424
S
23
23
22
22
21
21
2020
19
19
18
18
17
17
16
16
15
151414
S
13
13
1212 S
1111
10109
988
77
66
5
5
4
4
33
2
2
1
1
2424
S
23
23
2222
21
21
2020
1919
18
18
17
17
16
16
15
15
1414
S
13
13
1212
S
1111
10
10
9
9
8
8
77
66
5
5
4
43
322
1
1
2424
S
23
23
2222
2121
2020
1919
18
18
1717
16
16 1515
1414
S13
13
12
12
S
111110
10 99
8877
6
6
55
4
4
3
3
22S
11
24
24
S
23
23
22
22
212120
20
19
19
1818
171716
16 15
151414
S
131312
12
S
11
11
1010
9
9
8
87
7
66
5
5
44
33
2
2
1
1
24 24
S
23
23
22
22
21
21
20 20
19
19
18 18
17 17
16
16
15
15
14 14 S
13 13
12 12
S11
11
10
10
9
988
77
6
65
5
4
43
3
2
21
1
2424
S
23
232222
21
21
20
20
1919
18
18
17
1716
16 15
151414S
1313
12
12
S1111
1010
9
9
8
8
7
7
6
6
5
54
4
3
3
22
11
3
3
3
126
3
126
1
1
126
2
2
2
126
2
126
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
0
0
0
127
0
127
33
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
00
0
128
0
128
3
3
3
131
3
131
1
1
131
22
2
131
2
131
1
1
1
131
1
131
0
0
131
0
0
0
131
0
131
3
3
3
132
3
132
1
1
132
2
2
2
132
2
132
1
1
1
132
1
132
0
0
132
0
0
0
132
0
132
3
3
3
133
3
133
1
1
133
2
2
2
133
2
133
G
V
1
1
1
133
1
133
0
0
133
0
0
0
133
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
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17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
GG
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 51
Bank 52
Bank 53
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 73
Quad 126
Quad 127
Quad 128
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-36
Figure 3-36: FLVF1924 Package—XCKU115 and RLF1924 Package—XQKU115
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
200
17
19
30 28
35
33
34
29
29
29
29 29
29
29
29
29
29
29
29
26
26
26
26
26 26
27 26
26
26 26
3526 26
26
26
26
2625
25
25
25
25 25
25 2525 25
25
25
31
32
25
36 37
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E E
E
E E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E E
E E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
GG
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_36_100715
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Chapter 3: Device Diagrams
FLVA2104 (XCKU115)
X-Ref Target - Figure 3-37
Figure 3-37: FLVA2104 Package—XCKU115 I/O Bank Diagram
24 24
S
23
23
22 22
21 21
20
20
19
19
18
18
17
1716
16
15 15
14
14
S13
13
12 12S
11 11
10
10998
877
6
6
5
5
44
3
3
2
21
1
24
24
S
23 23
22
22
21 21
20
20
19 1918
18
17 17
16 16
15
15
14
14S
13 13
12
12
S11 11
10
10 9
988
7
7
665
54
4
3
3
22
1
1
24 24
S23 23
22 22
21
21
20 20
19 19
18 18
17
17
16 16 15 15
14 14
S13
13
12
12
S
11 11
10
10
9
98
87
766
5
54
4
33
2
2
1
1
24 24
S
23
23
22
2221 21
20 2019
1918 18
17 17
16 1615
15
14
14
S
13
13 12 12
S11
11
10
10
9
988
77
6
6
55
44
3
3
22
1
1
24
24
S
23
23
22
22
21
21
20 20
19
19
18
1817
17
16
16
15
15
14 14
S13
13
12
12
S
11
11
10
10
9
9
88
7766
55
4
4
3
3
2
2
1
1
24 24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16 16
15
15
14 14
S
13
13
12 12
S
11 11
10
10
9
9
8
8
7
7
66
5
5
4
43
3
22
11
24
24
S
23
23
22 22
21
21
20 20
19 19
18
18 17
17
16
16
15
15
14
14
S
13
13
12
12
S
11 11 10
10
99
8
8
7
7
66
554
4
33
2
2
11
24
24
S
23 23
22
22
21
21 20
20
19
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12S
11
11
10 10 9
9
8
8
77
6
6
5
5
4
4
3
3
2
2
1
1
2424
S
2323
2222
21
21
2020
1919
181817
17
1616
15
15
1414
S
1313
12
12S11
1110
10 9
9
8
8
7
7
66
5
5
443
322S
1
1
2424S
23
23
2222
21
21
20
201919
1818
1717
1616
15
15 1414
S
13
13
1212
S
11
11
1010
9988
77
6
6
5
5
4
4
3
3
22
1
1
2424
S2323
2222
21
21
20
2019
19
18
18
17
1716
16
1515
14
14 S13
13
1212
S
1111
1010
9
9
8
8
77
6
6
5
5
4
43
3
2
2
1
1
24
24 S
2323
22
22
21
21
2020
1919
18
18
17
17
16
16 15
15
14
14
S1313
12
12
S
11
11
10
10 99
8
8
7
7
6
6
5
5
4
4
3
3
2
2
S
1
1
2424
S
2323
2222 2121
20
20
19
19
1818
17
1716
16
15
15
14
14
S
13
13
12
12S
11
11
1010
99
8
877
6
6
5
5
44
332
2
11
24
24
S
2323
22
22 2121
2020
19
19
181817
17
16
16
1515
1414S
1313
12
12S
11
11
10
10
9
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24
24
S
2323
2222
2121
20
20
1919
18
18
17
1716
16 1515
1414
S1313
1212
S
11
11
10
10
9
9
8
87
7
6
6
55
44
33
2
2
11
24
24
S23
23 2222
21
21
2020
1919
18
18
1717
16
16
15
15
14
14
S13
13
1212
S
111110
10
9
9
88
77
6
6
55
4
4
3
3
2
2
S
1
1
3
3
3
126
3
126
1
1
126
2
2
2
126
2
126
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
0
0
0
127
0
127
3
3
3
128
3
128
1
1
128
2
2
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3
131
3
131
1
1
131
2
2
2
131
2
131
1
1
1
131
1
131
0
0
131
00
0
131
0
131
3
3
3
132
3
132
1
1
132
2
2
2
132
2
132
1
1
1
132
1
132
0
0
132
0
0
0
132
0
132
3
3
3
133
3
133
1
1
133
2
2
2
133
2
133
G
V
1
1
1
133
1
133
0
0
133
0
0
0
133
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 50
Bank 51
Bank 52
Bank 53
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 126
Quad 127
Quad 128
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 231
Quad 232
Quad 233
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-38
Figure 3-38: FLVA2104 Package—XCKU115 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
200
17
19
3028
35
3334
2929
29
29
2929
2929
292929
29
2626
26
26
2626
27
2626
26
2635 26
2626
26 26
26
25
25
25
25
2525
25
25
2525 25
253132 25
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVB2104 (XCKU095)
X-Ref Target - Figure 3-39
Figure 3-39: FFVB2104 Package—XCKU095 I/O Bank Diagram
24 24
S
23
23
22 22
21
21 20
20
19
19
18 18
17 1716
16
15
1514
14
S
13 13
12 12
S
11
11 10
10
9
988
776
65
5
44
3
3
22
11
24
24
S23
23
22 22 21
2120
20
19 19
18
18
17
17 16 16
15
15
14 14
S
13
13
12
12
S
11
11
10
10
9
9
8
8
7
7
6
65
54
43
3
2
211
24 24
S
23 23
22
22
21
21
20
20
19 19
18
18
17 1716
16
15
15
14
14
S
13 13
12 12
S
11 11
10 10
9
9
8
8
7
76
6
55
44
332
2
1
1
24
24S
23
23
22
2221
21
20
2019
19
18
1817
17
16
16
15
15 14
14 S
13 13
12 12
S11
11
10
10
9
9
887
7
6
6
5
5
44
3
32
2
1
1
24
24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16 16
15 15
14
14
S
13 13 12 12
S
11
11
10
10
9
9
8
8
7
7
66
5
5
4
4
33
2
2
11
24
24
S
23
2322 22
21
2120
2019
19
18
18
17
17
16 16
15
1514 14
S
13
13
12 12
S
11 11
10 10
9
98
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
24 24
S
23
23
22
22
21
21
20
2019 19
18
18
17
17
16
16
15 15
14 14
S
13
13 12
12
S
11 11
10
10
99
88
7
7
66
5
5
4
4
3
32
211
24
24
S
23
23
22
2221
21 20
20
1919
18
18
17
1716
16 15
15
14
14 S
13
13
12
12
S11
11
10
109
98
8
7
7
6
6
5
54
43
3
22
1
1
24
24
S
23
23
22
22
2121
2020
1919
18
18
17
1716
16
15
15
1414
S
1313
12
12
S
1111
1010
9988
7
7
66
554
4
3
32
211
1212
S
11
11
10
10
99
88
77
66
5
5
44
33
2
2
1
1
24
24
S23
2322
222121
20
20
19
19
18
18
17
17
1616
15
15
14
14
S
13
13
1212
S
11
11 1010
9
9
88
7
7
6
65
5
4
4
3
32
2
1
1
24
24S
23
23
22
22 21
21
202019
19
1818
17171616
1515
1414 S
1313
1212
S11
11 10
10
9
9
887
7
6
6
5
54
4
33
2
21
1
24
24
S
23
232222
21
21
202019
19
18
181717
1616
15
15 1414 S
1313
12
12S
11
11
10
10
9
9
8
8
77
6
6
55
4
4
3
32
2
1
1
24
24
S
23
23
22
22
21
21
20
20
1919
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11 10
109
9
8
8
7
7
6
6
5
54
4
3
32
2
S11
3
124
3
3
3
124
1
124
1
2
124
2
2
2
124
1
124
1
1
1
124
0
124
0
0
124
0
0
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
0
0
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
V
G
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 44
Bank 45
Bank 46
Bank 49
Bank 50
Bank 51
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 84
Bank 94
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_39_100715
{I XILINX¢ ll IIIIIIIIIIIIIIIIDIIDI DDDDDDDDDD DDDDI REESE I DDDDDDDDDDDDD DDDDDDDDDDDDDDD )5 Send Feed back
UltraScale Device Packaging and Pinouts 222
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 3: Device Diagrams
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
200
17
30 28
35
33
34
29
29
29
29
29
2929 29
29
29
29
29
26
26
26 26
26 26
27
26
26 26
26
35
26 26
26
26
26 26
25 25
25
25
25 25
25
25
25
25
25
2531
32
25
36 37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
n n
nn
n n
nn
nn
n n
nn
n n
nn
nn
n n
nnn n nn
nnn n
nnn n nn
nnn n
nnn n
nn
nnn n
nnn n nn
nnn n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_40_100715
X-Ref Target - Figure 3-40
Figure 3-40: FFVB2104 Package—XCKU095 Configuration/Power Diagram
(I XILINX¢ 3: u a» 3mm HEM: 690099 ®DD OOOOOB Send Feed back
UltraScale Device Packaging and Pinouts 223
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 3: Device Diagrams
FLVB2104 (XCKU115)
X-Ref Target - Figure 3-41
Figure 3-41: FLVB2104 Package—XCKU115 I/O Bank Diagram
24 24
S
23
23
22 22
21
21 20
20
19
19
18 18
17 1716
16
15
1514
14
S
13 13
12 12
S
11
11 10
10
9
988
776
65
5
44
3
3
22
11
24
24
S23
23
22 22 21
2120
20
19 19
18
18
17
17 16 16
15
15
14 14
S
13
13
12
12
S
11
11
10
10
9
9
8
8
7
7
6
65
54
43
3
2
211
24 24
S
23 23
22
22
21
21
20
20
19 19
18
18
17 1716
16
15
15
14
14
S
13 13
12 12
S
11 11
10 10
9
9
8
8
7
76
6
55
44
332
2
1
1
24
24S
23
23
22
2221
21
20
2019
19
18
1817
17
16
16
15
15 14
14 S
13 13
12 12
S11
11
10
10
9
9
887
7
6
6
5
5
44
3
32
2
1
1
24
24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16 16
15 15
14
14
S
13 13 12 12
S
11
11
10
10
9
9
8
8
7
7
66
5
5
4
4
33
2
2
11
24
24
S
23
2322 22
21
2120
2019
19
18
18
17
17
16 16
15
1514 14
S
13
13
12 12
S
11 11
10 10
9
98
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
24 24
S
23
23
22
22
21
21
20
2019 19
18
18
17
17
16
16
15 15
14 14
S
13
13 12
12
S
11 11
10
10
99
88
7
7
66
5
5
4
4
3
32
2
S
11
24
24
S
23
23
22
2221
21 20
20
1919
18
18
17
1716
16 15
15
14
14 S
13
13
12
12
S11
11
10
109
98
8
7
7
6
6
5
54
43
3
22
1
1
24
24
S
23
23
22
22
2121
2020
1919
18
18
17
1716
16
15
15
1414
S
1313
12
12
S
1111
1010
9988
7
7
66
554
4
3
32
211
1212
S
11
11
10
10
99
88
77
66
5
5
44
33
2
2
1
1
24
24
S23
2322
222121
20
20
19
19
18
18
17
17
1616
15
15
14
14
S
13
13
1212
S
11
11 1010
9
9
88
7
7
6
65
5
4
4
3
32
2
1
1
24
24S
23
23
22
22 21
21
202019
19
1818
17171616
1515
1414 S
1313
1212
S11
11 10
10
9
9
887
7
6
6
5
54
4
33
2
21
1
24
24
S
23
232222
21
21
202019
19
18
181717
1616
15
15 1414 S
1313
12
12S
11
11
10
10
9
9
8
8
77
6
6
55
4
4
3
32
2
1
1
24
24
S
23
23
22
22
21
21
20
20
1919
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11 10
109
9
8
8
7
7
6
6
5
54
4
3
32
2
S11
3
3
3
126
3
126
1
1
126
2
2
2
126
2
126
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
33
3
127
3
127
1
1
127
22
2
127
2
127
11
1
127
1
127
0
0
127
00
0
127
0
127
33
3
128
3
128
1
1
128
22
2
128
2
128
G
V
11
1
128
1
128
0
0
128
00
0
128
0
128
33
3
131
3
131
1
1
131
22
2
131
2
131
11
1
131
1
131
0
0
131
00
0
131
0
131
33
3
132
3
132
1
1
132
22
2
132
2
132
11
1
132
1
132
0
0
132
00
0
132
0
132
3
3
3
133
3
133
1
1
133
22
2
133
2
133
G
V
11
1
133
1
133
0
0
133
00
0
133
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 44
Bank 45
Bank 46
Bank 51
Bank 52
Bank 53
Bank 65
Bank 66
Bank 67
Bank 68
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 126
Quad 127
Quad 128
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_41_100715
{I XILINX¢ ID DIDDDDEDDDDIDDDD DDDBDDDBIDDDDBDD EDDDDIDDDDEDDDDI D IDMDDEDEDDIDMD DDDDDDDDDDDDD DDDDDDDDDD DDDDDDDDDDDDDDD I DEEBEDIDDDD Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-42
Figure 3-42: FLVB2104 Package—XCKU115 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14 18
16
4
2
5
3
200
17
19
30 28
35
33
34
29
29
29
29
29
2929 29
29
29
29
29
26
26
26 26
26 26
27
26
26 26
26
35
26 26
26
26
26 26
25 25
25
25
25 25
25
25
25
25
25
2531
32
25
36 37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
nn n n
nn
nn n n
nn n n
nn
nn n n
nn n n
nn
nn n n
nn n n
nn
nn n n
nn
n n
nn
nn
n n
nn
n n
nn
nn
n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_42_100715
(I XILINX¢ mammamaumumaamamaamm ammugizf 690069 ®DD {x OOOOOS w m m m.m»m»mmmmmm mmmmummmmm m m mama «uwmmmmmmmsmmmmsmmm Send Feed back
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Chapter 3: Device Diagrams
FFVC1517 (XCVU065)
X-Ref Target - Figure 3-43
Figure 3-43: FFVC1517 Package—XCVU065 I/O Bank Diagram
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 65
Bank 66
Bank 67
Bank 68
Bank 84
Bank 94
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
ug575_c3_43_100815
24
24
S
23 23
22
22
21
21
20 20
19
19
18
1817
17
16
1615 15
14
14 S
13 13
12
12
S11
11
10
10
99
88
77
665
5
44
3
3
22
11
24
24
S
23
23
22 22
21
21
20 20
19 19
18 18
17
17
16 16
15
15
14 14
S
13 13
12 12
S
11 11
10
10 99
8
8
77
66
5
5
4
4
3
322
11
2424
S
23
23
22
22
21
212020
1919
1818
17
17
1616
1515
1414
S
1313
1212
S
1111
10
10
9
98
8
7
7
6
6
5
54
4
33
2
2
1
12424
S23
2322
22
21
2120
20
19
19
18
1817
17
16
16 15
15
14
14
S
13
13
1212
S
11
11 10
10
99
88
7
7
66
55
4
4
33
2
2
11
24
24
S
23
23
22
22
21
21
202019
19
18
181717
16
16
1515
1414
S
1313
12
12 S
11
11
1010
9
9
8
8
7
7
6
6
55
44
3
3
22
1
1
24 24 S
23
23
22
22
21
21
20 20
19
19
18
18
17 17
16 1615
15 14
14 S
13
13
12 12 S
11 1110
10
99
88
7
76
6
5
5
4
4
3
3
22
112424
S
2323
222221
21
20
2019
19
1818
17
17
16
16
1515
1414
S
13
13
12
12
S
11
11
10
10 9
9
88
7
7
6
6
5
5
4
43
3
22
11
2424
S
23
23
22
22
21
21
2020
19
19
18
18
17
17
16
16
15
15
1414
S13
13
12
12
S
11
11
10
109
9
8
8
77
6
6
55
44
33
2
21
1
24
24
S2323
22
22
21
21
20
20
19
19
1818
17
17
1616
15
15
1414S
1313
1212 S
1111
10
10
9
98
8
77
6
6
5
5
4
43
32
2
1
1
24 24
S23
23
22 22
21
2120 20
19 19
18 1817
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
88
7
7
6
655
443
322
S
1
1
3
124
3
3
3
124
1
124
1
2
124
2
2
2
124
1
124
11
1
124
0
124
0
0
124
0
0
0
124
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
V
G
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
128
3
3
3
128
1
128
1
2
128
22
2
128
1
128
1
1
1
128
0
128
0
0
128
0
0
0
128
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
(I XILINX¢ l DDEDDDEIDD DDDIDDDUB D DID EDD u l DDDDDDDDDDDDD DDDDDDDDDD DDDDDDDDDDDDDDD EEEBEE DUDE Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-44
Figure 3-44: FFVC1517 Package—XCVU065 Configuration/Power Diagram
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_44_100815
8 7
23
24 21
22
1011
9
12
1
15
13
6
14
19
18
16
4
2
5
320
0
17
30 28 35
33
34
29
29
29
29
29 29
29
29
29
29
29 29
26 2626
26 26
26 27
26
26
26 26 35
26 2626
26
26 26
25 25
25
25 25
25
25
25
25
25
25
25
31 32
25
36 37
E
E
E
E E
E
E
E
E
E
E
E
E E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
(I XILINX¢ mammammmamuaumumam "mmugizmmm .. 690060 ®DD an ”N” m m mwmwmmmsmm mmmmumsmsm m m mum! ”mwmmsusmmsmssmsm ____ OOOOOG Send Feed back
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Chapter 3: Device Diagrams
FFVC1517 (XCVU080 and XCVU095)
X-Ref Target - Figure 3-45
Figure 3-45: FFVC1517 Package—XCVU080 and XCVU095 I/O Bank Diagram
ug575_c3_45_100815
24
24
S
23 23
22
22
21
21
20 20
19
19
18
1817
17
16
1615 15
14
14 S
13 13
12
12
S11
11
10
10
99
88
77
665
5
44
3
3
22
11
24
24
S
23
23
22 22
21
21
20 20
19 19
18 18
17
17
16 16
15
15
14 14
S
13 13
12 12
S
11 11
10
10 99
8
8
77
66
5
5
4
4
3
322
11
2424
S
23
23
22
22
21
212020
1919
1818
17
17
1616
1515
1414
S
1313
1212
S
1111
10
10
9
98
8
7
7
6
6
5
54
4
33
2
2
1
12424
S23
2322
22
21
2120
20
19
19
18
1817
17
16
16 15
15
14
14
S
13
13
1212
S
11
11 10
10
99
88
7
7
66
55
4
4
33
2
2
11
24
24
S
23
23
22
22
21
21
202019
19
18
181717
16
16
1515
1414
S
1313
12
12 S
11
11
1010
9
9
8
8
7
7
6
6
55
44
3
3
22
1
1
24 24 S
23
23
22
22
21
21
20 20
19
19
18
18
17 17
16 1615
15 14
14 S
13
13
12 12 S
11 1110
10
99
88
7
76
6
5
5
4
4
3
3
22
112424
S
2323
222221
21
20
2019
19
1818
17
17
16
16
1515
1414
S
13
13
12
12
S
11
11
10
10 9
9
88
7
7
6
6
5
5
4
43
3
22
11
2424
S
23
23
22
22
21
21
2020
19
19
18
18
17
17
16
16
15
15
1414
S13
13
12
12
S
11
11
10
109
9
8
8
77
6
6
55
44
33
2
21
1
24
24
S2323
22
22
21
21
20
20
19
19
1818
17
17
1616
15
15
1414S
1313
1212 S
1111
10
10
9
98
8
77
6
6
5
5
4
43
32
2
1
1
24 24
S23
23
22 22
21
2120 20
19 19
18 1817
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
88
7
7
6
655
443
322
S
1
1
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
1
125
11
1
125
0
125
0
0
125
0
0
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
128
3
3
3
128
1
128
1
2
128
2
2
2
128
1
128
1
1
1
128
0
128
0
0
128
0
0
0
128
3
129
3
3
3
129
1
129
1
2
129
22
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 65
Bank 66
Bank 67
Bank 68
Bank 84
Bank 94
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-46
Figure 3-46: FFVC1517 Package—XCVU080 and XCVU095 Configuration/Power Diagram
ug575_c3_46_100815
8 7
23
24 21
22
1011
9
12
1
15
13
6
14
19
18
16
4
2
5
320
0
17
30 28 35
33
34
29
29
29
29
29 29
29
29
29
29
29 29
26 2626
26 26
26 27
26
26
26 26 35
26 2626
26
26 26
25 25
25
25 25
25
25
25
25
25
25
25
31 32
25
36 37
E
E
E
E E
E
E
E
E
E
E
E
E E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVD1517 (XCVU080 and XCVU095)
X-Ref Target - Figure 3-47
Figure 3-47: FFVD1517 Package—XCVU080 and XCVU095 I/O Bank Diagram
24
24
S
23
23
22
2221
21
2020
1919
18
1817
17
16
16
1515
1414
S
1313
1212
S
11
11
1010 9
9
88
7
7
665
54
43
3
2
21
1
24 24 S23
23 22 22
21 21
20 20
19
19
18
18
17
17
16 16
15 15
14 14
S
13
13
12
12S11
11
10
1099
8877
66
5
5
4
4
33
22
11
12
12
S
11 11
10 10
99
887
76
6
55
443
3
22
1
1
24 24 S
23 2322 2221 21
20 20
19 19
18
18
17 17
16 16
15 15 14 14
S13 13
12 12
S
11 11
10 10
998
8
77
6
655
44
33
22
11
24
24
S
23
2322
22
21
21
20 20
19 19
18
18
17
17
16 16
15
15
14
14
S
13
13
12 12
S
11
11
10 10
9
9
88
7
7
6
65
544
33
2
2
1
1
24
24
S
23
23
22
22
2121
20
20
19
19
18
18
17
17
16
16
15
15
1414
S
1313
12
12
S
1111
1010
9
9
88
7
7
6
655
44
3
3
221
1
24
24
S
2323
22
22
2121
20
20
1919
1818
171716
16 151514
14S1313
12
12
S
11
11
1010
9
98
877
665
54
4
3
3
22
S
1
1
3
124
3
3
3
124
1
124
1
2
124
2
2
2
124
1
124
1
1
1
124
0
124
0
0
124
0
0
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
128
3
3
3
128
1
128
1
2
128
2
2
2
128
1
128
1
1
1
128
0
128
0
0
128
0
0
0
128
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
1
131
1
1
1
131
0
131
0
0
131
0
0
0
131
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Bank 65
Bank 66
Bank 67
Bank 69
Bank 70
Bank 71
Bank 84
Bank 94
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_47_100815
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-48
Figure 3-48: FFVD1517 Package—XCVU080 and XCVU095 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
1816
4
2
5
3
20 0
17
30
28
35
33
34
29
2929
29
2929
2929
29
2929
29
26
26
2626
2626
27
2626
2626
35
26
26
2626 26
26
2525
25
25
2525 25
2525
25 25
25
31
32
25
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E E
E
E E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E E
E
E E
E
E E
E
V V
V
V V
V
V V
V V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V
V V
V
V V
V
V V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
nnn n
nn
nnn n
nnn n
nn
nnn n
n
nn
n
nn
n
nn
n
n
nn
n
nn
n
nn
n
n n
n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_48_100815
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Chapter 3: Device Diagrams
FLVD1517 (XCVU125)
X-Ref Target - Figure 3-49
Figure 3-49: FLVD1517 Package—XCVU125 I/O Bank Diagram
24
24
S
23
23
22
2221
21
2020
1919
18
1817
17
16
16
1515
1414
S
1313
1212
S
11
11
1010 9
9
88
7
7
665
54
43
3
2
21
1
24 24 S23
23 22 22
21 21
20 20
19
19
18
18
17
17
16 16
15 15
14 14
S
13
13
12
12S11
11
10
1099
8877
66
5
5
4
4
33
22
11
12
12
S
11 11
10 10
99
887
76
6
55
443
3
22
1
1
24 24 S
23 2322 2221 21
20 20
19 19
18
18
17 17
16 16
15 15 14 14
S13 13
12 12
S
11 11
10 10
998
8
77
6
655
44
33
22
11
24
24
S
23
2322
22
21
21
20 20
19 19
18
18
17
17
16 16
15
15
14
14
S
13
13
12 12
S
11
11
10 10
9
9
88
7
7
6
65
544
33
2
2
1
1
24
24
S
23
23
22
22
2121
20
20
19
19
18
18
17
17
16
16
15
15
1414
S
1313
12
12
S
1111
1010
9
9
88
7
7
6
655
44
3
3
221
1
24
24
S
2323
22
22
2121
20
20
1919
1818
171716
16 151514
14S1313
12
12
S
11
11
1010
9
98
877
665
54
4
3
3
22
S
1
1
3
124
3
3
3
124
1
124
1
2
124
2
2
2
124
1
124
1
1
1
124
0
124
0
0
124
0
0
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
V
G
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
130
3
3
3
130
1
130
1
2
130
2
2
2
130
V
G
1
130
1
1
1
130
0
130
0
0
130
0
0
0
130
3
131
33
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
2
2
2
132
1
132
1
1
1
132
0
132
0
0
132
0
0
0
132
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Bank 65
Bank 66
Bank 67
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 124
Quad 125
Quad 126
Quad 127
Quad 129
Quad 130
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_49_100815
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-50
Figure 3-50: FLVD1517 Package—XCVU125 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
1816
4
2
5
3
20 0
17
19
30
28
35
33
34
29
2929
29
2929
2929
29
2929
29
26
26
2626
2626
27
2626
2626
35
26
26
2626 26
26
2525
25
25
2525 25
2525
25 25
25
31
32
25
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E E
E
E E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E E
E
E E
E
E E
E
V V
V
V V
V
V V
V V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V
V V
V
V V
V
V V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_50_100815
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Chapter 3: Device Diagrams
FFVB1760 (XCVU080 and XCVU095)
X-Ref Target - Figure 3-51
Figure 3-51: FFVB1760 Package—XCVU080 and XCVU095 I/O Bank Diagram
24 24 S
23
2322
22 21 21
20 20
19 19
18
18
17
17
16
16
15
15
14 14 S
13 13
12 12
S
11 11
10
10
998
877
66
5
5
44
3
3
22
11
24
24
S
23 23
22
22
21
21
20 20
19 19
18 18
17
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
8
87
7
66
55
4
4
33
22
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
1817 17
16 16
15 15 14 14
S13 13
12 12S
11 1110
10 99
88
7
7
66
5
5
4
43
32
2
1
1
24
24
S
23 23
22
22
21
21
20 20
19 19 18
18
17
17
16 16
15 15
14 14
S
13 13
12 12
S
11
11 10 10
9
9
8
87
7
66
55
443
322
11
24
24
S
23 23
22 22
21
21
20
20
19
19
18 18
17 17
16
1615
15
14 14
S
13
13
12
12
S
11
11
10 10
9
9
8
8
7
7
66
55
44
3
3
2
2
1
1
2424
S
2323
2222
2121
20
20 19
19
1818
1717
1616 15
15
1414
S
13
13
12
12
S
1111
10
10
9
9
8
8
7
7
66
55
4
4
3
3
2
2
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10 10
99
8
8
7
7
6
6
5
5
44
3
3
2
21
112
12
S
11
11
10
10
9
9
8
8
7
766
5
5
4
4
33
2
2
1
1
24
24
S
23
23
22 22
21
21
20 20 19
19
18 18
17 17
16
16
15
15
14 14
S
13
13
12
12
S
11 11
10 10
99
8
87
7
66
55
4
4
33
22
1
1
2424
S2323
2222
21
21
2020 1919
18
18
17
17
1616
15
15
14
14
S
1313
1212 S
1111 10
10
99
8
8
7
7
66
5
5
44
3
3
2
2
1
1
24
24
S
23 23
22
22
21
2120
20
19 19
18 18
17
17
16
16
15
15
14
14
S
13 13
12 12
S
11 11
10
10
9
9
88
7
7
66
5
5
4
4
3
322
11
2424
S
23
23
22
22 21
21
20
20
19
19
18
18
17
17
1616
15
15 1414
S
1313
1212
S
11
111010
9988
77
6
6
5
5
4
4
33
22
1
1
2424
S
2323
2222
21
21
20
20 1919
18
18 1717
1616
15
15
1414
S13
13
12
12
S
111110
10
9
9
8
8
7
7
66
5
5
4
433
2
2
1
1
2424
S2323
2222
21
21
2020
19
19
181817
17
16
16
1515
14
14
S
1313
1212
S
11
11
1010
9
9
8
877
6
6
5
544
33
2
2
S
1
1
3
128
3
3
3
128
1
128
1
2
128
2
2
2
128
1
128
1
1
1
128
0
128
0
0
128
0
0
0
128
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
130
3
3
3
130
1
130
1
2
130
22
2
130
1
130
1
1
1
130
0
130
0
0
130
0
0
0
130
3
131
3
3
3
131
1
131
1
2
131
22
2
131
1
131
1
1
1
131
0
131
0
0
131
0
0
0
131
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 49
Bank 50
Bank 51
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 84
Bank 94
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-52
Figure 3-52: FFVB1760 Package—XCVU080 and XCVU095 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
20
0
17
30
28
35
33
34
29 29
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29
29 29 29
29
29 29
29 29
26
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26
26 26
27
26
26
26
26
35
26 26
26 26
26 26
25
25 25
25
25 25
25 25
25
25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
n n
nnn n
nn
nnn n
nnn n
nn
nnn n
1
1
2
2
3
3
4
4
5
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6
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25
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36
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41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVB1760 (XCVU125)
X-Ref Target - Figure 3-53
Figure 3-53: FLVB1760 Package—XCVU125 I/O Bank Diagram
24 24 S
23
2322
22 21 21
20 20
19 19
18
18
17
17
16
16
15
15
14 14 S
13 13
12 12
S
11 11
10
10
998
877
66
5
5
44
3
3
22
11
24
24
S
23 23
22
22
21
21
20 20
19 19
18 18
17
17
16
16
15 15
14
14
S
13
13
12 12
S
11 11
10 10
9
9
8
87
7
66
55
4
4
33
22
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
1817 17
16 16
15 15 14 14
S13 13
12 12S
11 1110
10 99
88
7
7
66
5
5
4
43
32
2
1
1
24
24
S
23 23
22
22
21
21
20 20
19 19 18
18
17
17
16 16
15 15
14 14
S
13 13
12 12
S
11
11 10 10
9
9
8
87
7
66
55
443
322
11
24
24
S
23 23
22 22
21
21
20
20
19
19
18 18
17 17
16
1615
15
14 14
S
13
13
12
12
S
11
11
10 10
9
9
8
8
7
7
66
55
44
3
3
2
2
1
1
2424
S
23
23
22
22 21
21
20
20
19
19
18
18
17
17
1616
15
15 1414
S
1313
1212
S
11
111010
9988
77
6
6
5
5
4
4
33
22
1
1
2424
S
2323
2222
21
21
20
20 1919
18
18 1717
1616
15
15
1414
S13
13
12
12
S
111110
10
9
9
8
8
7
7
66
5
5
4
433
2
2
1
1
2424
S
2323
2222
2121
20
20 19
19
1818
1717
1616 15
15
1414
S
13
13
12
12
S
1111
10
10
9
9
8
8
7
7
66
55
4
4
3
3
2
2
1
1
24
24
S
23 23
22
22
21
21
20 2019
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10 10
99
8
8
7
7
6
6
5
5
44
3
3
2
21
112
12
S
11
11
10
10
9
9
8
8
7
766
5
5
4
4
33
2
2
1
1
24
24
S
23
23
22 22
21
21
20 20 19
19
18 18
17 17
16
16
15
15
14 14
S
13
13
12
12
S
11 11
10 10
99
8
87
7
66
55
4
4
33
22
1
1
2424
S2323
2222
21
21
2020 1919
18
18
17
17
1616
15
15
14
14
S
1313
1212 S
1111 10
10
99
8
8
7
7
66
5
5
44
3
3
2
2
1
1
24
24
S
23 23
22
22
21
2120
20
19 19
18 18
17
17
16
16
15
15
14
14
S
13 13
12 12
S
11 11
10
10
9
9
88
7
7
66
5
5
4
4
3
322
11
2424
S2323
2222
21
21
2020
19
19
181817
17
16
16
1515
14
14
S
1313
1212
S
11
11
1010
9
9
8
877
6
6
5
544
33
2
2
S
1
1
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
130
3
3
3
130
1
130
1
2
130
2
2
2
130
V
G
1
130
1
1
1
130
0
130
0
0
130
0
0
0
130
3
131
3
3
3
131
1
131
1
2
131
22
2
131
1
131
1
1
1
131
0
131
0
0
131
0
0
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
1
1
1
132
0
132
0
0
132
0
0
0
132
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 49
Bank 50
Bank 51
Bank 52
Bank 53
Bank 65
Bank 66
Bank 67
Bank 84
Bank 94
Quad 129
Quad 130
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 230
Quad 231
Quad 232
Quad 233
ug575_c3_53_100815
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-54
Figure 3-54: FLVB1760 Package—XCVU125 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
20
0
17
19
30
28
35
33
34
29 29
29
29
29 29 29
29
29 29
29 29
26
26
26
26
26 26
27
26
26
26
26
35
26 26
26 26
26 26
25
25 25
25
25 25
25 25
25
25
25 25
31 32
25 36
37
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E E
E
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_54_100815
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Chapter 3: Device Diagrams
FFVA2104 (XCVU080 and XCVU095)
X-Ref Target - Figure 3-55
Figure 3-55: FFVA2104 Package—XCVU080 and XCVU095 I/O Bank Diagram
24 24
S
23
23
22 22
21 21
20
20
19
19
18
18
17
1716
16
15 15
14
14
S13
13
12 12S
11 11
10
10998
877
6
6
5
5
44
3
3
2
21
1
24
24
S
23 23
22
22
21 21
20
20
19 1918
18
17 17
16 16
15
15
14
14S
13 13
12
12
S11 11
10
10 9
988
7
7
665
54
4
3
3
22
1
1
24 24
S23 23
22 22
21
21
20 20
19 19
18 18
17
17
16 16 15 15
14 14
S13
13
12
12
S
11 11
10
10
9
98
87
766
5
54
4
33
2
2
1
1
24 24
S
23
23
22
2221 21
20 2019
1918 18
17 17
16 1615
15
14
14
S
13
13 12 12
S11
11
10
10
9
988
77
6
6
55
44
3
3
22
1
1
24
24
S
23
23
22
22
21
21
20 20
19
19
18
1817
17
16
16
15
15
14 14
S13
13
12
12
S
11
11
10
10
9
9
88
7766
55
4
4
3
3
2
2
1
1
24 24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16 16
15
15
14 14
S
13
13
12 12
S
11 11
10
10
9
9
8
8
7
7
66
5
5
4
43
3
22
11
24
24
S
23
23
22 22
21
21
20 20
19 19
18
18 17
17
16
16
15
15
14
14
S
13
13
12
12
S
11 11 10
10
99
8
8
7
7
66
554
4
33
2
2
11
24
24
S
23 23
22
22
21
21 20
20
19
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12S
11
11
10 10 9
9
8
8
77
6
6
5
5
4
4
3
3
2
2
1
1
2424
S
2323
2222
21
21
2020
1919
181817
17
1616
15
15
1414
S
1313
12
12S11
1110
10 9
9
8
8
7
7
66
5
5
443
322
1
1
2424S
23
23
2222
21
21
20
201919
1818
1717
1616
15
15 1414
S
13
13
1212
S
11
11
1010
9988
77
6
6
5
5
4
4
3
3
22
1
1
2424
S2323
2222
21
21
20
2019
19
18
18
17
1716
16
1515
14
14 S13
13
1212
S
1111
1010
9
9
8
8
77
6
6
5
5
4
43
3
2
2
1
1
24
24 S
2323
22
22
21
21
2020
1919
18
18
17
17
16
16 15
15
14
14
S1313
12
12
S
11
11
10
10 99
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
2424
S
2323
2222 2121
20
20
19
19
1818
17
1716
16
15
15
14
14
S
13
13
12
12S
11
11
1010
99
8
877
6
6
5
5
44
332
2
11
24
24
S
2323
22
22 2121
2020
19
19
181817
17
16
16
1515
1414S
1313
12
12S
11
11
10
10
9
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24
24
S
2323
2222
2121
20
20
1919
18
18
17
1716
16 1515
1414
S1313
1212
S
11
11
10
10
9
9
8
87
7
6
6
55
44
33
2
2
11
24
24
S23
23 2222
21
21
2020
1919
18
18
1717
16
16
15
15
14
14
S13
13
1212
S
111110
10
9
9
88
77
6
6
55
4
4
3
3
2
2
S
1
1
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
128
3
3
3
128
1
128
1
2
128
2
2
2
128
1
128
1
1
1
128
0
128
0
0
128
00
0
128
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
0
0
0
129
3
130
3
3
3
130
1
130
1
2
130
2
2
2
130
1
130
1
1
1
130
0
130
0
0
130
0
0
0
130
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
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21
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22
22
23
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24
24
25
25
26
26
27
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28
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29
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31
31
32
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36
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37
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39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 49
Bank 50
Bank 51
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 84
Bank 94
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_55_100815
{I XILINX¢ a IUD E E D D D I l D D D u D l D D u I BID 3 jjuDDDDIDD u D 3 D D EDDDDIDDDDE DDIDDDDED M ED ID DDDDDDDDDDDDD DDDDDDDDDD DDDDDDDDDDDDDDD IEEEEEEEUIDDDD Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-56
Figure 3-56: FFVA2104 Package—XCVU080 and XCVU095 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19 18
16
4
2
5
3
200
17
3028
35
3334
2929
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2929
292929
29
2626
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2626
27
2626
26
2635 26
2626
26 26
26
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2525
25
25
2525 25
253132 25
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n n
n n
1
1
2
2
3
3
4
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38
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40
41
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42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_56_100815
(I XILINX. .a..... m...wu D 990069 ®DD u OOOOOG u w. M.» mmmmnmnmsmmm: m :.......... u . . .D. ......D Send Feed back
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Chapter 3: Device Diagrams
FLVA2104 (XCVU125)
X-Ref Target - Figure 3-57
Figure 3-57: FLVA2104 Package—XCVU125 I/O Bank Diagram
24 24
S
23
23
22 22
21 21
20
20
19
19
18
18
17
1716
16
15 15
14
14
S13
13
12 12S
11 11
10
10998
877
6
6
5
5
44
3
3
2
21
1
24
24
S
23 23
22
22
21 21
20
20
19 1918
18
17 17
16 16
15
15
14
14S
13 13
12
12
S11 11
10
10 9
988
7
7
665
54
4
3
3
22
1
1
24 24
S23 23
22 22
21
21
20 20
19 19
18 18
17
17
16 16 15 15
14 14
S13
13
12
12
S
11 11
10
10
9
98
87
766
5
54
4
33
2
2
1
1
24 24
S
23
23
22
2221 21
20 2019
1918 18
17 17
16 1615
15
14
14
S
13
13 12 12
S11
11
10
10
9
988
77
6
6
55
44
3
3
22
1
1
24
24
S
23
23
22
22
21
21
20 20
19
19
18
1817
17
16
16
15
15
14 14
S13
13
12
12
S
11
11
10
10
9
9
88
7766
55
4
4
3
3
2
2
1
1
24 24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16 16
15
15
14 14
S
13
13
12 12
S
11 11
10
10
9
9
8
8
7
7
66
5
5
4
43
3
22
11
24
24
S
23
23
22 22
21
21
20 20
19 19
18
18 17
17
16
16
15
15
14
14
S
13
13
12
12
S
11 11 10
10
99
8
8
7
7
66
554
4
33
2
2
11
24
24
S
23 23
22
22
21
21 20
20
19
19
18
18
17 17
16
16
15
15
14
14
S
13
13
12
12S
11
11
10 10 9
9
8
8
77
6
6
5
5
4
4
3
3
2
2
1
1
2424
S
2323
2222
21
21
2020
1919
181817
17
1616
15
15
1414
S
1313
12
12S11
1110
10 9
9
8
8
7
7
66
5
5
443
322
1
1
2424S
23
23
2222
21
21
20
201919
1818
1717
1616
15
15 1414
S
13
13
1212
S
11
11
1010
9988
77
6
6
5
5
4
4
3
3
22
1
1
2424
S2323
2222
21
21
20
2019
19
18
18
17
1716
16
1515
14
14 S13
13
1212
S
1111
1010
9
9
8
8
77
6
6
5
5
4
43
3
2
2
1
1
24
24 S
2323
22
22
21
21
2020
1919
18
18
17
17
16
16 15
15
14
14
S1313
12
12
S
11
11
10
10 99
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
2424
S
2323
2222 2121
20
20
19
19
1818
17
1716
16
15
15
14
14
S
13
13
12
12S
11
11
1010
99
8
877
6
6
5
5
44
332
2
11
24
24
S
2323
22
22 2121
2020
19
19
181817
17
16
16
1515
1414S
1313
12
12S
11
11
10
10
9
9
8
8
7
7
6
65
5
4
4
3
3
2
2
1
1
24
24
S
2323
2222
2121
20
20
1919
18
18
17
1716
16 1515
1414
S1313
1212
S
11
11
10
10
9
9
8
87
7
6
6
55
44
33
2
2
11
24
24
S23
23 2222
21
21
2020
1919
18
18
1717
16
16
15
15
14
14
S13
13
1212
S
111110
10
9
9
88
77
6
6
55
4
4
3
3
2
2
S
1
1
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
V
G
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
130
3
3
3
130
1
130
1
2
130
2
2
2
130
V
G
1
130
1
1
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
1
131
1
1
1
131
0
131
0
0
131
0
0
0
131
3
132
3
3
3
132
1
132
1
2
132
2
2
2
132
1
132
1
1
1
132
0
132
0
0
132
0
0
0
132
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
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37
37
38
38
39
39
40
40
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42
42
43
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45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 44
Bank 45
Bank 46
Bank 47
Bank 50
Bank 51
Bank 52
Bank 53
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 125
Quad 126
Quad 127
Quad 130
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_57_100815
{I XILINX¢ Send Feed back I DDDDDDDDDDDDD I l I I I I I I I I m. DDDDDDDDDD EDEDDDDI D D I DDDIJJJJEDDDDIDD IDDDDEDDDDIDDDDE I DEDDDDIDDDDEDDD I B B I I B I I E B I ID I I I I I I I I I DDDDDDDDDDDDDDD I I E I EEEEEE
UltraScale Device Packaging and Pinouts 240
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-58
Figure 3-58: FLVA2104 Package—XCVU125 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
200
17
19
3028
35
3334
2929
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2929
292929
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2626
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26
2626
27
2626
26
2635 26
2626
26 26
26
25
25
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25
2525
25
25
2525 25
253132 25
36
37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
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5
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43
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45
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46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_58_100815
(I XILINX¢ DD F F — — — - - OOOOOO DD® 009000 Send Feedback
UltraScale Device Packaging and Pinouts 241
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Chapter 3: Device Diagrams
FFVB2104 (XCVU080 and XCVU095)
X-Ref Target - Figure 3-59
Figure 3-59: FFVB2104 Package—XCVU080 and XCVU095 I/O Bank Diagram
24 24
S
23
23
22 22
21
21 20
20
19
19
18 18
17 1716
16
15
1514
14
S
13 13
12 12
S
11
11 10
10
9
988
776
65
5
44
3
3
22
11
24
24
S23
23
22 22 21
2120
20
19 19
18
18
17
17 16 16
15
15
14 14
S
13
13
12
12
S
11
11
10
10
9
9
8
8
7
7
6
65
54
43
3
2
211
24 24
S
23 23
22
22
21
21
20
20
19 19
18
18
17 1716
16
15
15
14
14
S
13 13
12 12
S
11 11
10 10
9
9
8
8
7
76
6
55
44
332
2
1
1
24
24S
23
23
22
2221
21
20
2019
19
18
1817
17
16
16
15
15 14
14 S
13 13
12 12
S11
11
10
10
9
9
887
7
6
6
5
5
44
3
32
2
1
1
24
24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16 16
15 15
14
14
S
13 13 12 12
S
11
11
10
10
9
9
8
8
7
7
66
5
5
4
4
33
2
2
11
24
24
S
23
2322 22
21
2120
2019
19
18
18
17
17
16 16
15
1514 14
S
13
13
12 12
S
11 11
10 10
9
98
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
24 24
S
23
23
22
22
21
21
20
2019 19
18
18
17
17
16
16
15 15
14 14
S
13
13 12
12
S
11 11
10
10
99
88
7
7
66
5
5
4
4
3
32
211
24
24
S
23
23
22
2221
21 20
20
1919
18
18
17
1716
16 15
15
14
14 S
13
13
12
12
S11
11
10
109
98
8
7
7
6
6
5
54
43
3
22
1
1
24
24
S
23
23
22
22
2121
2020
1919
18
18
17
1716
16
15
15
1414
S
1313
12
12
S
1111
1010
9988
7
7
66
554
4
3
32
211
1212
S
11
11
10
10
99
88
77
66
5
5
44
33
2
2
1
1
24
24
S23
2322
222121
20
20
19
19
18
18
17
17
1616
15
15
14
14
S
13
13
1212
S
11
11 1010
9
9
88
7
7
6
65
5
4
4
3
32
2
1
1
24
24S
23
23
22
22 21
21
202019
19
1818
17171616
1515
1414 S
1313
1212
S11
11 10
10
9
9
887
7
6
6
5
54
4
33
2
21
1
24
24
S
23
232222
21
21
202019
19
18
181717
1616
15
15 1414 S
1313
12
12S
11
11
10
10
9
9
8
8
77
6
6
55
4
4
3
32
2
1
1
24
24
S
23
23
22
22
21
21
20
20
1919
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11 10
109
9
8
8
7
7
6
6
5
54
4
3
32
2
S11
3
124
3
3
3
124
1
124
1
2
124
2
2
2
124
1
124
1
1
1
124
0
124
0
0
124
0
0
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
0
0
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
V
G
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 49
Bank 50
Bank 51
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 84
Bank 94
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
ug575_c3_59_100815
{I XILINX¢ l l a E DDDIDDDDEDDDDIDD DEED DDBDDDDIDUDDBDDD DUI E l IDDDDEDDDDI DDDDIDDDDEDD DI EEEEUEEI DUDUUDUUDU DUDUUDUUDUUDU UDDUDUUDUUDUUDU Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-60
Figure 3-60: FFVB2104 Package—XCVU080 and XCVU095 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
18
16
4
2
5
3
200
17
30 28
35
33
34
29
29
29
29
29
2929 29
29
29
29
29
26
26
26 26
26 26
27
26
26 26
26
35
26 26
26
26
26 26
25 25
25
25
25 25
25
25
25
25
25
2531
32
25
36 37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
n n
nn
n n
nn
nn
n n
nn
n n
nn
nn
n n
nnn n nn
nnn n
nnn n nn
nnn n
nnn n
nn
nnn n
nnn n nn
nnn n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
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20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_60_100815
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Chapter 3: Device Diagrams
FLVB2104 (XCVU125)
X-Ref Target - Figure 3-61
Figure 3-61: FLVB2104 Package—XCVU125 I/O Bank Diagram
24 24
S
23
23
22 22
21
21 20
20
19
19
18 18
17 1716
16
15
1514
14
S
13 13
12 12
S
11
11 10
10
9
988
776
65
5
44
3
3
22
11
24
24
S23
23
22 22 21
2120
20
19 19
18
18
17
17 16 16
15
15
14 14
S
13
13
12
12
S
11
11
10
10
9
9
8
8
7
7
6
65
54
43
3
2
211
24 24
S
23 23
22
22
21
21
20
20
19 19
18
18
17 1716
16
15
15
14
14
S
13 13
12 12
S
11 11
10 10
9
9
8
8
7
76
6
55
44
332
2
1
1
24
24S
23
23
22
2221
21
20
2019
19
18
1817
17
16
16
15
15 14
14 S
13 13
12 12
S11
11
10
10
9
9
887
7
6
6
5
5
44
3
32
2
1
1
24
24
S
23
23
22 22
21
21
20
20
19
19
18
18
17
17
16 16
15 15
14
14
S
13 13 12 12
S
11
11
10
10
9
9
8
8
7
7
66
5
5
4
4
33
2
2
11
24
24
S
23
2322 22
21
2120
2019
19
18
18
17
17
16 16
15
1514 14
S
13
13
12 12
S
11 11
10 10
9
98
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
24 24
S
23
23
22
22
21
21
20
2019 19
18
18
17
17
16
16
15 15
14 14
S
13
13 12
12
S
11 11
10
10
99
88
7
7
66
5
5
4
4
3
32
211
24
24
S
23
23
22
2221
21 20
20
1919
18
18
17
1716
16 15
15
14
14 S
13
13
12
12
S11
11
10
109
98
8
7
7
6
6
5
54
43
3
22
1
1
24
24
S
23
23
22
22
2121
2020
1919
18
18
17
1716
16
15
15
1414
S
1313
12
12
S
1111
1010
9988
7
7
66
554
4
3
32
211
1212
S
11
11
10
10
99
88
77
66
5
5
44
33
2
2
1
1
24
24
S23
2322
222121
20
20
19
19
18
18
17
17
1616
15
15
14
14
S
13
13
1212
S
11
11 1010
9
9
88
7
7
6
65
5
4
4
3
32
2
1
1
24
24S
23
23
22
22 21
21
202019
19
1818
17171616
1515
1414 S
1313
1212
S11
11 10
10
9
9
887
7
6
6
5
54
4
33
2
21
1
24
24
S
23
232222
21
21
202019
19
18
181717
1616
15
15 1414 S
1313
12
12S
11
11
10
10
9
9
8
8
77
6
6
55
4
4
3
32
2
1
1
24
24
S
23
23
22
22
21
21
20
20
1919
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11 10
109
9
8
8
7
7
6
6
5
54
4
3
32
2
S11
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
V
G
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
0
0
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
V
G
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
33
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
11
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 45
Bank 46
Bank 50
Bank 51
Bank 52
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 84
Bank 94
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
ug575_c3_61_100815
{I XILINX¢ ID DIDDDDEDDDDIDDDD DDDBDDDBIDDDDBDD EDDDDIDDDDEDDDDI DDIDDDDEDDDDIDDD u l u u l DDDDDDDDDDDDD DDDDDDDDDD DDDDDDDDDDDDDDD I EEEEEDIDDDD Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-62
Figure 3-62: FLVB2104 Package—XCVU125 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14 18
16
4
2
5
3
200
17
19
30 28
35
33
34
29
29
29
29
29
2929 29
29
29
29
29
26
26
26 26
26 26
27
26
26 26
26
35
26 26
26
26
26 26
25 25
25
25
25 25
25
25
25
25
25
2531
32
25
36 37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLGB2104 (XCVU160 and XCVU190)
X-Ref Target - Figure 3-63
Figure 3-63: FLGB2104 Package—XCVU160 and XCVU190 I/O Bank Diagram
24 24
S
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22 22
21
21 20
20
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19
18 18
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S
13 13
12 12
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11
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10
9
988
776
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44
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3
22
11
24
24
S23
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211
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S
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18
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S
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S
11 11
10 10
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6
55
44
332
2
1
1
24
24S
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23
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2221
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2019
19
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1817
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S11
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887
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44
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1
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S
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66
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5
4
4
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2
2
11
24
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S
23
2322 22
21
2120
2019
19
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1514 14
S
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12 12
S
11 11
10 10
9
98
8
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7
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5
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3
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1
24 24
S
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2019 19
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14 14
S
13
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12
S
11 11
10
10
99
88
7
7
66
5
5
4
4
3
32
211
24
24
S
23
23
22
2221
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1919
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1716
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14 S
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12
12
S11
11
10
109
98
8
7
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6
5
54
43
3
22
1
1
24
24
S
23
23
22
22
2121
2020
1919
18
18
17
1716
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15
15
1414
S
1313
12
12
S
1111
1010
9988
7
7
66
554
4
3
32
211
1212
S
11
11
10
10
99
88
77
66
5
5
44
33
2
2
1
1
24
24
S23
2322
222121
20
20
19
19
18
18
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17
1616
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15
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14
S
13
13
1212
S
11
11 1010
9
9
88
7
7
6
65
5
4
4
3
32
2
1
1
24
24S
23
23
22
22 21
21
202019
19
1818
17171616
1515
1414 S
1313
1212
S11
11 10
10
9
9
887
7
6
6
5
54
4
33
2
21
1
24
24
S
23
232222
21
21
202019
19
18
181717
1616
15
15 1414 S
1313
12
12S
11
11
10
10
9
9
8
8
77
6
6
55
4
4
3
32
2
1
1
24
24
S
23
23
22
22
21
21
20
20
1919
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11 10
109
9
8
8
7
7
6
6
5
54
4
3
32
2
S11
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
V
G
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
0
0
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
V
G
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
33
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
11
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
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37
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41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 44
Bank 45
Bank 46
Bank 50
Bank 51
Bank 52
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 84
Bank 94
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_63_100815
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-64
Figure 3-64: FLGB2104 Package—XCVU160 and XCVU190 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14 18
16
4
2
5
3
200
17
19
30 28
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34
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26 26
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25 25
25
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2531
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25
36 37
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
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28
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42
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44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVC2104 (XCVU095)
X-Ref Target - Figure 3-65
Figure 3-65: FFVC2104 Package—XCVU095 I/O Bank Diagram
24
24
S
23
23
22
22
21
2120
20
1919
1818
17
17
16
1615
15
14
14
S
1313
12
12
S
1111
10
10
9
9
8
8
7
7
6
6
55
4
4
3
32
2
1
1
24
24
S23
23
22 22
21
21
20
20
19
19
18
1817
17
16
16
15 15
14 14 S
13 13
12 12
S
11 11
10
10
9
9
8877
66
5
54
433
2
2
1
1
24
24S
23
23
22 22
21
21
20 20
19
19
18
18
17
17
16
16
15 15
14 14
S
13 13
12 12
S
11
11
10 109
9
8
8
7
7
6
6
5544
3
3
2
21
1
24 24
S
23
23
22
22
21
21
20
20
19 19
18
1817 17
16
16
15
15
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14
S
13 13
12 12
S
11 11 10
10
9
9
88
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7
6
6
5
54
4
3
3
2
2
1
1
24
24
S
23
23
22 22
21 21
20 20
19 19
18 18
17
17
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16
15
15
14
14
S
13 13
12
12
S
11 1110
10
99
8
8
7
76
6
5
5
44
3
3
2
21
1
24
24
S
23
23
22
22
21
21
2020
19
19
18
18 17
17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
54
433
2
21
1
24
24
S
2323
2222
21
21
2020
19
19
1818
17
17
16
16
1515
1414
S
1313
1212
S
1111
10
10
9
988
7
7
665
5
44
3
32
2
1
1
24
24
S
23
23
2222
21
21
20
20
19
19
18
18
1717
161615
15 1414S
1313
1212
S
1111
10
10
9
9
88
7
7
6
65
544
3
3
2
2
S
1
1
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
00
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
V
G
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
22
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 84
Bank 94
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-66
Figure 3-66: FFVC2104 Package—XCVU095 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
19
1816 4
2
5
3
20 0
17
30
28
35
33
34
29
29
29
2929
29
2929
2929
29
29
26
2626
26
26
26
27
2626
26
26
35
2626
26
26
26
26
25
25
25
25
25
25
2525
25
25
25
25 31
32 25
36
37
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n n
n n
n n n nn n n n n n n nn n
n n n n
n n n n
n n n n
n n n n
n n n n
n n n n
n n nn n nn n
n n n n n nn n
n n nn n nn n
n n n n n nn n
n n nn n nn n
n nn n n n nn n n
n n n n n nn n
n n nn n nn n
n n n n n nn n
n n n nn n n n n n nn n nn n
n n n n n nn n
n nn n n n nn n nn n
n n n n nn n n n nn n
n nn n n n nn n n
n n nn n n
n n n n
n n n n
n n
n n
nn
n n
nn
nn n n
nn
n n
nn
nn n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVC2104 (XCVU125)
X-Ref Target - Figure 3-67
Figure 3-67: FLVC2104 Package—XCVU125 I/O Bank Diagram
24
24
S
23
23
22
22
21
2120
20
1919
1818
17
17
16
1615
15
14
14
S
1313
12
12
S
1111
10
10
9
9
8
8
7
7
6
6
55
4
4
3
32
2
1
1
24
24
S23
23
22 22
21
21
20
20
19
19
18
1817
17
16
16
15 15
14 14 S
13 13
12 12
S
11 11
10
10
9
9
8877
66
5
54
433
2
2
1
1
24
24S
23
23
22 22
21
21
20 20
19
19
18
18
17
17
16
16
15 15
14 14
S
13 13
12 12
S
11
11
10 109
9
8
8
7
7
6
6
5544
3
3
2
21
1
24 24
S
23
23
22
22
21
21
20
20
19 19
18
1817 17
16
16
15
15
14
14
S
13 13
12 12
S
11 11 10
10
9
9
88
7
7
6
6
5
54
4
3
3
2
2
1
1
24
24
S
23
23
22 22
21 21
20 20
19 19
18 18
17
17
16
16
15
15
14
14
S
13 13
12
12
S
11 1110
10
99
8
8
7
76
6
5
5
44
3
3
2
21
1
24
24
S
23
23
22
22
21
21
2020
19
19
18
18 17
17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
54
433
2
21
1
24
24
S
2323
2222
21
21
2020
19
19
1818
17
17
16
16
1515
1414
S
1313
1212
S
1111
10
10
9
988
7
7
665
5
44
3
32
2
1
1
24
24
S
23
23
2222
21
21
20
20
19
19
18
18
1717
161615
15 1414S
1313
1212
S
1111
10
10
9
9
88
7
7
6
65
544
3
3
2
2
S
1
1
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
V
G
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
00
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
V
G
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
1
1
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
22
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
33
3233
3
233
1
1233
22
2233
2
233
11
1233
1
233
0
0233
00
0233
0
233
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 84
Bank 94
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-68
Figure 3-68: FLVC2104 Package—XCVU125 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
1816 4
2
5
3
20 0
1719
30
28
35
33
34
29
29
29
2929
29
2929
2929
29
29
26
2626
26
26
26
27
2626
26
26
35
2626
26
26
26
26
25
25
25
25
25
25
2525
25
25
25
25 31
32 25
36
37
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
nn n n
nn
nn
n n
n n
nn
n n
nn
nnn n
nn n n
nn
nn n n
nn n n
nn
nn n n
nn n n
nn
nn n n
nn n n
nn
nn n n
nnn n
nn
n
nn
n n
nn
n
nn
n nnn
nnn n
nn
nnn n
n n
nnn n
nn
nnn n
nnn n
nn
nnn n
nnn n
nn
nnn n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
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20
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21
21
22
22
23
23
24
24
25
25
26
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27
27
28
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29
29
30
30
31
31
32
32
33
33
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35
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36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLGC2104 (XCVU160 and XCVU190)
X-Ref Target - Figure 3-69
Figure 3-69: FLGC2104 Package—XCVU160 and XCVU190 I/O Bank Diagram
24
24
S
23
23
22
22
21
2120
20
1919
1818
17
17
16
1615
15
14
14
S
1313
12
12
S
1111
10
10
9
9
8
8
7
7
6
6
55
4
4
3
32
2
1
1
24
24
S23
23
22 22
21
21
20
20
19
19
18
1817
17
16
16
15 15
14 14 S
13 13
12 12
S
11 11
10
10
9
9
8877
66
5
54
433
2
2
1
1
24
24S
23
23
22 22
21
21
20 20
19
19
18
18
17
17
16
16
15 15
14 14
S
13 13
12 12
S
11
11
10 109
9
8
8
7
7
6
6
5544
3
3
2
21
1
24 24
S
23
23
22
22
21
21
20
20
19 19
18
1817 17
16
16
15
15
14
14
S
13 13
12 12
S
11 11 10
10
9
9
88
7
7
6
6
5
54
4
3
3
2
2
1
1
24
24
S
23
23
22 22
21 21
20 20
19 19
18 18
17
17
16
16
15
15
14
14
S
13 13
12
12
S
11 1110
10
99
8
8
7
76
6
5
5
44
3
3
2
21
1
24
24
S
23
23
22
22
21
21
2020
19
19
18
18 17
17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10
10 9
9
8
8
7
7
6
6
5
54
433
2
21
1
24
24
S
2323
2222
21
21
2020
19
19
1818
17
17
16
16
1515
1414
S
1313
1212
S
1111
10
10
9
988
7
7
665
5
44
3
32
2
1
1
24
24
S
23
23
2222
21
21
20
20
19
19
18
18
1717
161615
15 1414S
1313
1212
S
1111
10
10
9
9
88
7
7
6
65
544
3
3
2
2
S
1
1
3
120
33
3
120
1
120
1
2
120
2
2
2
120
V
G
1
120
1
1
1
120
0
120
0
0
120
0
0
0
120
3
121
33
3
121
1
121
1
2
121
22
2
121
1
121
11
1
121
0
121
0
0
121
00
0
121
3
122
33
3
122
1
122
1
2
122
22
2
122
1
122
11
1
122
0
122
0
0
122
00
0
122
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
V
G
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
00
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
V
G
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
1
1
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3220
3
220
1
1220
2
2
2220
2
220
1
1
1220
1
220
0
0220
00
0220
0
220
3
3
3221
3
221
1
1221
2
2
2221
2
221
G
V
1
1
1221
1
221
0
0221
0
0
0221
0
221
3
3
3222
3
222
1
1222
2
2
2222
2
222
1
1
1222
1
222
0
0222
0
0
0222
0
222
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
22
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
33
3233
3
233
1
1233
22
2233
2
233
11
1233
1
233
0
0233
00
0233
0
233
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 84
Bank 94
Quad 120
Quad 121
Quad 122
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 220
Quad 221
Quad 222
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-70
Figure 3-70: FLGC2104 Package—XCVU160 and XCVU190 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
1816 4
2
5
3
20 0
1719
30
28
35
33
34
29
29
29
2929
29
2929
2929
29
29
26
2626
26
26
26
27
2626
26
26
35
2626
26
26
26
26
25
25
25
25
25
25
2525
25
25
25
25 31
32 25
36
37
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLGB2377 (XCVU440)
X-Ref Target - Figure 3-71
Figure 3-71: FLGB2377 Package—XCVU440 I/O Bank Diagram
24 24 S
23
23
22
22
21 21
20 20
19 19
18
18
17 17
16 16
15 15
14 14S13
13
12 12
S
11
11
10
10
9
9
88
7
766
55
4
4
3
3
2
2
1
1
24
24
S
23
23
22 22
21 21
20 20
19 19
18
1817
17
16 16
15 15
14
14S13
13 12 12
S
11
11
10 10
99
8
8
7
7
6
6
5
54
4
33
22
1
1
24 24
S
23
23
22
22
21
21
20
20
19 19
18 18
17 17
16
1615
15
14
14S13
13
12
12
S
11 11
10
10
9
9
8
8
77
6
6
55
4
4
33
22
11
24
24
S
23
23
22 22
21
21 20
20
19 19
18
18
17
17
16 16
15
15
14
14
S
13 13 12
12
S
11 11
10
10 9
9
8
8
77
66
55
44
3
3
2
2
11
24 24
S
23 23
22 22
21 21
20 20
19 19
18
18
17
17
16
16
15 15
14 14
S
13 13
12
12
S
11 11
10 10
9
9
8
8
77
66
55
4
4
33
22
1
1
24
24S
23
23
22 22
21 21
20 20
19 19
18
18
17 17
16
1615 15
14
14
S
13 13
12 12
S
11
11 10
10
9
9
8
8
7
7
6
6
55
44
3
3
22
11
24
24
S
23
23
22 22
21 21
20 20
19 19
18
18
17 17
16
16
15 15
14 14
S
13
13
12
12
S
11 11
10
10
9
9
8
8
7
7
6
65
54
4
3
3
2
211
24
24
S
23 23
22
22
21
21 20
20
19
19
18 18
17
17 16
16
15
15
14 14
S
13
13
12
12
S
11
11
10
10
9
9
88
77
6
6
55
44
3
3
2
2
1
1
24
24
S
23
2322
22
2121
2020 19
19
18
18
17
17
16
16
15
15
14
14
S
13
13
12
12
S
11
11
10
10
9
9
88
7
7
6
65
5
4
4
3
3
22
1
1
24
24
S23
23
22 22
21 21
20
20 19
19
18 18
17
17
16 16
15
15
14
14
S13
13
12
12 S
11 11
10 109
9
8
8
77
6
65
5
44
33
2
2
1
1
24 24
S
23 2322 22
21
21
20 20
19 19
18
1817 1716 16
15 15 14 14
S
13 13
12
12 S
11
1110
10
9
988
77
66
5
544
3
322
1
1
24 24S
23 2322 22
21 21
20 20 19 19
18
18
17
17
16 16
15
15
14
14
S
13
13
12 12
S
11 11
10 10
99
8877
665
5
4
4
33
2
211
24
24 S
2323
2222
21
21
20
20
19
19
1818
17
17 1616
1515
14
14
S1313
1212
S
11
11
1010
99
88
7
7
6
655
44
3
3
22
11
2424 S
2323
2222 21
21 20
20
19
19
18
1817
17
161615
15 1414
S
1313 12
12
S1111
1010
99
88
77
66
55
44
33
22
1
1
2424 S
2323
2222 2121
20
20
1919
18
18 1717
16
1615
15
1414 S
13
13
1212
S1111
10
10
99
88
7
76
65
54
4
33
22
11
2424
S
2323
22
22
21
21
20
20
19
19
18
1817
17
16
16
15
15
14
14
S
13
13 1212
S11
11
10
10 9
98
877
66
5
54
4
3
3
22
1
1
24 24
S
23 2322 22
21 21
20
20
19
19
18 1817 17
16 16
15
15
14
14
S
13 13
12 12
S
11
11
10 10
99
88
7
7
6
6
55
443
32
211
24
24
S
23 23
22 22
21
21
20 20
19
19
18
1817 17
16 16
15 15
14 14
S
13 13
12 12
S11
11
10
109
988
7766
55
4
4
3
3
22
1
1
24 24
S
23
23
22 22
21 21
20 20
19 19
18
1817 1716
16
15 15
14
14
S
13 13
12 12 S11
11
10 10
998
8
7
766
55
4
43
322
11
24 24S23
2322 22
21 2120 20
19 19
18
18 17
17
16
16
15 15
14
14
S
13
1312
12
S
11 11
10
10
9
988
77
6
6
5
5
44
3
3
2
211
24
24
S23
232222
21
21
20
20
1919
1818 1717
16
16
1515
14
14
S
1313
12
12
S
1111
1010
9
9
887
7
6
6
5
5
4
4
33
2
21
1
2424
S
2323 2222
2121
20
20 1919
18
18
17
17
16
16 15
15 14
14
S
1313 12
12
S
11
11 10
10
9
9
88
7
7
6
6
55
4
43
3
2
21
1
2424
S
23
23 2222
21
21
2020
19
19
18
18
1717
1616
1515
1414 S
1313
1212
S11
11 10
10
99
8
8
77
66
55
4
4
33
22
11
24
24
S
2323
22
22
2121
2020
19
19
18
18
17
17
1616
1515
14
14
S
13
131212
S
1111
101099
8
8
7
7
66
5
5
4
43
3
22
1
1
2424 S
232322
22
21
21 20
20 1919
1818
1717 1616
151514
14
S
1313
1212
S
11
11
10
109
9887
76
6
55
44
3
3
22
S
1
1
3
3
3221
3
221
1
1221
2
2
2221
2
221 G
V
1
1
1221
1
221
0
0221
0
0
0221
0
221
3
3
3222
3
222
1
1222
2
2
2222
2
222
1
1
1222
1
222
0
0222
0
0
0222
0
222
3
3
3223
3
223
1
1223
2
2
2223
2
223
1
1
1223
1
223
0
0223
0
0
0223
0
223
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
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34
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35
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36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
A A
BB
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
Bank 40
Bank 41
Bank 42
Bank 43
Bank 45
Bank 46
Bank 47
Bank 48
Bank 50
Bank 51
Bank 52
Bank 53
Bank 60
Bank 61
Bank 62
Bank 63
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 221
Quad 222
Quad 223
Quad 224
Quad 225
Quad 226
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_71_100815
(I XILINX¢ DUE EDDDDIDD u u DDIDDTH DD IDDDDE D ID DEDDDJIE DD! I u u DDDIDTHF EU I u IDDDDEDDDDI u D D D D D D D D D D D D D D D D D D D D D D D D D D D l D D D D D D D D D D D D D D D Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-72
Figure 3-72: FLGB2377 Package—XCVU440 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5 3
20
0
17
19
30 28
35
33 3429 29
29 29
29
29
29
29
29 2929 29
26 26
26
26
26
26
27
26 26
26 26
35
26
26
26 26
26 26
25 25
25
25
25
25
25 25
25 25 25
2531
32
25
36 37
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V V
V
V
V
V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
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10
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25
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29
29
30
30
31
31
32
32
33
33
34
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37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
A A
BB
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
ug575_c3_72_100815
{I XILINX¢ — — — - I - CDOOOOO DDS 000600 Send Feed back
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Chapter 3: Device Diagrams
FLGA2577 (XCVU190)
X-Ref Target - Figure 3-73
Figure 3-73: FLGA2577 Package—XCVU190 I/O Bank Diagram
2424
S
23
23 22
22
21
21
20
20 1919
18
18
1717
16
16
1515
1414
S
131312
12 S11
11
1010
998
877
66
5
5
4
4
33
2
211
24
24
S
23
23
22
22
21
21
20
20
19 19
18
18
17
17
16
16
15
15
14
14
S
13
13
12 12
S11 11
10 10
9
9
8
877
6
65
5
44
33
22
1
1
24 24
S
23
2322 22
21 21
20
20 19 1918
18
17 17
16 16 15 15
14 14
S
13 13
12
12
S
11
11 10
10
9
9
8
877
6
6
5
5
4
4
3
3
2
2
11
2424
S23
23
2222
21
21
2020
1919
18
18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
1111
10
10
99
88
77
6
6
55
4
4
33
2
2
1
1
S
12
12
1111
24 24
S
23
23
22 22
21
21
20 20
19
19
18 18
17 1716 16
15 1514 14
S
13
13
12 12
S
11 11
10 10
998
8
7
7
6
6
55
44
3
32
2
11
12 12
S
11 11
10
10
9
9
8
877
66
5
5
4
4
3
32
2
1
1
24
24
S
23
23
22
22
21
21
20 20
19
19
18
18
17
17
16
16
15 15
14
14
S
13 13
12 12
S
11
11
10
10
99
88
7
7
66
554
4
3
3221
124
24S
23
23
2222
2121
20
20
1919
18
18
1717 16
16 15
15
1414
S
1313
1212
S
11
11 10
109
9
88
7
7
6
6
55
4
4
33
2
2
1
1
24
24
S2323
2222
2121
20
20
1919
1818
17
17 16
16
1515
1414
S
13
13
1212 S
1111
1010
9
9
88
77
6
6
55
44
33
22
1
1
3
119
3
3
3
119
1
119
1
2
119
2
2
2
119
1
119
1
1
1
119
0
119
0
0
119
0
0
0
119
3
120
3
3
3
120
1
120
1
2
120
22
2
120
V
G
1
120
1
1
1
120
0
120
0
0
120
0
0
0
120
3
121
33
3
121
1
121
1
2
121
2
2
2
121
1
121
1
1
1
121
0
121
0
0
121
0
0
0
121
3
122
33
3
122
1
122
1
2
122
22
2
122
1
122
11
1
122
0
122
0
0
122
00
0
122
3
123
33
3
123
1
123
1
2
123
22
2
123
1
123
11
1
123
0
123
0
0
123
00
0
123
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
12
125
22
2
125
V
G
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
12
126
22
2
126
1
126
11
1
126
0
126
00
126
00
0
126
3
127
33
3
127
1
127
12
127
22
2
127
1
127
11
1
127
0
127
00
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
00
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
V
G
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
33
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
2
2
2
132
1
132
1
1
1
132
0
132
0
0
132
0
0
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
00
0
133
3
3
3219
3
219
1
1219
22
2219
2
219
11
1219
1
219
0
0219
0
0
0219
0
219
3
3
3220
3
220
1
1220
2
2
2220
2
220
1
1
1220
1
220
0
0220
0
0
0220
0
220
3
3
3221
3
221
1
1221
2
2
2221
2
221
G
V
1
1
1221
1
221
0
0221
0
0
0221
0
221
3
3
3222
3
222
1
1222
2
2
2222
2
222
1
1
1222
1
222
0
0222
0
0
0222
0
222
3
3
3223
3
223
1
1223
2
2
2223
2
223
1
1
1223
1
223
0
0223
0
0
0223
0
223
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231 G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
33
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 61
Bank 62
Bank 63
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Quad 119
Quad 120
Quad 121
Quad 122
Quad 123
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 219
Quad 220
Quad 221
Quad 222
Quad 223
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-74
Figure 3-74: FLGA2577 Package—XCVU190 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
20
0
17
19
3028
35 33
34
2929
29
29
2929
2929
29
29
29
29
26
26
26
26 26
26
27
26
26
26
26
35
2626
26
26
2626
2525
2525
25
25
2525
25
25
2525
31
32
25
36
37
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V V
V V
V V
V V
V
V
V
V
V
V
V
V
V V
V V
V V
V V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VV
V V
VV
V V
VV
V V
V
V
V
V
V
V
V
V
VV
V V
VV
V V
VV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
n n n n
n n n n
n n n n n n n n
n n n n n n n n
n n n n n n n n
n n n n
n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLGA2892 (XCVU440)
X-Ref Target - Figure 3-75
Figure 3-75: FLGA2892 Package—XCVU440 I/O Bank Diagram
24
24
S
23
23
22 22
21
21
20
20
19
19
18
18
17 17
16 16
15 15
14
14
S
13 13
12
12
S11 11
10 10
9988
77
6655
4
433
22
11
24 24
S
23
23 22
22
21
21
20
20 19 19
18 18
17 17
16 16
15
15
14
14
S
13
13
12 12
S11
11
10
10
9
9
88
7
7
6
6
5
5
4
4
3
3
2
21
1
24
24S
23
23
22 22
21 21
20 2019
19
18 18
17 17 16 16
15 15
14 14
S
13 13
12 12
S
11 11
10
10
9
9
8
87
7
66
55
44
33
2
2
11
24 24
S23 23
22
22 21 21
20 20
19 19 18 18
17 17
16 16
15 15
14
14
S
13 13
12
12
S
11
11
10 10
9
9
88
7
7
6
6
55
4
4
3
3
22
1
1
24 24
S
23 23 22
2221
21
20 20
19 19
18 18
17 17
16 16
15 15
14 14
S
13 13
12 12
S
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
33
2
211
24
24 S
23 23
22 22
21 21
20 20 19
19
18 18
17 17
16 16
15
15
14
14S
13
13
12 12
S
11 11
10 10
9
9
8
8
7
7
6
6
55
44
332
2
11
24
24S
23 23
22 22
21 21
20 20 19
19
18 18
17 17
16 16
15 15
14
14
S
13
13
12 12
S
11 11
10
10 9
9
88
7
7
6
6
5
5
4
4
3
3
2
2
1
1
24
24
S
23 23 22 22
21 21
20
20
19 19 18
1817 17
16 16
15 15 14 14
S
13
13 12 12
S
11
11
10
10
9
9
887
7
66
55
4
4
3
3
22
11
24
24
S
23
23
22 22
21
21
20
20
19
19
18 18
17
17
16 16
15
15
14
14
S
13
13
12 12
S
11
11
10
10
9
9
8
8
77
6
655
44
33
22
11
24
24 S
23
23
22 22
21 21
20 2019 19
18 18
17 17
16
1615
15
14 14
S
13
1312 12
S
11
11
10
10
99
88
77
6
6
5
544
33
2211
24
24
S
23
23
22
22
21
21
20
20
19
19
18 18
17
17
16
16 15
15
14
14
S
13
13
12 12
S
11
11
10
10
9
9
88
7
7
66
55
44
33
2
2
1
1
24
24S
23
23
22 22
21
2120
20
19
19
18
1817
17
16
16
15
15
14
14
S
13
13
12
12
S
11
11 10
10
9
9
8
8
7
7
6
6
5
54
4
33
2
2
1
1
24 24
S23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
1615
15
14
14
S
13 13
12
12
S
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
21
1
24 24
S
23 23
22 22
21 21
20
20
19 19
18
18
17
17
16 1615 15
14 14
S
13
13
12
12
S
11 11
10
10
99
88
77
66
5
5
44
3
32
2
1
1
24
24
S
23 23
22 22
21 21
20 20
19 19
18 18
17 17
16
16
15
1514 14
S
13 1312 12
S
11 11
10 10
9
9
8
8
77
66
5
5
4
4
33
2
2
11
24
24
S
2323
22
22
21
21 2020
1919
18
18
17
17
16
16 1515
14
14
S
13
13
12
12
S
11
11
1010
9
9
88
7
7
6
65
5
4
4
33
22
11
24
24S2323
22
2221
21
2020
19
19
18
18
17
17
1616 15
1514
14 S
13
13
12
12
S
1111
10
10
99
8
8
7
7
6
65
5
44
3
32
2
1
1
24
24
S
23
23
22
22
21
21
20
20
19
19
18
1817
17
16
16 15
15
1414
S
13
13
1212
S
11
11
1010
9
98
877
6
6
5
54
4
3
3
22
1
1
24
24
S
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14 S
13
13
1212
S
1111
10
10
99
88
7
7
6
65
5
4
43
322
1
1
24
24
S
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14 14S
13 13
12
12S11
11
10
10
99
8
8
7
7
6
65
5
44
3
32
2
1
1
24 24
S
23
2322 22
21 21
20
20
19
19
18 18
17
17
16 16
15
15
14
14
S
13
13
12 12
S
11
11
10
10
99
8
8
7
7
6
6
55
443
3
2211
24
24
S23
23
22 22
21
21
20
20
19
19
18 18
17
17
16
16
15
15 14
14
S
13
13
12
12
S
11
11 10
1099
887
766
55
443
3
22
1
1
24 24
S
23 23
22
22
21
21
20
20
19
19
18
1817
17
16 16
15
15
14
14S
13
13
12
12
S
11
11
10 10
9
98
8
7
7
66
55
44
332
211
2424
S
2323
2222
2121
20
20
1919
18
18
17
171616
15
15
14
14
S
1313
1212
S
11
11
10
10
9
9
887
7
66
5
54
4
3
3
2
2
11
2424
S
2323
2222
2121
2020
19
19
18
18
17
1716
16
15
15
14
14 S
13
13
12
12
S
11
11
10
10
9
9
8
87
7
6
6
55
44
3
3
22
11
24
24 S
23
23
22
22
21
21
2020
19
19
18
18
17
1716
16
15
15
14
14
S13
13
12
12
S
11
11
10
10 9
9
8
8
77
6
6
5
5
4
4
33
2
2
1
1
24
24
S23
23
22
22
21
21
2020
19
19
1818
1717
16161515
14
14
S
1313
1212
S
11
1110
10
9
9
8
8
7
7
6
6
5
5
44
33
2211
2424
S
23
23
22
22 21
21
2020 19
19
18
18
17
1716
16
1515 14
14
S
13
13 12
12
S
11
11
10 10
9
9
8
8
7
7
665
54
4
3
3
22
S
1
1
3
3
3219
3
219
1
1219
2
2
2219
2
219
1
1
1219
1
219
0
0219
0
0
0219
0
219
3
3
3220
3
220
1
1220
2
2
2220
2
220
1
1
1220
1
220
0
0220
0
0
0220
0
220
3
3
3221
3
221
1
1221
2
2
2221
2
221
G
V
1
1
1221
1
221
0
0221
0
0
0221
0
221
3
3
3222
3
222
1
1222
2
2
2222
2
222
1
1
1222
1
222
0
0222
0
0
0222
0
222
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
VCCO
39
VCCO
39
VCCO
39
VCCO
39
VCCO
39
VCCO
39
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
49
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
84
VCCO
84
VCCO
84
VCCO
84
VCCO
94
VCCO
94
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
BM BM
BN BN
BP BP
Bank 39
Bank 40
Bank 41
Bank 42
Bank 43
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 49
Bank 50
Bank 51
Bank 52
Bank 53
Bank 60
Bank 61
Bank 62
Bank 63
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 73
Bank 84
Bank 94
Quad 219
Quad 220
Quad 221
Quad 222
Quad 224
Quad 225
Quad 226
Quad 227
Quad 229
Quad 230
Quad 231
Quad 232 SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[H or Y]RXP#
#MGT[H or Y]RXN#
#MGT[H or Y]TXP#
#MGT[H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-76
Figure 3-76: FLGA2892 Package—XCVU440 Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
1
15
13
6
14
18
16
4
2
5
3
20
0
17
19
30
28
35
33
34
29
29
29
29
29
29
29
29
29
29
29
29
26
26
26
26
26 2627
26 26
26
2635 26
26
26
26
26 26
25
25
25
25
25
2525
25
25 25
25
25 31
3225
36
37
E
E
E
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
V V
V
V V
V
V
V
V
V
V
V
V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
BM BM
BN BN
BP BP
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO_[bank number]
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Dedicated Pins
0 CCLK_0
1 CFGBVS_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 I2C_SDA
35 PERSTN[0 to 1]
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVA676 (XCKU3P and XCKU5P)
X-Ref Target - Figure 3-77
Figure 3-77: FFVA676 Package—XCKU3P and XCKU5P I/O Bank Diagram
2424
2323
22
22
212120
20
19
19
S
S
18
18
17
17
16
16
1515
14
14
13
13 1212
1111
1010
99
8
8
77
S
6
65
5
4
4
33
22
11
24 24
23
23
22
22
21 21
20 20
19 19 S
S
18
18
17
17
16
1615 15
14
14
13
13 12 12
11
11
10 10
9
9
8
87
7
S
66
5
5
4
4
3
3
2
2
1
1
2424
23
23
22
22
2121 20
20
19
19
S
S
1818
17
17
1616
15
15
1414
1313
12
12
1111
1010
99
8
8
7
7
S
66
5
5
44
33
2
2
1
1
2424
23
23
2222
2121
20
20
19
19
S
S
18
181717
1616 15
15
14
14 1313
1212 11
11
10
10
99
8877
S
66
5
5
4
4
3
3
2
21
1
12 1211 11
10 10
9
988
77
66
5
5
4
4
3
3
2
2
11
12 12
11 11
10 10
9
9
8
8
7
7
66
55
4
43
3
221
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
G
V
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
84
VCCO
84
VCCO
84
VCCO
85
VCCO
85
VCCO
85
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 64
Bank 65
Bank 66
Bank 67
Bank 84
Bank 85
Quad 224
Quad 225
Quad 226
Quad 227
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-78
Figure 3-78: FFVA676 Package—XCKU3P and XCKU5P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
1816
4
2
5
3
20
0
17
2830
34
33
29
29
2929 29
29
29
29
35
27
2929
29
29
2626
26
26
2626
2626
26
26
2626
2626
2626
25
25
25
25
38
25
2525
25
25
2525
2525
32
31
37
36
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
n
n
n
n
n
n
n
nn
n
n
n
n
n
n
n
nn
nn
n
nnn
n
n
n
n
n
n
nn
n
n
n
n
nn
nn
n
n
n
n
nn
n
n
n
n
n
n
n
n
n
n
n
n
nn
n
n
n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
ug575_c3_100_030817
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVB676 (XCKU3P and XCKU5P) and FFRB676
(XQKU5P)
X-Ref Target - Figure 3-79
Figure 3-79: FFVB676 Package—XCKU3P and XCKU5P and FFRB676 Package—XQKU5P
I/O Bank Diagram
24
24
2323
22
22
21
21
20
20
1919
S
S
181817
17
1616
15
15
1414
1313
121211
11 10
10
99
88
77
S
6
6
5
5
44
3
3
2
2
1
1
2424
23
23
22
22 2121
20
20
1919
S
S
1818
17
17
1616
1515
1414
1313
1212
1111
1010
99
88
77
S
6
6
5
5
4
4
33
22
1
1
2424
23
23
22
22
2121
2020
1919
S
S
1818
1717
16
16
15
15
14
14
13
13
12
12
11
11
1010
99
8877
S
66
55
44
3
3
22
1
1
24
24
23
23
22
22 21
21
20
20
1919
S
S18
18
17
17
16
16
1515
14
14
13
13
12
12
11
11
10
10
99
8
8
7
7
S
6
6
554
4
33
22
11
12
12
11 11
10
10 99
88
77
665
5
44
3
32
2
1
1
12
12
11
11
10
10
9
988
77
66
554
43
322
11
1212
11
11
1010
9
9
8
87
7
66
55
44
3
3
2
2
11
0224
0
1224
1
G
V
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0225
0
1225
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
84
VCCO
84
VCCO
86
VCCO
86
VCCO
87
VCCO
87
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
ug575_c3_100_030817
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 64
Bank 65
Bank 66
Bank 67
Bank 84
Bank 86
Bank 87
Quad 224
Quad 225
Quad 226
Quad 227
(I XILINX¢ D DIDDDDID l DDDIDDDD u l DDBDD I B DUI]- u l D UBEDW’H’ E l l DDDDDDDDD IUUDUIUEEEEEEEI DUUDUDDUDDUDDUD DUDUDDUDDUDDUD Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-80
Figure 3-80: FFVB676 Package—XCKU3P and XCKU5P and FFRB676 Package—XQKU5P
Configuration/Power Diagram
0
R
2
34
5
6
8 7
9
1011
12
13
14
15
16
17
18
19
20
22
2124
23
2830
34
33
29
29
2929
2929
2929
35
27
2929
2929
26
26
26
26
26
26
26
26
26
26
26
26
2626
2626
25252525
38
252525
2525
2525
25
25
3231
37
36
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
SFVB784 (XCKU3P and XCKU5P) and SFRB784
(XQKU5P)
X-Ref Target - Figure 3-81
Figure 3-81: SFVB784 Package—XCKU3P and XCKU5P and SFRB784 Package—XQKU5P
I/O Bank Diagram
2424 23
23
2222
2121
20
20
1919
S
S
1818
17
17 16
16
15
15
14
14
1313
1212 11
11
1010
998
8
77
S
66
55
44
33
22
1
1
2424
2323
2222
2121
20
20
19
19
S
S
1818
1717
16
16
15
15
14
14 13
13
1212
1111
10
10
9
9
88
7
7S66
5
5
4
4
3
3
2
2
1
1
2424
23
232222
21
21
20
20
19
19
S
S
1818
1717
16
16
15
15
14
14
13
13
1212
11
11
1010
99
8
8
7
7
S
6
655
4
4
3
3
22
1
1
2424
232322
22
21
21
2020
19
19
S
S
18
18
17
1716
16
15
15
14
14 1313
1212
1111
1010
9
9
887
7S
66
55
4
4
33
2
21
1
1212
1111 10
10 99
8877
6655
4
4
33
22
1
1
12 1211 11
10
10
99
8
8
7
7
6
6
55
4
4
3
32
21
1
12
12
11
11
10 10 9
9
8
8
7
7
6
6
55
44
33
2
2
11
1212
1111
1010
9
9
88
77
6
6
5
5
4
4
3
3
2
2
11
V
0224
0
1224
1
G
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0225
0
1225
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
84
VCCO
84
VCCO
85
VCCO
85
VCCO
86
VCCO
86
VCCO
87
VCCO
87
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
Bank 64
Bank 65
Bank 66
Bank 67
Bank 84
Bank 85
Bank 86
Bank 87
Quad 224
Quad 225
Quad 226
Quad 227
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-82
Figure 3-82: SFVB784 Package—XCKU3P and XCKU5P and SFRB784 Package—XQKU5P
Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
15 13
14
16
17
18
19
20
22
2124
23 2830
34
332929
29
29
29
29
29
29
35
27
2929
2929
26
26
26
26
26
26
26
26
2626
26
26
2626
2626
25
25
25
25
38
25
25
25 2525
25
25
25
25
3231
37
36
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVD900 (XCKU3P and XCKU5P)
X-Ref Target - Figure 3-83
Figure 3-83: FFVD900 Package—XCKU3P and XCKU5P I/O Bank Diagram
24
24
23
23 22
22
21
21
2020
1919
S
S18
181717 1616
1515
1414
1313
1212
1111
1010
9
9
88
7
7S
6
6
5
5
44
33
22
11
24
24
23
2322
22
21 2120
20
19 19
S
S
18
18
17
17
16 16
15 15
14 14
13 1312 12
11 11
10
10
998
8
77S
66
5
5
44
3
32
2
11
24
24
23
23
22
22 21
21
2020 19
19
S
S
18
18
17
1716
16
1515
14
14
13
13
12
12 1111
10
10
9
98
8
77
S6
6
5
5
44
33
2
21
1
24
24
23
23
22
22
21
21
2020
1919
S
S18
18
1717
16
16
15
15
14
14
1313
1212
1111
10
10
9988
77S
66
55
4
4
33
2
2
1
1
12
12
11
11
1010
9
9
8
8
7
7
6
655
4
4
3
3
2
21
1
12 1211
11 10
109
98
8
7
7
665
5
44
33
2
211
12 12
11 1110
10 998
877
665
544
3
3
2
21
1
12 1211 1110
1099
8
877
665
54
43
3
22
11
0224
0
1224
1
G
V
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0225
0
1225
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
84
VCCO
84
VCCO
85
VCCO
85
VCCO
86
VCCO
86
VCCO
87
VCCO
87
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
A
G AG
AH AH
AJ AJ
AK AK
Bank 64
Bank 65
Bank 66
Bank 67
Bank 84
Bank 85
Bank 86
Bank 87
Quad 224
Quad 225
Quad 226
Quad 227
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-84
Figure 3-84: FFVD900 Package—XCKU3P and XCKU5P Configuration/Power Diagram
8 7
23
24 21
22
1011912
R
15
13
6
14
19
18
16
4
2
5
3
20
0
17
28
30
34
33
29
29 29
29
2929 29
29
35
27
29
29
29
2926
26
2626
26
26
26
26
26
26 2626
26
26
26
26 25
25
2525
38
25
25
25
25
25
2525
2525
32
31 37
36
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
nn
n
n
n
n
n
n
n n n n n
n
n
n
n n n n
n
n
n
n n n n
n n
n
n n n n
n n
nn n n n
n
n
n
n n n n
n
n
n n n n
n
n n n
n
n
n
n n
n n n
n n n
n n
n n n
n n n n
n n n n
n n n n n
n
nn
n n n n
n n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
ug575_c3_100_030817
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVD900 (XCKU11P)
X-Ref Target - Figure 3-85
Figure 3-85: FFVD900 Package—XCKU11P I/O Bank Diagram
2424
2323 22
22
21
21
20201919
S
S18
18
1717
1616
1515
1414
1313
1212
1111
10
10
99
8877
S
66
55
44
33
22
1
1
24
24
2323
22
22
2121
20
20
19
19 S
S
1818
1717
1616
1515
1414
13
13
12
12
11
11
10
10
99
88
77
S66
55
4
4
33
22
1
124
24
23
23 22
22
21
21
2020
1919
S
S18
181717 1616
1515
1414
1313
1212
1111
1010
9
9
88
7
7S
6
6
5
5
44
33
22
11
24
24
23
23
22
22
21
21
2020
1919
S
S18
18
1717
16
16
15
15
14
14
1313
1212
1111
10
10
9988
77S
66
55
4
4
33
2
2
1
1
24
24
23
2322
22
21 2120
20
19 19
S
S
18
18
17
17
16 16
15 15
14 14
13 1312 12
11 11
10
10
998
8
77S
66
5
5
44
3
32
2
11
24
24
23
23
22
22 21
21
2020 19
19
S
S
18
18
17
1716
16
1515
14
14
13
13
12
12 1111
10
10
9
98
8
77
S6
6
5
5
44
33
2
21
1
12
12
11
11
1010
9
9
8
8
7
7
6
655
4
4
3
3
2
21
1
12 1211
11 10
109
98
8
7
7
665
5
44
33
2
211
12 12
11 1110
10 998
877
665
544
3
3
2
21
1
12 1211 1110
1099
8
877
665
54
43
3
22
11
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
G
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
88
VCCO
88
VCCO
89
VCCO
89
VCCO
90
VCCO
90
VCCO
91
VCCO
91
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
A
G AG
AH AH
AJ AJ
AK AK
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 88
Bank 89
Bank 90
Bank 91
Quad 224
Quad 225
Quad 226
Quad 227
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-86
Figure 3-86: FFVD900 Package—XCKU11P Configuration/Power Diagram
0
R
23
4
5
6
8 7
91011 12
13
14
15
16
17
18
19
20
22
2124
23
28
30
34
33
29
29 29
29
2929 29
29
35
27
29
29
29
2926
26
2626
26
26
26
26
26
26 2626
26
26
26
26 25
25
2525
38
25
25
25
25
25
2525
2525
32
31 37
36
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVE900 (XCKU9P)
X-Ref Target - Figure 3-87
Figure 3-87: FFVE900 Package—XCKU9P I/O Bank Diagram
1212
11
11
10
10
99
88
7
7
6
6
5
5
4
4
33
22111212 1111
10
10
9
9
88
7
7
66
55
4
433
2
21
1
12
12
11
11
1010
99
887
76
655
4
4
33
2
21
11212
1111
10
10
9
9
8
8
77
66
55
4
4
33
22
1
1
24 24
23
23
22 22
21 21
20
20
19
19
S
S18 18
17 17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9
9
88
77
S
6
6
5
54
433
2
21
1
24
24
23
23
22
22
21
21
20 20
19 19
S
S
18 18
17
17
16 1615 15
14 14
13 13
12
12
11 11
10 10 9
9
88
77S
6
6
5544
3
3
22
1
1
24
24 23 23
22
22 21 21
20
20
19 19
S S
18
18
17
17
16
16
15
1514
14
13
13
12 12
11 11
10 10
99
88
7
7
S
6
6
55
4
4
3
3
2
2
11
24 24
23 23
22
22
21
21
20
20
19 19
S S
18 18 17
17
16 16
15
15
14
1413
13
12 12
11 11
10 10
9
9
8
8
77
S
66
55
44
33
22
11
33
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
00
0
127
0
127
3
3
3
128
3
128
1
1
128
22
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3
129
3
129
1
1
129
2
2
2
129
2
129
11
1
129
1
129
0
0
129
0
0
0
129
0
129
33
3
130
3
130
1
1
130
22
2
130
2
130
11
1
130
1
130
0
0
130
00
0
130
0
130
3
3
3228
3
228
1
1228
2
2
2228
2
228
G
V
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
VCCO
44
VCCO
44
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
A
G AG
AH AH
AJ AJ
AK AK
Bank 44
Bank 47
Bank 48
Bank 49
Bank 64
Bank 65
Bank 66
Bank 67
Quad 127
Quad 128
Quad 129
Quad 130
Quad 228
Quad 229
Quad 230
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-88
Figure 3-88: FFVE900 Package—XCKU9P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
18
16
4
2
5
3
20
0
17
35
34 28 33
29
29 29 29
29
29
29 29
29 29
29
26
29
26
26
26
26
2626
30
26
27
26 26
26 26
26 26
26 26
25 25
25
25
25
25 25
25
25 25
25
38
25
25
31
36
32 37
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVE900 (XCKU13P)
X-Ref Target - Figure 3-89
Figure 3-89: FFVE900 Package—XCKU13P I/O Bank Diagram
1212
11
11
10
10
99
88
7
7
6
6
5
5
4
4
33
22111212 1111
10
10
9
9
88
7
7
66
55
4
433
2
21
1
12
12
11
11
1010
99
887
76
655
4
4
33
2
21
11212
1111
10
10
9
9
8
8
77
66
55
4
4
33
22
1
1
24 24
23
23
22 22
21 21
20
20
19
19
S
S18 18
17 17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9
9
88
77
S
6
6
5
54
433
2
21
1
24
24
23
23
22
22
21
21
20 20
19 19
S
S
18 18
17
17
16 1615 15
14 14
13 13
12
12
11 11
10 10 9
9
88
77S
6
6
5544
3
3
22
1
1
24
24 23 23
22
22 21 21
20
20
19 19
S S
18
18
17
17
16
16
15
1514
14
13
13
12 12
11 11
10 10
99
88
7
7
S
6
6
55
4
4
3
3
2
2
11
24 24
23 23
22
22
21
21
20
20
19 19
S S
18 18 17
17
16 16
15
15
14
1413
13
12 12
11 11
10 10
9
9
8
8
77
S
66
55
44
33
22
11
33
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
00
0
127
0
127
3
3
3
128
3
128
1
1
128
22
2
128
2
128
G
V
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3
129
3
129
1
1
129
2
2
2
129
2
129
11
1
129
1
129
0
0
129
0
0
0
129
0
129
33
3
130
3
130
1
1
130
22
2
130
2
130
11
1
130
1
130
0
0
130
00
0
130
0
130
3
3
3228
3
228
1
1228
2
2
2228
2
228
G
V
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
VCCO
44
VCCO
44
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
49
VCCO
49
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
A
G AG
AH AH
AJ AJ
AK AK
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 44
Bank 47
Bank 48
Bank 49
Bank 64
Bank 65
Bank 66
Bank 67
Quad 127
Quad 128
Quad 129
Quad 130
Quad 228
Quad 229
Quad 230
ug575_c3_100_030817
(I XILINX¢ DDDDIDDDDEDDD I DDIDDDDIDDDDI IDDDDIDDDDDD DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD EEEEEE DEDU- Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-90
Figure 3-90: FFVE900 Package—XCKU13P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
18
16
4
2
5
3
20
0
17
35
34 28 33
29
29 29 29
29
29
29 29
29 29
29
26
29
26
26
26
26
2626
30
26
27
26 26
26 26
26 26
26 26
25 25
25
25
25
25 25
25
25 25
25
38
25
25
31
36
32 37
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
ug575_c3_100_030817
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVA1156 (XCKU11P)
X-Ref Target - Figure 3-91
Figure 3-91: FFVA1156 Package—XCKU11P I/O Bank Diagram
24 24
23
23
22 22
21
21
20 20
19 19
S
S18 1817 17
16
1615 15
14 14
13 13
12 12
11
11
10 10
99
8
8
7
7
S66
554
4
3
3
221
1
24
24
23
23
22
22
2121
2020
19
19
S
S
1818
17
17
1616
1515
1414
13
13
12
12 11
11
10
10 9
9
8
8
7
7
S66
5
5
4
4
3
3
2
2
1
1
24
24 23
23
2222
21
21
20
20
19
19
S
S
18
18
17
17
16
16
15
15
1414 13
13
1212
1111
10
10
9
9
8
8
77
S
6
6
5
5
4
4
3
3
2
2
1
1
24
24
23
23
2222
21
21
2020
1919
S
S
18
18
1717
1616
1515
14
141313
121211
11
10
109
9
88
7
7
S
665
5
443
3
22
11
24
24
23232222
21
21
20
20
19
19 S
S
18181717
16
16
15
15
141413
13
1212
1111 10
10
99
88
77
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23 23
22
22
21
21
20
20
19
19 S
S
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7S
6
6
5
5
4
4
3
3
2
2
1
1
2424
23
23
22
22
2121
2020
19
19
S
S
18
18 1717
1616
15
15
1414
13
13
12
12
1111
10
10
9
9887
7
S
6
6
5
544
33
221
1
24 24
23
2322 22
21
21
20 20
19 19S
S
18 18
17
17
16 16
15 15
14
14 13 13
12 12 11
11
10 109
9
8
8
7
7
S
66
55
443
3
2
2
1
1
12
12
11 11
10
10
9
9
8
8
7
7
66
55
4
4
3
3
2
2
1
1
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
11
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
G
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0228
0
1228
1
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
88
VCCO
88
VCCO
88
VCCO
89
VCCO
89
VCCO
89
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
ug575_c3_100_062217
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 88
Bank 89
Quad 129
Quad 130
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
(I XILINX¢ E I E l EDD l EDDDDIDDDD u DIDDDDDDD I D u u D l D. H DJIEDD fl IDDDDDDDDD l DDDDDDIDD DDUDDUDUU DDDDDDDDDDDDDDD DDDDDDDDDDDDDD I] B E E I! I D D D D I Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-92
Figure 3-92: FFVA1156 Package—XCKU11P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20 22
2124
23
2830
34
33
29
29
2929
2929
29
29
35
27
29
29 2929
2626
26
26
2626
26
26
26
26
2626
26
26
26
262525 25
25
38
25 25
25
25
252525
2525
3231 37
36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
n n n
n n n n n n n n
n n n n n n n n n n
n n n n n n n n n
n n n n n n n n
n n n n n n n nn
n n n n n n n n n
n n n n n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_062217
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Chapter 3: Device Diagrams
FFVA1156 (XCKU15P) and FFRA1156 (XQKU15P)
X-Ref Target - Figure 3-93
Figure 3-93: FFVA1156 Package—XCKU15P and FFRA1156 Package—XQKU15P
I/O Bank Diagram
24 24
23
23
22 22
21
21
20 20
19 19
S
S18 1817 17
16
1615 15
14 14
13 13
12 12
11
11
10 10
99
8
8
7
7
S66
554
4
3
3
221
1
24
24
23
23
22
22
2121
2020
19
19
S
S
1818
17
17
1616
1515
1414
13
13
12
12 11
11
10
10 9
9
8
8
7
7
S66
5
5
4
4
3
3
2
2
1
1
24
24 23
23
2222
21
21
20
20
19
19
S
S
18
18
17
17
16
16
15
15
1414 13
13
1212
1111
10
10
9
9
8
8
77
S
6
6
5
5
4
4
3
3
2
2
1
1
24
24
23
23
2222
21
21
2020
1919
S
S
18
18
1717
1616
1515
14
141313
121211
11
10
109
9
88
7
7
S
665
5
443
3
22
11
24
24
23
23
22
22
21
21
20
20
1919
S
S
18
181717
16
16
1515
141413
13
12
12
11
11
10
1099
887
7
S
6
6
55
44
33
22
1
1
24
24
23232222
21
21
20
20
19
19 S
S
18181717
16
16
15
15
141413
13
1212
1111 10
10
99
88
77
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23 23
22
22
21
21
20
20
19
19 S
S
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7S
6
6
5
5
4
4
3
3
2
2
1
1
2424
23
23
22
22
2121
2020
19
19
S
S
18
18 1717
1616
15
15
1414
13
13
12
12
1111
10
10
9
9887
7
S
6
6
5
544
33
221
1
24 24
23
2322 22
21
21
20 20
19 19S
S
18 18
17
17
16 16
15 15
14
14 13 13
12 12 11
11
10 109
9
8
8
7
7
S
66
55
443
3
2
2
1
1
12
12
11 11
10
10
9
9
8
8
7
7
66
55
4
4
3
3
2
2
1
1
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
11
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
G
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0228
0
1228
1
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
90
VCCO
90
VCCO
90
VCCO
91
VCCO
91
VCCO
91
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
UU
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 90
Bank 91
Quad 129
Quad 130
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-94
Figure 3-94: FFVA1156 Package—XCKU15P and FFRA1156 Package—XQKU15P
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
18
16
4
2
5
3
20
0
17
2830
34
33
29
29
2929
2929
29
29
35
27
29
29 2929
2626
26
26
2626
26
26
26
26
2626
26
26
26
262525 25
25
38
25 25
25
25
252525
2525
3231 37
36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
nn
n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
ug575_c3_100_030817
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVE1517 (XCKU11P)
X-Ref Target - Figure 3-95
Figure 3-95: FFVE1517 Package—XCKU11P I/O Bank Diagram
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 88
Bank 89
Bank 90
Bank 91
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_062217
24
24
23 23
22 22
21
21
20 20 19 19 S
S
18 18 17 17
16 16 15 15
14 14 13 13
12
12
11 11
10
109
9887
7S
66
5
5
44
3
3
2
2
11
2424
2323
22
22
21
2120
20 1919 S S
18
18
17
17
1616 15
151414
131312
12
11
1110
10
9
9
88
7
7
S
6655
4433
2211
242423
23
22
22
21
21
2020
19
19
S
S
181817
17
16
16
15
151414
1313
1212
11
11
10
10
9
9
88
77
S
66
5
5
4
4
33
2
2
11
24
24
2323
2222
21
21 20
20
19
19
S
S
18
18
17
17
1616
15
15
14
14
1313
1212
11
11
10
10
99
887
7
S
66
5
5
44
33
2
2
1
1
24
24
2323
22
22
2121
20
20
19
19
S
S
18
18
17
17 1616
15
15
14
14
13
13
12121111
1010
99
88
77
S6
6
5
5
4
4
33
2
2
1
1
24
24
2323
2222
21
21
20
20
1919
S
S
18
1817
17
16
16
1515
14
14
1313
12
12
1111
1010
9
9
88
77
S
66
5
5
4
4
3
3
2211
24 24
23
23
22
22
21 21
20
20
19 19
S
S
18
18
17 17
16
1615
15
14
14
13 13
12 12
11
11 10
10
9
9
8
8
7
7
S
66
554
4
33
2
2
11
24 24
23
23
22 22
21 21
20
20
19
19S
S
18 18
17 1716
16 15 15
14
14
13
13
12
12
11 11
10
10
99
8
8
77
S
6
6
55
443
32
2
1
1
12
12
11 11
10
109
98
8
77
6
6
554
433
2211
12 12
11 11
10
10
9
9
88
7
7
6655
4433
22
1
1
12
12
11
11
10
10
9
9
8877
6655
443
322
1
1
12
12
11 11
10 109
9887
76655
4
433
2
2
11
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
G
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0228
0
1228
1
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0229
0
1229
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0230
0
1230
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0231
0
1231
1
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
88
VCCO
88
VCCO
89
VCCO
89
VCCO
90
VCCO
90
VCCO
91
VCCO
91
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-96
Figure 3-96: FFVE1517 Package—XCKU11P Configuration/Power Diagram
ug575_c3_100_062217
0 R 2 3
4 5 6
8 7
910
11 12 13 14 15
16 17 18 19
20
22
2124
23
28 30
34
33
29
29
29 29
29
29
29 29
35
27
29
29
29 29
26
2626
26
26
26
26 26
26 26
26
26 26
26
26
26
25
25
25
25
3825
25 25
25 2525
25
25 25
32
31
37 36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
nn
nn
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVE1517 (XCKU15P) and FFRE1517 (XQKU15P)
X-Ref Target - Figure 3-97
Figure 3-97: FFVE1517 Package—XCKU15P and FFRE1517 Package—XQKU15P
I/O Bank Diagram
24
24
23 23
22 22
21
21
20 20 19 19 S
S
18 18 17 17
16 16 15 15
14 14 13 13
12
12
11 11
10
109
9887
7S
66
5
5
44
3
3
2
2
11
2424
2323
22
22
21
2120
20 1919 S S
18
18
17
17
1616 15
151414
131312
12
11
1110
10
9
9
88
7
7
S
6655
4433
2211
242423
23
22
22
21
21
2020
19
19
S
S
181817
17
16
16
15
151414
1313
1212
11
11
10
10
9
9
88
77
S
66
5
5
4
4
33
2
2
11
24
24
2323
2222
21
21 20
20
19
19
S
S
18
18
17
17
1616
15
15
14
14
1313
1212
11
11
10
10
99
887
7
S
66
5
5
44
33
2
2
1
1
24
24
2323
22
22
2121
20
20
19
19
S
S
18
18
17
17 1616
15
15
14
14
13
13
12121111
1010
99
88
77
S6
6
5
5
4
4
33
2
2
1
1
24
24
2323
2222
21
21
20
20
1919
S
S
18
1817
17
16
16
1515
14
14
1313
12
12
1111
1010
9
9
88
77
S
66
5
5
4
4
3
3
2211
24 24
23
23
22
22
21 21
20
20
19 19
S
S
18
18
17 17
16
1615
15
14
14
13 13
12 12
11
11 10
10
9
9
8
8
7
7
S
66
554
4
33
2
2
11
24 24
23
23
22 22
21 21
20
20
19
19S
S
18 18
17 1716
16 15 15
14
14
13
13
12
12
11 11
10
10
99
8
8
77
S
6
6
55
443
32
2
1
1
12
12
11 11
10
109
98
8
77
6
6
554
433
2211
12 12
11 11
10
10
9
9
88
7
7
6655
4433
22
1
1
12
12
11
11
10
10
9
9
8877
6655
443
322
1
1
12
12
11 11
10 109
9887
76655
4
433
2
2
11
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0
132
0
1
132
1
0
132
1
132
2
132
3
132
0
1
2
3
0
132
1
132
2
132
3
132
0
1
2
3
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
G
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0228
0
1228
1
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0229
0
1229
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0230
0
1230
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0231
0
1231
1
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
90
VCCO
90
VCCO
91
VCCO
91
VCCO
93
VCCO
93
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 90
Bank 91
Bank 93
Bank 94
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-98
Figure 3-98: FFVE1517 Package—XCKU15P and FFRE1517 Package—XQKU15P
Configuration/Power Diagram
0 R 2 3
4 5 6
8 7
910
11 12 13 14 15
16 17 18 19
20
22
2124
23
28 30
34
33
29
29
29 29
29
29
29 29
35
27
29
29
29 29
26
2626
26
26
26
26 26
26 26
26
26 26
26
26
26
25
25
25
25
3825
25 25
25 2525
25
25 25
32
31
37 36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
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Chapter 3: Device Diagrams
FFVA1760 (XCKU15P)
X-Ref Target - Figure 3-99
Figure 3-99: FFVA1760 Package—XCKU15P I/O Bank Diagram
24 24
23 2322
22 21
2120 20
19 19S
S
18 18
17
17
16 16
15
15
14 14
13
13
12
12
11
11
10 10
99
8
87
7
S
6
6
5
5
44
3
3
2
2
1
1
2424 2323
2222 21
212020
1919S
S
1818 1717
1616 15
1514
14
13
13
12
12
11
11
10
10 9
988
77S
66
5
54
433
2
2
11
2424
2323
22
22
2121
2020
1919
S
S
1818
1717
1616
1515
14
14
1313
12
12
1111
1010
99
8
8
7
7
S66
5
5
44
3
3
2
2
1
1
2424
23
23 22
22
21
21
20
20
19
19
S
S
1818
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
99
8
8
77
S
66
5
5
4
4
3
32
211
2424
2323
2222
2121 20
20
19
19
S
S
18
18
1717
16
16
1515
1414
1313
1212
11
11
10
10
9
98
8
77
S
66
5
5
44
332
2
11
24
24
23 23
22
22
21 21
20
20
19 19
S S
18
18
17 17
16
16
15
15
14 14
13
13
12 12
11 11
10
10
9
988
77
S
66
5
5
44
33
22
1
1
24
24
2323
22
22
2121
20
20
1919
S
S
18
1817
17 1616
15
15
1414
1313
12
12
1111
10109
9
88
77S
66
5
5
4
4
33
22
11
24 24
23
23
22
22 21
21
20
20 19
19
S
S
18 18
17 17
16
16
15
15
14
14
13
13
12
12
11
1110
10
998
87
7
S
6655
44
33
2
2
11
12 1211
11
10 10
99
8
877
6
6
5
5
443
3
221
1
12 12
11 11
10
10
9988
7
76
6
5
5
443
32
211
12
12
11 11
10
10
99
887
7
6655
4
433
2
2
11
12
12
11
11
10
10
9
9
8
8
7
7
66
5
5
4
4
3
32
2
11
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0 1
2
3
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
12
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
01
2
3
0
132
0
1
132
1
0
132
1
132
2
132
3
132
0
1
2
3
0
132
1
132
2
132
3
132
0
1
23
0
133
0
1
133
1
0
133
1
133
2
133
3
133
0
1
2
3
0
133
1
133
2
133
3
133
0
1
2
3
0
134
0
1
134
1
0
134
1
134
2
134
3
134
0
1
2
3
0
134
1
134
2
134
3
134
01
2
3
0224
1224
2224
3224
0
1
23
0
224
1
224
2
224
3
224
0
12
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
30
225
1
225
2
225
3
225
01
2
3
0225
0
1225
1
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
23
0226
0
1226
1G
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0228
0
1228
1
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0229
0
1229
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0230
0
1230
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0231
0
1231
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
0232
0
1232
1
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1
2 3
0233
0
1233
1
0234
1234 2234
3234
0
1 2
3
0
234
1
234
2
234
3
234
0
1 2
3
0234
0
1234
1
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
90
VCCO
90
VCCO
91
VCCO
91
VCCO
93
VCCO
93
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Bank 90
Bank 91
Bank 93
Bank 94
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 134
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
Quad 234
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-100
Figure 3-100: FFVA1760 Package—XCKU15P Configuration/Power Diagram
0
R
2
3
4 5 6
8 7
9
101112
13
14
15
16
17
18
19
20
22
2124
23
28
30
3433
29
29
2929
29
29
2929
35
27
29
2929
29 2626
26
26
2626
2626
26
26
2626
262626
26
2525
2525 38 25
2525
25
25
25
25
2525
3231
3736
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V V
V
V V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
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36
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41
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42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
ug575_c3_100_030817
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FFVE1760 (XCKU15P)
X-Ref Target - Figure 3-101
Figure 3-101: FFVE1760 Package—XCKU15P I/O Bank Diagram
24
24
23 23
22 22
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20 20
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19
S
S
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15 15
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11 10
109
9
88
77
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11
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21 21
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S
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10 10
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7
S
6
6
55
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4
3
3
22
1
1
2424
2323
2222 21
21
2020
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19
S
S1818
17
17
16
161515
1414 13
1312
12 1111
10
10
998
8
7
7
S
6
65
5
4
4
33
22
11
2424
23
23
2222
2121
20
20
1919
S
S
18
18
1717 16
1615
15
14
141313
1212
1111 1010
9
9
8
877
S6
6
5
5
4
4
3
3
2
21
1
24
24 23
23
2222
2121
20
20
1919SS
181817
17 1616
15
15
141413
13
1212
11
1110
10
9
98
8
7
7S
6
6
55
4
4
3322
1
1
2424
2323
22
22
2121
20
20 19
19
S
S
1818
17
17
16
16
15
15
14
1413
13
12
1211
11
1010
9
9
8
8
7
7
S
6
6
55
4
43
3
2
2
1
1
24
24 23
23
22
22 21
21
2020 19
19
S
S
18
18 17
17
16
16
1515
14
14 13
13
12
1211
11
10
10
99
88
77
S
6
6
55
4
4
33
22
1
1
24
24
2323
2222
2121
20
20 19
19 S
S
1818
17
17
16
16
15
15
1414
1313
12
121111
10
10
99
8
8
7
7
S
6
6
55
4
43
3
22
1
1
24 24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17 17
16 16
15
15 14
14
13
13
12 12
11
11
10
10
99
88
7
7S
66
55
4
4
33
221
1
24
24
23
23 22 22
21 21
20
2019 19
S
S
18
18
17
17
16 16
15
1514 14
13 13
12 12
11
1110
10
9
9
8
87
7
S
66
55
4
4
3
3
22
1
1
2424
23
23
22
22
2121
20
20
1919
SS
18
18
17
1716
16
1515
1414
13
13
1212
1111
1010
9
9
8
8
77
S
6
6
55
4
43
3
22
1
1
12
1211
11
10
10
9
98
877
6
65
5
4
4
3
3
2
2
11
12 1211
1110 10
99
887
76
655
44
33
2
2
11
12 12
11
11 10
10
9
9
887
7
6
6
5
5
4
4
3
3
2
2
1
1
12
12
11 11
10 10
99
887
7
6
6
55
4
43
32
211
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0
132
0
1
132
1
0
132
1
132
2
132
3
132
0
1
2
3
0
132
1
132
2
132
3
132
0
1
2
3
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
G
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0228
0
1228
1
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0229
0
1229
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0230
0
1230
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0231
0
1231
1
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
VCCO
90
VCCO
90
VCCO
91
VCCO
91
VCCO
93
VCCO
93
VCCO
94
VCCO
94
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
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17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
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30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Bank 90
Bank 91
Bank 93
Bank 94
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-102
Figure 3-102: FFVE1760 Package—XCKU15P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
28
30
34
33 29 29
29 29
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2929 29
35
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29
26 26
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2626 26
26 26
26 26
26
2626
26
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26
25
25 25
25
38
2525 25
25 25
25
25
25
25
32 31
37
36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
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8
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31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
A A
B B
C C
D D
E E
F F
G G
H H
JJ
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
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Chapter 3: Device Diagrams
FFVC1517 (XCVU3P) and FFRC1517 (XQVU3P)
X-Ref Target - Figure 3-103
Figure 3-103: FFVC1517 Package—XCVU3P and FFRC1517 Package—XQVU3P I/O Bank Diagram
24
24
23
23
22
22 21
21
20 20
19
19
S
S
18
18
17 1716
16
15 15
14 14
13 13
12
1211
11 10 10
9
9
8
8
7
7
S
6
655
44
3
3221
1
24 24
23
23
22
22 21
21
20
20
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19
S
S
18
18
17
17
16
16
15
15 14
14
13
13
12 12
11
11
10
10
99
887
7
S66
554
4332
211
24 2423
23
22
2221
21
20 20
19 19
S
S
18 18
17
17 16 16
15 15
14 14
13 13
12 12
11 11
10
10
9
9
8
8
7
7
S
6
65
5
4
4
332
2
1
1
24
24
23
23
2222
21
21
2020
1919
S
S
1818 17
17
1616
15
15
1414
1313
1212
1111
10
10
998
8
77S
665
5
4
43
3
22
11
24
24
2323
22
2221
21 2020
19
19
S
S18
18
17
17
16
16
1515
14
14 1313
12
1211
1110
10
99
88
77
S
66
5
5
44
3
3
22
11
24
24
23 23
22
22
21
2120
20
19
19
S
S18 18
17
17
16 16
15
15
14 14
13 13
12 12
11 1110
10
9
9
8
877
S
6
6
5
5
4
4
3
3
2
2
1
1
24 2423
23 22
22
21
21
20 20
19
19
S
S18
18
17
17
16
16 15
15
14 14
13
13
12
12
11
11
10
10
9
9
8
8
77S
6
6
55
44
33
2
2
1
1
24 24
23 23
22 22
21
21
20
20
19
19
SS
18 18
17
17
16
16
15 15
14 14
13
13
12
12
11
11
10
10
9
9
88
7
7
S
6
6
5
54
4
3
3
22
11
2424
23
23 22
22
21
21
202019
19
S
S
18
18
1717
1616
15
15
14
14
13
13
1212
1111
10
10 99
887
7S
6
6
5
5
4
4
3
3
22
11
2424 23
23
2222
21
21
2020
1919
S
S
1818
17
17
16
16
1515 14
14
13
13
1212
1111
10109
9
88
7
7
S
6
6
55
44
3
3
221
1
3
3
3
124
3
124
1
1
124
2
2
2
124
2
124
11
1
124
1
124
0
0
124
0
0
0
124
0
124
3
3
3
125
3
125
1
1
125
2
2
2
125
2
125
1
1
1
125
1
125
0
0
125
0
0
0
125
0
125
3
3
3
126
3
126
1
1
126
2
2
2
126
2
126
G
V
1
1
1
126
1
126
0
0
126
0
0
0
126
0
126
3
3
3
127
3
127
1
1
127
2
2
2
127
2
127
1
1
1
127
1
127
0
0
127
0
0
0
127
0
127
3
3
3
128
3
128
1
1
128
22
2
128
2
128
1
1
1
128
1
128
0
0
128
0
0
0
128
0
128
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
1
1
2
2
3
3
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
MM
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
Bank 44
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-104
Figure 3-104: FFVC1517 Package—XCVU3P and FFRC1517 Package—XQVU3P
Configuration/Power Diagram
8 7
23
24 21
22
1011
9
12
R
15
13
6
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4
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5
320
0
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2830
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26 2626
252525
25 38
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3231
3736
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
1
1
2
2
3
3
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39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLGF1924 (XCVU11P)
X-Ref Target - Figure 3-105
Figure 3-105: FLGF1924 Package—XCVU11P I/O Bank Diagram
24 2423
23 22
22
21
21
20 20
19
19
S
S
18
18 17
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15
14 14
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12 12
11 11
10 10
9
9
88
77
S
665
5
4
4
33
2
2
1
1
24
24
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23
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22
21 21
20 20
19 19
S
S
18 18 17 17
16 16
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1110
10
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S
665
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44
33
2
2
1
1
242423
23
22
22
21
21
20
2019
19
S
S
18
1817
17
16
1615
15
141413
13
1212
1111
10
10 9
9
8
8
7
7
S
66
5544
3
3
2
211
2424
23
23 2222
2121 20
20
19
19S
S18
18 17
17
16
16 1515
14
14
13
13
1212
1111
10
10
99
8
8
77
S
6
6
5
5
44
3
3
2
2
1
1
24
24
23
23
2222 21
212020
1919
S
S
18
18
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17
16
16 15
1514
14
13
13 12
121111
10
10
998
8
7
7S
66
55
4
4
33
2
2
11
2424 23
23 2222
21
21
20
20 19
19S
S
18
18
17
17
16
16
15
15
1414 13
13
1212
1111
10
10 9
9
8
87
7
S66
5
5
4
43
32
2
1124
2423
23
22
22
21
21
2020
19
19
S
S
18
18
17
17
16
16
15
15
141413
1312
12
11
11
10
10
9
988
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7
S
66
55
4
4
33
2
2
1
1
24 24
23
23
22 22
21
21
20 20
19 19
S
S
18
18
17
17
16
16
15
15
14 14
13
13
12 12
11 11
10
10
9
98
8
77
S
66
5
5
4
4
3
3
22
1
1
24 24
23
23
22 22
21
21
20
20
19 19
S
S
18
18
17
17
16
16
15
15
14 14
13 13
12
12 11 11
10 10 9
98
8
7
7
S
6
6
5
5
4
4
3
3
22
11
2424 23
2322
22 21
21
2020
19
19S
S
1818
1717
16
16
15
15
1414
1313
1212 11
1110
10 9
9
88
77
S
6
6
5
5
4
4
3
3
2
2
1
1
24
24 23
2322
22 21 21
20
20
19
19
S
S
18 18
17 17
16
16
15
15
14 14
13 13
12
12
11
11
10 10
9
9
8
8
7
7
S
66
5
544
332
21
1
24 24
23
23
22 22
21 21
20 20
19 19
S
S18
18
17 17
16
16
15 15
14 14
13
13
12
12 11 11
10
10
99
8877
S
6
6554
4
3
3
22
11
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
125
0
1
125
1
G
V
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
126
0
1
126
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
127
0
1
127
1
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
129
0
1
129
1
G
V
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
130
0
1
130
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0
131
0
1
131
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0224
0
1224
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0225
0
1225
1
G
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0226
0
1226
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0227
0
1227
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0228
0
1228
1
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0229
0
1229
1
G
V
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0230
0
1230
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0231
0
1231
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
0232
0
1232
1
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1
2
3
0233
0
1233
1
G
V
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
GG
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Bank 75
Quad 125
Quad 126
Quad 127
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-106
Figure 3-106: FLGF1924 Package—XCVU11P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19 18
16
4
2
5
3
200
17
283034
33
29
29
29
29
29
2929
29
35
27
29
2929
29
26
2626
26
262626
26
2626
2626
26
26 26
26
25
25
25
25
38
25
2525
25252525
25
25
32
31 3736
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
EE
E
EE
EE
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
EE
EE
E E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V
V
V
V
V
V
V
V
V
n
n
nn
n
n
n
n
nn
nnnn
n
n
nn
nn
n
n
nn
n
n
nn
nn
nn
n
n
nn
n
n n
n
nn n
nn
n n
n
n
n
n
nn
n
n
n
n
n
n
n
n
n
n
n
nnnn
n
n
n
n nn
nn
n
n n
n
nn
n
nn
n
n
nnn
n
n
nn
n
n
n
nn
n
n
n
nn
nn
nn
n
n
n
n
n
n
n
n
n
n
n
n
1
1
2
2
3
3
4
4
5
5
6
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25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
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Chapter 3: Device Diagrams
FSVH1924 (XCVU31P)
X-Ref Target - Figure 3-107
Figure 3-107: FSVH1924 Package—XCVU31P I/O Bank Diagram
24 24
23
23
22 2221
21
20 2019 19
SS
18 18
17
17
16
16
15
15
14
14
13 13
12 12
11 11
10 10
99
887
7
S66
5
5
44
3322
1
1
2424
23
232222 2121
2020
1919
S S
18
18 1717
1616
1515
14
14
13
13
1212
1111
1010
99
88
77
S
6
6
55
44
3
3
2
2
1124
24 23
23
2222 21
21
20
20 19
19S S
18
18
17
1716
16 15
15
1414
1313
1212 11
11
1010
99
88
77
S
6
6
5
5
443
322
11
24 2423 23
22 22
21 21
20 20
19
19
S
S18
1817 17
16
16
15 15
14 1413 13
12 12
11 11 10
10
9
9
88
7
7S
66
5
5
4
4
33
22
11
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
V
0
125
0
1
125
1
G
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
GG
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
Bank 64
Bank 65
Bank 66
Bank 67
Quad 124
Quad 125
Quad 126
Quad 127
Quad 224
Quad 225
Quad 226
Quad 227
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_031518
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-108
Figure 3-108: FSVH1924 Package—XCVU31P Configuration/Power Diagram
0
R
23
45
6
8 7
9
10
11
12
13
14
15
1617
18 19
20
22
2124
23
28
30 34
33
2929 29
29
29
29 29
2935 27
29
29
29
2926
26 26
26
2626
2626
2626 26
26
2626
2626
2525
2525
38
2525
25
25
25
2525 25
253231
3736
r
rr
r
r
r
r
r
r r
rr
r
Rr
rrr
rr
rr
rrr
r
r
r
rrr
rr
rr
rrr
r r HBM
AUX
HBM
AUX
HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
E
E
E
E
E
E
E
E
E
E
V V
V
V
V
V
V V
V V
V
V
V
V
V V
V
V
V
V
n n n n n n n
n n n n n n
n n n n n n n
n n n n n n
n n n n n n n
n n n n n n
n n n n n n n
n n n n n n n nn
n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n n n n nn
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n nn n nn n n n n
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n nn n nn n n n n
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n nn n nn n n n n
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n nn n nn n n n n
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n nn n nn n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
ug575_c3_031518
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
r RSVD
R RSVDGND
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
HBM
AUX VCCAUX_HBM
HBM
VCC VCC_HBM
HBM
IO VCC_IO_HBM
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLVA2104 (XCVU5P and XCVU7P) and FLRA2104
(XQVU7P)
X-Ref Target - Figure 3-109
Figure 3-109: FLVA2104 Package—XCVU5P and XCVU7P and FLRA2104 Package—XQVU7P
I/O Bank Diagram
2424
23
23
22
22
2121
2020
19
19
S
S
1818
1717
1616
15
15
14
14
13
13
1212
11
11
10
10 9
9
88
77
S
6
6
55
44
3
3
22
1
1
2424
2323
2222
21
21
2020
1919
S
S1818 17
17
1616 1515
1414
13
13
12
12
1111
10
10
9
9
8
8
7
7
S
66
5
5
4
4
33
2
2
1
1
24
24
2323
22
22
2121
20
20
1919
S
S
18
18
1717
1616
15
1514
14
1313
12
12
1111
10
10
9
9
88
7
7
S
66
5
5
4
43
3
221
1
2424
23
23 2222
2121 20
20
19
19S
S18
18 17
17
16
16 1515
14
14
13
13
1212
1111
10
10
99
8
8
77
S
6
6
5
5
44
3
3
2
2
1
1
24 24
23 23
22 22
21
21
20
20
19
19
S
S
18
18
17
17
16
16
15 15
14
14
13
13
12 12
11 11
10 10
9
98
8
77
S
6
6
5
54
4
3
3
2
2
1
1
24 24 23
23 22 22
21
21 20
20
19 19
S
S
18 18
17 17
16 16
15
15
14 14
13
13
12 12
11
11
10 10
9988
77
S6
6
5
54
43
3
22
1
1
24 24
23 23
22 22
21
2120 20
19 19
S
S
18 18
17
17
16 16
15
15
14 14
13 13
12
12
11
11
10
10
9
9
8
8
7
7S
665
5
44
3
3
221
1
24
24
23
23
22 22
21
21 20 20
19 19
S
S18
1817 17
16
16
15
15
14
1413
13
12 12
11 11
10
10 9
9
88
77S
6
6
55
4
43
32
2
1
1
24
24
2323
22
22 21
21
20
20
19
19
S
S
18
18
1717
16
16
15
15
14
14
13
13
12
12
11
11
1010
9
98
877
S
6
6
5
5
4
43
32
2
1
1
24
24
23
23
2222 21
212020
1919
S
S
18
18
17
17
16
16 15
1514
14
13
13 12
121111
10
10
998
8
7
7S
66
55
4
4
33
2
2
11
2424 23
23 2222
21
21
20
20
19
19S
S
18
18
17
17
1616
15
15
1414
13
13
1212
1111
10
10 9
9
8
8
7
7
S
66
5
5
4
4
3
3
22
11
24
2423
23
22
22
21
21
2020
19
19
S
S
18
18
17
17
16
16
15
15
141413
1312
12
11
11
10
10
9
9
88
77
S
66
55
4
4
3
3
2
2
1
1
24
24
23 23
22 22
21 2120
20
19 19
S
S
18
18
17
17
16
16
15 15
14 14
13 13
12 1211
11 10
109
9
8
8
7
7
S
6
655
44
33
2
211
24
24 23 23
22
22
21 21
20 20
19
19
S
S
18 18
17
17
16
16
15 15
14 14
13 13
12
12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
21
1
24 24
23 23
22 22 21 21
20
20
19
19
S S
18 18
17
17
16
16
15
15
14
14
13
13
12
1211
11
10 10
99
8
8
77
S
6
6
5
5
44
33
2
2
11
24
24 23 23
22
22
21
21
20 20
19 19
S
S
18
18
17
17
16
16
15
1514
14
13 13
12
12
11
1110
10
99
8
8
7
7
S
6
6
5
5
4
43
3
2
2
1
1
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
V
G
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
130
3
3
3
130
1
130
1
2
130
2
2
2
130
1
130
1
1
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
V
G
1
131
1
1
1
131
0
131
0
0
131
0
0
0
131
3
132
3
3
3
132
1
132
1
2
132
2
2
2
132
1
132
1
1
1
132
0
132
0
0
132
0
0
0
132
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
53
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
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17
18
18
19
19
20
20
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24
24
25
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27
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28
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30
30
31
31
32
32
33
33
34
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36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 44
Bank 45
Bank 46
Bank 47
Bank 50
Bank 51
Bank 52
Bank 53
Bank 64
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 72
Bank 73
Quad 125
Quad 126
Quad 127
Quad 130
Quad 131
Quad 132
Quad 224
Quad 225
Quad 226
Quad 227
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-110
Figure 3-110: FLVA2104 Package—XCVU5P and XCVU7P and FLRA2104 Package—XQVU7P
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19 18
16
4
2
5
3
200
17
28 30
34 33
29 29
29
2929 29
29 29
35
27
29 29
29
29
26 26
26
26
26 26
26 26
26
26
26
26
26
26
26
26
25
25
25
2538
25
25 25 25
25
25 25
25
25
32 31 37
36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_100_030817
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
(I XILINX¢ gunman: nanu»»»» Send Feed back mum:H unwmmwm m -» f u u I- "x“ OQOOOQ I ®DD E I 5 HEW” 000006 u.....”.”mw..m:m mm mall I ........ .........:......m
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Chapter 3: Device Diagrams
FLGA2104 (XCVU9P)
X-Ref Target - Figure 3-111
Figure 3-111: FLGA2104 Package—XCVU9P I/O Bank Diagram
24
24
2323
22
22 21
21
20
20
19
19
S
S
18
18
1717
16
16
15
15
14
14
13
13
12
12
11
11
1010
9
98
877
S
6
6
5
5
4
43
32
2
1
1
24
24
23
23
2222 21
212020
1919
S
S
18
18
17
17
16
16 15
1514
14
13
13 12
121111
10
10
998
8
7
7S
66
55
4
4
33
2
2
11
2424 23
23 2222
21
21
20
20
19
19S
S
18
18
17
17
1616
15
15
1414
13
13
1212
1111
10
10 9
9
8
8
7
7
S
66
5
5
4
4
3
3
22
11
24
2423
23
22
22
21
21
2020
19
19
S
S
18
18
17
17
16
16
15
15
141413
1312
12
11
11
10
10
9
9
88
77
S
66
55
4
4
3
3
2
2
1
1
24 24
23 23
22 22
21
21
20
20
19
19
S
S
18
18
17
17
16
16
15 15
14
14
13
13
12 12
11 11
10 10
9
98
8
77
S
6
6
5
54
4
3
3
2
2
1
1
24 24 23
23 22 22
21
21 20
20
19 19
S
S
18 18
17 17
16 16
15
15
14 14
13
13
12 12
11
11
10 10
9988
77
S6
6
5
54
43
3
22
1
1
24 24
23 23
22 22
21
2120 20
19 19
S
S
18 18
17
17
16 16
15
15
14 14
13 13
12
12
11
11
10
10
9
9
8
8
7
7S
665
5
44
3
3
221
1
24
24
23
23
22 22
21
21 20 20
19 19
S
S18
1817 17
16
16
15
15
14
1413
13
12 12
11 11
10
10 9
9
88
77S
6
6
55
4
43
32
2
1
1
2424
23
23
22
22
2121
2020
19
19
S
S
1818
1717
1616
15
15
14
14
13
13
1212
11
11
10
10 9
9
88
77
S
6
6
55
44
3
3
22
1
1
2424
2323
2222
21
21
2020
1919
S
S1818 17
17
1616 1515
1414
13
13
12
12
1111
10
10
9
9
8
8
7
7
S
66
5
5
4
4
33
2
2
1
1
24
24
2323
22
22
2121
20
20
1919
S
S
18
18
1717
1616
15
1514
14
1313
12
12
1111
10
10
9
9
88
7
7
S
66
5
5
4
43
3
221
1
2424
23
23 2222
2121 20
20
19
19S
S18
18 17
17
16
16 1515
14
14
13
13
1212
1111
10
10
99
8
8
77
S
6
6
5
5
44
3
3
2
2
1
1
24
24
23 23
22 22
21 2120
20
19 19
S
S
18
18
17
17
16
16
15 15
14 14
13 13
12 1211
11 10
109
9
8
8
7
7
S
6
655
44
33
2
211
24
24 23 23
22
22
21 21
20 20
19
19
S
S
18 18
17
17
16
16
15 15
14 14
13 13
12
12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
21
1
24 24
23 23
22 22 21 21
20
20
19
19
S S
18 18
17
17
16
16
15
15
14
14
13
13
12
1211
11
10 10
99
8
8
77
S
6
6
5
5
44
33
2
2
11
24
24 23 23
22
22
21
21
20 20
19 19
S
S
18
18
17
17
16
16
15
1514
14
13 13
12
12
11
1110
10
99
8
8
7
7
S
6
6
5
5
4
43
3
2
2
1
1
3
120
3
3
3
120
1
120
1
2
120
2
2
2
120
1
120
1
1
1
120
0
120
0
0
120
0
0
0
120
3
121
3
3
3
121
1
121
1
2
121
2
2
2
121
V
G
1
121
1
1
1
121
0
121
0
0
121
0
0
0
121
3
122
3
3
3
122
1
122
1
2
122
2
2
2
122
1
122
1
1
1
122
0
122
0
0
122
0
0
0
122
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
1
125
1
1
1
125
0
125
0
0
125
00
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
V
G
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
41
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
42
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
43
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
48
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 40
Bank 41
Bank 42
Bank 43
Bank 45
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 72
Bank 73
Quad 120
Quad 121
Quad 122
Quad 125
Quad 126
Quad 127
Quad 224
Quad 225
Quad 226
Quad 227
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
{I XILINX¢ DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD I EEEEE Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-112
Figure 3-112: FLGA2104 Package—XCVU9P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19 18
16
4
2
5
3
200
17
28 30
34 33
29 29
29
2929 29
29 29
35
27
29 29
29
29
26 26
26
26
26 26
26 26
26
26
26
26
26
26
26
26
25
25
25
2538
25
25 25 25
25
25 25
25
25
32 31 37
36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
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15
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22
22
23
23
24
24
25
25
26
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30
30
31
31
32
32
33
33
34
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35
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36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
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44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
(I XILINX¢ unmmuum unnumumu mummu“ Hunnumm Nlu I Send Feedback u 090099 ®_H=H_ 000009 9mmmm ”waus EJHEEEE
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Chapter 3: Device Diagrams
FHGA2104 (XCVU13P)
X-Ref Target - Figure 3-113
Figure 3-113: FHGA2104 Package—XCVU13P I/O Bank Diagram
24 24
23 23
22 22
21
21
20
20
19
19
S
S
18
18
17
17
16
16
15 15
14
14
13
13
12 12
11 11
10 10
9
98
8
77
S
6
6
5
54
4
3
3
2
2
1
1
24 24 23
23 22 22
21
21 20
20
19 19
S
S
18 18
17 17
16 16
15
15
14 14
13
13
12 12
11
11
10 10
9988
77
S6
6
5
54
43
3
22
1
1
24 24
23 23
22 22
21
2120 20
19 19
S
S
18 18
17
17
16 16
15
15
14 14
13 13
12
12
11
11
10
10
9
9
8
8
7
7S
665
5
44
3
3
221
1
24
24
23
23
22 22
21
21 20 20
19 19
S
S18
1817 17
16
16
15
15
14
1413
13
12 12
11 11
10
10 9
9
88
77S
6
6
55
4
43
32
2
1
1
2424
23
23
22
22
2121
2020
19
19
S
S
1818
1717
1616
15
15
14
14
13
13
1212
11
11
10
10 9
9
88
77
S
6
6
55
44
3
3
22
1
1
2424
2323
2222
21
21
2020
1919
S
S1818 17
17
1616 1515
1414
13
13
12
12
1111
10
10
9
9
8
8
7
7
S
66
5
5
4
4
33
2
2
1
1
24
24
2323
22
22
2121
20
20
1919
S
S
18
18
1717
1616
15
1514
14
1313
12
12
1111
10
10
9
9
88
7
7
S
66
5
5
4
43
3
221
1
2424
23
23 2222
2121 20
20
19
19S
S18
18 17
17
16
16 1515
14
14
13
13
1212
1111
10
10
99
8
8
77
S
6
6
5
5
44
3
3
2
2
1
1
24
24
2323
22
22 21
21
20
20
19
19
S
S
18
18
1717
16
16
15
15
14
14
13
13
12
12
11
11
1010
9
98
877
S
6
6
5
5
4
43
32
2
1
1
24
24
23
23
2222 21
212020
1919
S
S
18
18
17
17
16
16 15
1514
14
13
13 12
121111
10
10
998
8
7
7S
66
55
4
4
33
2
2
11
2424 23
23 2222
21
21
20
20
19
19S
S
18
18
17
17
1616
15
15
1414
13
13
1212
1111
10
10 9
9
8
8
7
7
S
66
5
5
4
4
3
3
22
11
24
2423
23
22
22
21
21
2020
19
19
S
S
18
18
17
17
16
16
15
15
141413
1312
12
11
11
10
10
9
9
88
77
S
66
55
4
4
3
3
2
2
1
1
24
24
23 23
22 22
21 2120
20
19 19
S
S
18
18
17
17
16
16
15 15
14 14
13 13
12 1211
11 10
109
9
8
8
7
7
S
6
655
44
33
2
211
24
24 23 23
22
22
21 21
20 20
19
19
S
S
18 18
17
17
16
16
15 15
14 14
13 13
12
12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
21
1
24 24
23 23
22 22 21 21
20
20
19
19
S S
18 18
17
17
16
16
15
15
14
14
13
13
12
1211
11
10 10
99
8
8
77
S
6
6
5
5
44
33
2
2
11
24
24 23 23
22
22
21
21
20 20
19 19
S
S
18
18
17
17
16
16
15
1514
14
13 13
12
12
11
1110
10
99
8
8
7
7
S
6
6
5
5
4
43
3
2
2
1
1
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
V
G
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
3
3
3
126
1
126
1
2
126
2
2
2
126
1
126
1
1
1
126
0
126
0
0
126
0
0
0
126
3
127
3
3
3
127
1
127
1
2
127
2
2
2
127
1
127
1
1
1
127
0
127
0
0
127
0
0
0
127
3
129
3
3
3
129
1
129
1
2
129
2
2
2
129
V
G
1
129
1
1
1
129
0
129
0
0
129
00
0
129
3
130
3
3
3
130
1
130
1
2
130
2
2
2
130
1
130
1
1
1
130
0
130
0
0
130
0
0
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
1
131
1
1
1
131
0
131
0
0
131
0
0
0
131
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3229
3
229
1
1229
2
2
2229
2
229
G
V
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
60
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 60
Bank 61
Bank 62
Bank 63
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Bank 75
Quad 125
Quad 126
Quad 127
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-114
Figure 3-114: FHGA2104 Package—XCVU13P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19 18
16
4
2
5
3
200
17
28 30
34 33
29 29
29
2929 29
29 29
35
27
29 29
29
29
26 26
26
26
26 26
26 26
26
26
26
26
26
26
26
26
25
25
25
2538
25
25 25 25
25
25 25
25
25
32 31 37
36
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_062217
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Chapter 3: Device Diagrams
FLVB2104 (XCVU5P and XCVU7P) and FLRB2104
(XQVU7P)
X-Ref Target - Figure 3-115
Figure 3-115: FLVB2104 Package—XCVU5P and XCVU7P and FLRB2104 Package—XQVU7P
I/O Bank Diagram
2424
232322
22
21
21
20
201919
S
S18
181717
16
16
15
15 14
14
1313
1212
1111
1010
9
9
8
8
7
7
S6
6
55
44
33
2
2
1
1
24
24
23
23
2222
21
21
20
20
1919
S
S
18
18
17
17
1616
15
15 1414
13
13
12
12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
2
11
2424
23
232222
21
21
20
20
19
19
S
S1818
1717
16
16
15
15
14
14
1313
1212
11
11
10
10
9
9
88
77S
6
6
5
544
3
322
11
12 12
11
1110
10
99
88
77
S66
5
544
332
2
1
1
24
24
23
23
22
22
21 21
20 20
19 19
S S
18
1817
17
16
16
15
15
14 1413 13
12
12
11 11
10 10
9988
7
7
S
66
55
4
4
3
3
2
2
11
24
24
23
23
22
22
21
21
20
2019 19
S
S
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
S
6
6
5
5
4
4
3
3
221
1
2424
23
23
22
2221
21
20
20
1919
S
S
18
18
17
17
16
16
1515
1414
13
13
12
12
111110
10
99
887
7
S66
5
54
4
3
3
2
2
11
24
24
23
23
22
22
21
21
20
2019 19
S
S
18
1817
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
2
11
24
24
23
23
2222
21
21
20
20
19
19 S
S
18
1817
17 1616
15
15
1414
13
13 1212
1111
1010
9
9
8
87
7S
6
6
5
5
4
4
3
3
2
2
1
1
24
24
23
23
2222
21
21
20
20
19
19S
S
18
18
17
17 1616
1515
14
14
1313 1212
11
11
10
10
9
9
8
8
7
7
S66
5
5
4
4
33
2
2
11
24
24
23
23
22
22
21
21
20
20
19
19
S
S18
18
17
17
16
16
15
15
14
14
1313
121211
11
10
10
9
9
88
7
7
S
6
65
544
3
3
2
21
1
24
24
23
23
22 22
21
2120 20
19
19
S
S
18
18
17 17
16 16
15
15
14 14
13 13
12
12
11
11 10
109
9
8
877
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23
23
22
22
21
21
20 20
19
19
S
S
18 18
17 1716 16
15 15
14 14
13 13
12 1211
11
10
10
9
988
7
7
S
6
6
5
5
4
4
33
2
2
1
1
24
2423
23
22
22
21 21
20
2019
19
S
S18
18
17
17
16 16
15
15 14
14
13
13
12 12
11
11
10 109
9
887
7S
6
6
5
5
4
4
3
3
2
2
1
1
3
125
3
3
3
125
1
125
1
2
125
2
2
2
125
1
125
1
1
1
125
0
125
0
0
125
0
0
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
V
G
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
0
0
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
33
3
131
1
131
1
2
131
22
2
131
V
G
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
11
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
44
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
45
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
46
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
50
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
51
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
52
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 44
Bank 45
Bank 46
Bank 50
Bank 51
Bank 52
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
{I XILINX¢ ID DIDDDDEDDDDIDDDD DDDBDDDBIDDDDBDD EDDDDIDDDDEDDDDI DDIDDDDEDDDDIDDD u l u u l DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD IDDDDI Send Feed back
UltraScale Device Packaging and Pinouts 298
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-116
Figure 3-116: FLVB2104 Package—XCVU5P and XCVU7P and FLRB2104 Package—XQVU7P
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
18
16
4
2
5
3
200
17
2830
34
33
29
2929
29
29
29
2929
35
27
29
29
29
29
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2626
2626
26
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26
262626
26
2626
252525
25
38
25
2525
25
25 25
25
25
25
32
31
3736
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
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12
13
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15
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17
17
18
18
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21
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22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
(I XILINX¢ HI 11 11 "I an PE II II .I Q9 ages 69 k 1 69 e999 Q9 000000 DD® 006900 Send Feed back
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Chapter 3: Device Diagrams
FLGB2104 (XCVU9P)
X-Ref Target - Figure 3-117
Figure 3-117: FLGB2104 Package—XCVU9P I/O Bank Diagram
24
24
23
23
2222
21
21
20
20
19
19 S
S
18
1817
17 1616
15
15
1414
13
13 1212
1111
1010
9
9
8
87
7S
6
6
5
5
4
4
3
3
2
2
1
1
24
24
23
23
2222
21
21
20
20
19
19S
S
18
18
17
17 1616
1515
14
14
1313 1212
11
11
10
10
9
9
8
8
7
7
S66
5
5
4
4
33
2
2
11
24
24
23
23
22
22
21
21
20
20
19
19
S
S18
18
17
17
16
16
15
15
14
14
1313
121211
11
10
10
9
9
88
7
7
S
6
65
544
3
3
2
21
1
12 12
11
1110
10
99
88
77
S66
5
544
332
2
1
1
24
24
23
23
22
22
21 21
20 20
19 19
S S
18
1817
17
16
16
15
15
14 1413 13
12
12
11 11
10 10
9988
7
7
S
66
55
4
4
3
3
2
2
11
24
24
23
23
22
22
21
21
20
2019 19
S
S
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
S
6
6
5
5
4
4
3
3
221
1
2424
23
23
22
2221
21
20
20
1919
S
S
18
18
17
17
16
16
1515
1414
13
13
12
12
111110
10
99
887
7
S66
5
54
4
3
3
2
2
11
24
24
23
23
22
22
21
21
20
2019 19
S
S
18
1817
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
2
11
2424
232322
22
21
21
20
201919
S
S18
181717
16
16
15
15 14
14
1313
1212
1111
1010
9
9
8
8
7
7
S6
6
55
44
33
2
2
1
1
24
24
23
23
2222
21
21
20
20
1919
S
S
18
18
17
17
1616
15
15 1414
13
13
12
12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
2
11
2424
23
232222
21
21
20
20
19
19
S
S1818
1717
16
16
15
15
14
14
1313
1212
11
11
10
10
9
9
88
77S
6
6
5
544
3
322
11
24
24
23
23
22 22
21
2120 20
19
19
S
S
18
18
17 17
16 16
15
15
14 14
13 13
12
12
11
11 10
109
9
8
877
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23
23
22
22
21
21
20 20
19
19
S
S
18 18
17 1716 16
15 15
14 14
13 13
12 1211
11
10
10
9
988
7
7
S
6
6
5
5
4
4
33
2
2
1
1
24
2423
23
22
22
21 21
20
2019
19
S
S18
18
17
17
16 16
15
15 14
14
13
13
12 12
11
11
10 109
9
887
7S
6
6
5
5
4
4
3
3
2
2
1
1
3
120
3
3
3
120
1
120
1
2
120
2
2
2
120
1
120
1
1
1
120
0
120
0
0
120
0
0
0
120
3
121
33
3
121
1
121
1
2
121
22
2
121
V
G
1
121
11
1
121
0
121
0
0
121
00
0
121
3
122
33
3
122
1
122
1
2
122
22
2
122
1
122
11
1
122
0
122
0
0
122
00
0
122
3
123
33
3
123
1
123
1
2
123
22
2
123
1
123
11
1
123
0
123
0
0
123
00
0
123
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
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1
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126
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126
1
126
1
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126
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G
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1
126
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00
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3224
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0224
0
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0224
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0225
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3227
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0227
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0227
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0230
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3231
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1231
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V
1
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1231
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231
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0231
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0231
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3
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3232
3
232
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1233
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0233
0
0
0233
0
233
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
40
VCCO
41
VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 40
Bank 41
Bank 42
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Quad 120
Quad 121
Quad 122
Quad 123
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N ug575_c3_100_030817
{I XILINX¢ ID DIDDDDEDDDDIDDDD DDDBDDDBIDDDDBDD EDDDDIDDDDEDDDDI DDIDDDDEDDDDIDDD u l u u l DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD BEBE! IDDDDI Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-118
Figure 3-118: FLGB2104 Package—XCVU9P Configuration/Power Diagram
8 7
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R
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n
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
(I XILINX¢ u (DOOOOO Ellj® 000600 Send Feedback
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Chapter 3: Device Diagrams
FLGB2104 (XCVU11P)
X-Ref Target - Figure 3-119
Figure 3-119: FLGB2104 Package—XCVU11P I/O Bank Diagram
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111110
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S66
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1111
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S1818
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2019
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1227
1
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0227
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0227
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227
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3228
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228
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1228
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2
2228
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1228
1
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0228
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0228
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3229
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1229
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2229
2
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G
V
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1
1229
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0229
0
0
0229
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3
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1230
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2230
2
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1
1230
1
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0230
0
0
0230
0
230
3
3
3231
3
231
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1231
2
2
2231
2
231
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1
1231
1
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0231
0
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0231
0
231
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3232
3
232
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1232
2
2
2232
2
232
1
1
1232
1
232
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0232
0
0
0232
0
232
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3233
3
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2233
2
233
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1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
66
VCCO
66
VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
67
VCCO
68
VCCO
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VCCO
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VCCO
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VCCO
68
VCCO
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VCCO
69
VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
74
1
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A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
ug575_c3_100_030817
(I XILINX¢ DIDDDDD I l DDDDDDD DDDDDIDI DIDDDDI l DDDDDDDDIDDDDBDDDDIDDDED DDDDDIDEDDDDDDDI u DDIDDDDDDDDDI u I EDD-D E I E IBDDDD l D ID DDDDIDDDDEDDDDIDDDD DDDDDBDDEDIDDDDBDE DEDUDDIDDDDEDUDDI IDDIDMDDEDEDDIDMD DBDEDBIB u DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD I REESE IDDDDI Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-120
Figure 3-120: FLGB2104 Package—XCVU11P Configuration/Power Diagram
8 7
23
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22
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11
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R
15
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E E
E
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V V
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V
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V V
V
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V
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V
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V
V
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V
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V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n n
n n n n
n n n n
n n n n
n n n n n
n n n n n
n n n n n
n n n n n n
n n n n n n n n
n n n n n n n
n n n
n n n
n n n
n n
n n
n n
n
n n
n n n n
n n n
n n n n nn n n
n n n n n n n nn n
n n n n n n n n nn n n
n n n n n n n n nn n n
n n n n n n n n nn n
n n n n n n n nn n n
n n n n n
n n n n
n
1
1
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
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Chapter 3: Device Diagrams
FHGB2104 (XCVU13P)
X-Ref Target - Figure 3-121
Figure 3-121: FHGB2104 Package—XCVU13P I/O Bank Diagram
24
24
23
23
22
22
21 21
20 20
19 19
S S
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1817
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14 1413 13
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11 11
10 10
9988
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7
S
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2019 19
S
S
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S
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6
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5
4
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3
221
1
2424
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2221
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1919
S
S
18
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1515
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12
111110
10
99
887
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S66
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54
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3
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11
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2019 19
S
S
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87
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S
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2
11
2424
232322
22
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21
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201919
S
S18
181717
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15 14
14
1313
1212
1111
1010
9
9
8
8
7
7
S6
6
55
44
33
2
2
1
1
24
24
23
23
2222
21
21
20
20
1919
S
S
18
18
17
17
1616
15
15 1414
13
13
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12
11
11
10
10
9
9
8
87
7
S
6
6
5
5
4
4
3
3
2
2
11
2424
23
232222
21
21
20
20
19
19
S
S1818
1717
16
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15
15
14
14
1313
1212
11
11
10
10
9
9
88
77S
6
6
5
544
3
322
11
24
24
23
23
2222
21
21
20
20
19
19 S
S
18
1817
17 1616
15
15
1414
13
13 1212
1111
1010
9
9
8
87
7S
6
6
5
5
4
4
3
3
2
2
1
1
24
24
23
23
2222
21
21
20
20
19
19S
S
18
18
17
17 1616
1515
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14
1313 1212
11
11
10
10
9
9
8
8
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7
S66
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5
4
4
33
2
2
11
24
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S
S18
18
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1313
121211
11
10
10
9
9
88
7
7
S
6
65
544
3
3
2
21
1
12 12
11
1110
10
99
88
77
S66
5
544
332
2
1
1
24
24
23
23
22 22
21
2120 20
19
19
S
S
18
18
17 17
16 16
15
15
14 14
13 13
12
12
11
11 10
109
9
8
877
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23
23
22
22
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20 20
19
19
S
S
18 18
17 1716 16
15 15
14 14
13 13
12 1211
11
10
10
9
988
7
7
S
6
6
5
5
4
4
33
2
2
1
1
24
2423
23
22
22
21 21
20
2019
19
S
S18
18
17
17
16 16
15
15 14
14
13
13
12 12
11
11
10 109
9
887
7S
6
6
5
5
4
4
3
3
2
2
1
1
3
124
3
3
3
124
1
124
1
2
124
2
2
2
124
1
124
1
1
1
124
0
124
0
0
124
0
0
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
V
G
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
0
0
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
V
G
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
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1
130
1
2
130
22
2
130
1
130
11
1
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0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
G
V
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
2
2
2233
2
233
1
1
1233
1
233
0
0233
0
0
0233
0
233
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
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17
17
18
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19
19
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20
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23
24
24
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27
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29
30
30
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31
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33
33
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36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 61
Bank 62
Bank 63
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
{I XILINX¢ ID DIDDDDEDDDDIDDDD DDDBDDDBIDDDDBDD EDDDDIDDDDEDDDDI DDIDDDDEDDDDIDDD u l u u l DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD I EEEEE Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-122
Figure 3-122: FHGB2104 Package—XCVU13P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
18
16
4
2
5
3
200
17
2830
34
33
29
2929
29
29
29
2929
35
27
29
29
29
29
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26
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2626
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262626
26
2626
252525
25
38
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25
25 25
25
25
25
32
31
3736
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
1
1
2
2
3
3
4
4
5
5
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44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
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Chapter 3: Device Diagrams
FLVC2104 (XCVU5P and XCVU7P)
X-Ref Target - Figure 3-123
Figure 3-123: FLVC2104 Package—XCVU5P and XCVU7P I/O Bank Diagram
2424
23
23
22
22
21
21
20
20
1919
S S
18
18
1717 16
1615
15 14
14
1313
1212
1111
10
10
9
9
88
7
7
S
6
65
5
4
4
3
3
2
2
1
1
24
24
23
23 2222
21
21
2020
19
19
S
S18
18
17
17
16
16
1515
1414
1313
121211
11
1010
9
9
8
8
7
7
S
6
6
5544
3
3
2
2
1
1
24
2423
23
2222
21
21
20
20
19
19
S
S
18
18
17
17 16
161515
1414
1313
1212
1111 10
10
9
9
8877
S
66
5
5
4
4
33
2
2
1
1
24
24
23
23
22
2221
21
20
20
19 19 S
S18 18
17
17
16
16
15
15
14
1413 13
12
12
11 11 10
109
98
8
7
7
S
6
655
4
4
3
3
2
2
1
1
24
2423
23
22 22
21
21
20
20
19
19
S
S
18
18
17 17
16 16
15
15
14 14
13 13
12 12
11 11
10
10 9
9
88
7
7
S
6
6
5
5
443
3
2
2
1
1
24
24
23 23
22 22
21
21
20 20
19
19
S
S18 18
17
1716
16
15 15
14 14
13 13
12 12
11 11
10
10
9
9
88
7
7
S
66
5
5
44
3
3
2
2
1
1
24
24
23
2322
22 21
21
20 20
19
19S
S
18
18
17
17
16
16 15
1514
14
13
13 12
1211
11
10
10
9
9
8
8
7
7S6
6
5
5
4
4
33
2
2
1
1
24
24
23
23
2222
2121
2020
1919
S
S
1818 17
1716
16
15
15
14
14
1313
12
121111
10
10
99
8
8
7
7
S6
6
5
5
44
3
3
2
2
1
1
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
V
G
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
00
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
V
G
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
1
1
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
22
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
33
3233
3
233
1
1233
22
2233
2
233
11
1233
1
233
0
0233
00
0233
0
233
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_100_030817
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-124
Figure 3-124: FLVC2104 Package—XCVU5P and XCVU7P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
1816 4
2
5
3
20 0
17
28
30
34
33
29
2929
29
29
29
29 29 35
2729 29
29
29
26
26
26
26
26
2626 26
26
26
26 26 26
2626
26 25
25
25
25
38
25
25
2525 25
25
25
25
25
32
31
37
36
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
nn n n
nn
nn
n n
nn
n n
nn
nnn n
nn n n
nn
nn n n
n n
nn n n
nn
nn n n
nn n n
nn
nn n n
nn n n
nn
nn n n
nnn n
nn
n
nn
n n
nn
n
nn
n nnn
nnn n
nn
nnn n
n n
nnn n
nn
nnn n
nnn n
nn
nnn n
nnn n
nn
nnn n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n n
n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n n
n
n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
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Chapter 3: Device Diagrams
FLGC2104 (XCVU9P)
X-Ref Target - Figure 3-125
Figure 3-125: FLGC2104 Package—XCVU9P I/O Bank Diagram
2424
23
23
22
22
21
21
20
20
1919
S S
18
18
1717 16
1615
15 14
14
1313
1212
1111
10
10
9
9
88
7
7
S
6
65
5
4
4
3
3
2
2
1
1
24
24
23
23 2222
21
21
2020
19
19
S
S18
18
17
17
16
16
1515
1414
1313
121211
11
1010
9
9
8
8
7
7
S
6
6
5544
3
3
2
2
1
1
24
2423
23
2222
21
21
20
20
19
19
S
S
18
18
17
17 16
161515
1414
1313
1212
1111 10
10
9
9
8877
S
66
5
5
4
4
33
2
2
1
1
24
24
23
23
22
2221
21
20
20
19 19 S
S18 18
17
17
16
16
15
15
14
1413 13
12
12
11 11 10
109
98
8
7
7
S
6
655
4
4
3
3
2
2
1
1
24
2423
23
22 22
21
21
20
20
19
19
S
S
18
18
17 17
16 16
15
15
14 14
13 13
12 12
11 11
10
10 9
9
88
7
7
S
6
6
5
5
443
3
2
2
1
1
24
24
23 23
22 22
21
21
20 20
19
19
S
S18 18
17
1716
16
15 15
14 14
13 13
12 12
11 11
10
10
9
9
88
7
7
S
66
5
5
44
3
3
2
2
1
1
24
24
23
2322
22 21
21
20 20
19
19S
S
18
18
17
17
16
16 15
1514
14
13
13 12
1211
11
10
10
9
9
8
8
7
7S6
6
5
5
4
4
33
2
2
1
1
24
24
23
23
2222
2121
2020
1919
S
S
1818 17
1716
16
15
15
14
14
1313
12
121111
10
10
99
8
8
7
7
S6
6
5
5
44
3
3
2
2
1
1
3
120
33
3
120
1
120
1
2
120
2
2
2
120
1
120
1
1
1
120
0
120
0
0
120
0
0
0
120
3
121
33
3
121
1
121
1
2
121
22
2
121
V
G
1
121
11
1
121
0
121
0
0
121
00
0
121
3
122
33
3
122
1
122
1
2
122
22
2
122
1
122
11
1
122
0
122
0
0
122
00
0
122
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
V
G
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
00
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
V
G
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
1
1
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3220
3
220
1
1220
2
2
2220
2
220
1
1
1220
1
220
0
0220
00
0220
0
220
3
3
3221
3
221
1
1221
2
2
2221
2
221
G
V
1
1
1221
1
221
0
0221
0
0
0221
0
221
3
3
3222
3
222
1
1222
2
2
2222
2
222
1
1
1222
1
222
0
0222
0
0
0222
0
222
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
G
V
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
22
2231
2
231
G
V
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
33
3233
3
233
1
1233
22
2233
2
233
11
1233
1
233
0
0233
00
0233
0
233
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
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38
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39
40
40
41
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42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Quad 120
Quad 121
Quad 122
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 220
Quad 221
Quad 222
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-126
Figure 3-126: FLGC2104 Package—XCVU9P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
1816 4
2
5
3
20 0
17
28
30
34
33
29
2929
29
29
29
29 29 35
2729 29
29
29
26
26
26
26
26
2626 26
26
26
26 26 26
2626
26 25
25
25
25
38
25
25
2525 25
25
25
25
25
32
31
37
36
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
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15
15
16
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17
17
18
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22
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24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLGC2104 (XCVU11P) and FLRC2104 (XQVU11P)
X-Ref Target - Figure 3-127
Figure 3-127: FLGC2104 Package—XCVU11P and FLRC2104 Package—XQVU11P
I/O Bank Diagram
24
24
23
23 2222
21
21
2020
19
19
S
S18
18
17
17
16
16
1515
1414
1313
121211
11
1010
9
9
8
8
7
7
S
6
6
5544
3
3
2
2
1
1
24
2423
23
2222
21
21
20
20
19
19
S
S
18
18
17
17 16
161515
1414
1313
1212
1111 10
10
9
9
8877
S
66
5
5
4
4
33
2
2
1
1
24
24
23
23
22
2221
21
20
20
19 19 S
S18 18
17
17
16
16
15
15
14
1413 13
12
12
11 11 10
109
98
8
7
7
S
6
655
4
4
3
3
2
2
1
1
24
2423
23
22 22
21
21
20
20
19
19
S
S
18
18
17 17
16 16
15
15
14 14
13 13
12 12
11 11
10
10 9
9
88
7
7
S
6
6
5
5
443
3
2
2
1
1
24
24
23 23
22 22
21
21
20 20
19
19
S
S18 18
17
1716
16
15 15
14 14
13 13
12 12
11 11
10
10
9
9
88
7
7
S
66
5
5
44
3
3
2
2
1
1
24
24
23
2322
22 21
21
20 20
19
19S
S
18
18
17
17
16
16 15
1514
14
13
13 12
1211
11
10
10
9
9
8
8
7
7S6
6
5
5
4
4
33
2
2
1
1
24
24
23
23
2222
2121
2020
1919
S
S
1818 17
1716
16
15
15
14
14
1313
12
121111
10
10
99
8
8
7
7
S6
6
5
5
44
3
3
2
2
1
1
2424
23
23
22
22
21
21
20
20
1919
S S
18
18
1717 16
1615
15 14
14
1313
1212
1111
10
10
9
9
88
7
7
S
6
65
5
4
4
3
3
2
2
1
1
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
V
G
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
0
0
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
V
G
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
00
130
00
0
130
3
131
33
3
131
1
131
1
2
131
22
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
33
3
132
1
132
1
2
132
22
2
132
1
132
11
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
V
G
1
133
11
1
133
0
133
0
0
133
00
0
133
3
134
3
3
3
134
1
134
1
2
134
22
2
134
1
134
1
1
1
134
0
134
0
0
134
00
0
134
3
135
3
3
3
135
1
135
1
2
135
2
2
2
135
1
135
1
1
1
135
0
135
0
0
135
0
0
0
135
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
G
V
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
2
2
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
3
3
3233
3
233
1
1233
22
2233
2
233
G
V
1
1
1233
1
233
0
0233
0
0
0233
0
233
3
3
3234
3
234
1
1234
2
2
2234
2
234
1
1
1234
1
234
0
0234
0
0
0234
0
234
33
3235
3
235
1
1235
22
2235
2
235
11
1235
1
235
0
0235
00
0235
0
235
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_100_062217
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 134
Quad 135
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
Quad 234
Quad 235
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-128
Figure 3-128: FLGC2104 Package—XCVU11P and FLRC2104 Package—XQVU11P
Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
1816 4
2
5
3
20 0
17
28
30
34
33
29
2929
29
29
29
29 29 35
2729 29
29
29
26
26
26
26
26
2626 26
26
26
26 26 26
2626
26 25
25
25
25
38
25
25
2525 25
25
25
25
25
32
31
37
36
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
nn n n
nn
nn
n n
n n
nn
n n
nn
nnn n
nnn n
nn
n
nn
n
n n
n
nn
n
nn
n nnn
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_100_062217
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FHGC2104 (XCVU13P)
X-Ref Target - Figure 3-129
Figure 3-129: FHGC2104 Package—XCVU13P I/O Bank Diagram
24
24
23
23 2222
21
21
2020
19
19
S
S18
18
17
17
16
16
1515
1414
1313
121211
11
1010
9
9
8
8
7
7
S
6
6
5544
3
3
2
2
1
1
24
2423
23
2222
21
21
20
20
19
19
S
S
18
18
17
17 16
161515
1414
1313
1212
1111 10
10
9
9
8877
S
66
5
5
4
4
33
2
2
1
1
24
24
23
23
22
2221
21
20
20
19 19 S
S18 18
17
17
16
16
15
15
14
1413 13
12
12
11 11 10
109
98
8
7
7
S
6
655
4
4
3
3
2
2
1
1
24
2423
23
22 22
21
21
20
20
19
19
S
S
18
18
17 17
16 16
15
15
14 14
13 13
12 12
11 11
10
10 9
9
88
7
7
S
6
6
5
5
443
3
2
2
1
1
24
24
23 23
22 22
21
21
20 20
19
19
S
S18 18
17
1716
16
15 15
14 14
13 13
12 12
11 11
10
10
9
9
88
7
7
S
66
5
5
44
3
3
2
2
1
1
24
24
23
2322
22 21
21
20 20
19
19S
S
18
18
17
17
16
16 15
1514
14
13
13 12
1211
11
10
10
9
9
8
8
7
7S6
6
5
5
4
4
33
2
2
1
1
24
24
23
23
2222
2121
2020
1919
S
S
1818 17
1716
16
15
15
14
14
1313
12
121111
10
10
99
8
8
7
7
S6
6
5
5
44
3
3
2
2
1
1
2424
23
23
22
22
21
21
20
20
1919
S S
18
18
1717 16
1615
15 14
14
1313
1212
1111
10
10
9
9
88
7
7
S
6
65
5
4
4
3
3
2
2
1
1
3
121
33
3
121
1
121
1
2
121
2
2
2
121
V
G
1
121
1
1
1
121
0
121
0
0
121
0
0
0
121
3
122
33
3
122
1
122
1
2
122
22
2
122
1
122
11
1
122
0
122
0
0
122
00
0
122
3
123
33
3
123
1
123
1
2
123
22
2
123
1
123
11
1
123
0
123
0
0
123
00
0
123
3
124
33
3
124
1
124
1
2
124
22
2
124
1
124
11
1
124
0
124
0
0
124
00
0
124
3
125
33
3
125
1
125
1
2
125
22
2
125
V
G
1
125
11
1
125
0
125
0
0
125
00
0
125
3
126
33
3
126
1
126
1
2
126
22
2
126
1
126
11
1
126
0
126
0
0
126
00
0
126
3
127
33
3
127
1
127
1
2
127
22
2
127
1
127
11
1
127
0
127
0
0
127
00
0
127
3
128
33
3
128
1
128
1
2
128
22
2
128
1
128
11
1
128
0
128
00
128
00
0
128
3
129
33
3
129
1
129
1
2
129
22
2
129
V
G
1
129
11
1
129
0
129
0
0
129
00
0
129
3
130
33
3
130
1
130
1
2
130
22
2
130
1
130
11
1
130
0
130
0
0
130
00
0
130
3
131
3
3
3
131
1
131
1
2
131
2
2
2
131
1
131
11
1
131
0
131
0
0
131
00
0
131
3
132
3
3
3
132
1
132
1
2
132
22
2
132
1
132
1
1
1
132
0
132
0
0
132
00
0
132
3
133
3
3
3
133
1
133
1
2
133
2
2
2
133
V
G
1
133
1
1
1
133
0
133
0
0
133
0
0
0
133
3
3
3221
3
221
1
1221
2
2
2221
2
221
G
V
1
1
1221
1
221
0
0221
00
0221
0
221
3
3
3222
3
222
1
1222
2
2
2222
2
222
1
1
1222
1
222
0
0222
0
0
0222
0
222
3
3
3223
3
223
1
1223
2
2
2223
2
223
1
1
1223
1
223
0
0223
0
0
0223
0
223
3
3
3224
3
224
1
1224
2
2
2224
2
224
1
1
1224
1
224
0
0224
0
0
0224
0
224
3
3
3225
3
225
1
1225
2
2
2225
2
225
G
V
1
1
1225
1
225
0
0225
0
0
0225
0
225
3
3
3226
3
226
1
1226
2
2
2226
2
226
1
1
1226
1
226
0
0226
0
0
0226
0
226
3
3
3227
3
227
1
1227
2
2
2227
2
227
1
1
1227
1
227
0
0227
0
0
0227
0
227
3
3
3228
3
228
1
1228
2
2
2228
2
228
1
1
1228
1
228
0
0228
0
0
0228
0
228
3
3
3229
3
229
1
1229
2
2
2229
2
229
G
V
1
1
1229
1
229
0
0229
0
0
0229
0
229
3
3
3230
3
230
1
1230
2
2
2230
2
230
1
1
1230
1
230
0
0230
0
0
0230
0
230
3
3
3231
3
231
1
1231
22
2231
2
231
1
1
1231
1
231
0
0231
0
0
0231
0
231
3
3
3232
3
232
1
1232
2
2
2232
2
232
1
1
1232
1
232
0
0232
0
0
0232
0
232
33
3233
3
233
1
1233
22
2233
2
233
G
V
11
1233
1
233
0
0233
00
0233
0
233
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
VCCO
64
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Quad 121
Quad 122
Quad 123
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 221
Quad 222
Quad 223
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-130
Figure 3-130: FHGC2104 Package—XCVU13P Configuration/Power Diagram
8 7
23
24 21
22
10
11
9
12
R
15
13
6
14
19
1816 4
2
5
3
20 0
17
28
30
34
33
29
2929
29
29
29
29 29 35
2729 29
29
29
26
26
26
26
26
2626 26
26
26
26 26 26
2626
26 25
25
25
25
38
25
25
2525 25
25
25
25
25
32
31
37
36
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
V
V
V
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FSGD2104 (XCVU9P)
X-Ref Target - Figure 3-131
Figure 3-131: FSGD2104 Package—XCVU9P I/O Bank Diagram
2424
23
23
2222
2121
2020
19
19
S
S
18
1817
17
1616
1515
1414
1313
12
1211
111010
9
9
88
7
7
S
6
6
5
5
4
4
3
3
22
1
1
2424
2323
2222
2121
202019
19S
S
18
18
1717
1616
1515
14
1413
13 121211
11 1010
99
88
77
S
6
65
5
4
43
3
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2
1
1
2424
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1919
SS 18
1817
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1616
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1414
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11 10
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99
88
77
S
6
65
544
33
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1
1
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22 22
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S
S
18 18
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14 13 13
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12 11 11
10 10
99
8
8
77
S
665
5
443
32
2
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1
24 24
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21 21
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19 19
S
S
18 18
17 17
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15 15
14 14
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12 12
11 11
10 10
9
9
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87
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S
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55
44
33
221
1
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24
2323
22
22
2121
20
20
1919
SS
18
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1414
13131212
11111010
99
88
7
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S
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55
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2
1
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22 22 21 21
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19 19
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S
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15 15
14 14
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10 10
9
9
88
77
S66
55
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4
33
22
1
12424
23
23
22
22
212120
20
19
19S
S
18
18
17
17
1616
1515
1414
13131212
1111 1010
99
88
77
S
66
554
4
3
3
2
2
11
24
24
23
23
2222
2121
2020
1919
S
S
18
181717
16
16
15
15
14141313
1212
1111 1010
998
8
7
7S
66
5
5
44
3322
11
24
24
2323
2222
2121
20
20
19
19
S
S1818
17
17 1616
1515
14
14
1313
1212
1111
10
10
9
98
8
7
7
S
6
6
5
5
44
3
3
22
1
1
24 24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
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1514
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13 13
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11 11
10
10
99
88
7
7
S
6
6
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5
4
4
3
32
2
11
24 24
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20 20 19
19
S S
18 18 17
1716 16
15 15
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10
99
88
77
S
66
55
44
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2
1
1
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24 23
2322
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SS
18 18
17 17
16 16
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15
14 14 13
1312 12
11 11
10 10
9
9
88
7
7
S
6
655
4
4
33
2
2
1
1
0
120
0
1
120
1
0
120
1
120
2
120
3
120
0
1
2
3
0
120
1
120
2
120
3
120
0
1
2
3
0
121
0
1
121
1
G
V
0
121
1
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2
121
3
121
0
1
2
3
0
121
1
121
2
121
3
121
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1
2
3
0
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0
1
122
1
0
122
1
122
2
122
3
122
0
1
2
3
0
122
1
122
2
122
3
122
0
1
2
3
0
123
0
1
123
1
0
123
1
123
2
123
3
123
0
1
2
3
0
123
1
123
2
123
3
123
0
1
2
3
0
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0
1
124
1
0
124
1
124
2
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3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
0
125
0
1
125
1
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
G
V
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
131
0
1
131
1
G
V
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0225
0
1225
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
G
V
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0229
0
1229
1
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0230
0
1230
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
G
V
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0232
0
1232
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
0233
0
1233
1
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1
2
3
VCCO
40
VCCO
40
VCCO
40
VCCO
41
VCCO
41
VCCO
41
VCCO
42
VCCO
42
VCCO
42
VCCO
46
VCCO
46
VCCO
46
VCCO
47
VCCO
47
VCCO
47
VCCO
48
VCCO
48
VCCO
48
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
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11
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40
40
41
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42
42
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44
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45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 40
Bank 41
Bank 42
Bank 46
Bank 47
Bank 48
Bank 64
Bank 65
Bank 66
Bank 67
Bank 70
Bank 71
Bank 72
Quad 120
Quad 121
Quad 122
Quad 123
Quad 124
Quad 125
Quad 126
Quad 127
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
{I XILINX¢ I DUI I DUDE-EDD DIDDDDID DDDEDDDD IDDDDIDD I I D III-IIIIIIDIIIIIIII DDDDDDDDDDDDDDDDDDD IIIIIIIIIIIIIIIIIII DDDDDDDDDDDDDDDDD DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD I BEEEEUIDDDDI Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-132
Figure 3-132: FSGD2104 Package—XCVU9P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
28
30
3433
29
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2929
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29
2929
3527
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29
26
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26
2626
26262626
26262626
2626
2525
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3825
25
25
2525
25
25
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25
32
31
37
36
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n
1
1
2
2
3
3
4
4
5
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45
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46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_100_030817
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
(I XILINX¢ OQOOOQ ®_H=H_ 000005 Send Feedback
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Chapter 3: Device Diagrams
FSGD2104 (XCVU11P)
X-Ref Target - Figure 3-133
Figure 3-133: FSGD2104 Package—XCVU11P I/O Bank Diagram
24
24
23
23
22 22
21
21
20
20
19
19
S
S
18 18
17
17
16
16
15
15
14
14 13 13
12
12 11 11
10 10
99
8
8
77
S
665
5
443
32
2
1
1
24 24
23
23
22
22
21 21
20
20
19 19
S
S
18 18
17 17
16
16
15 15
14 14
13
13
12 12
11 11
10 10
9
9
8
87
7
S
6
6
55
44
33
221
1
24
24
2323
22
22
2121
20
20
1919
SS
18
18
17
17
16
16
15
15
1414
13131212
11111010
99
88
7
7
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23 23
22 22 21 21
20 20
19 19
S
S
18
18
17
17
16
16
15 15
14 14
13
13
12
12
11 11
10 10
9
9
88
77
S66
55
4
4
33
22
1
1
2424
23
23
2222
2121
2020
19
19
S
S
18
1817
17
1616
1515
1414
1313
12
1211
111010
9
9
88
7
7
S
6
6
5
5
4
4
3
3
22
1
1
2424
2323
2222
2121
202019
19S
S
18
18
1717
1616
1515
14
1413
13 121211
11 1010
99
88
77
S
6
65
5
4
43
3
2
2
1
1
2424
23
23
22
22
21
21
20
20
1919
SS 18
1817
17
1616
15
15
1414
13
13
12
12
11
11 10
10
99
88
77
S
6
65
544
33
2
2
1
1
24
24
2323
2222
2121
20
20
19
19
S
S1818
17
17 1616
1515
14
14
1313
1212
1111
10
10
9
98
8
7
7
S
6
6
5
5
44
3
3
22
1
1
24 24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15
1514
14
13 13
12
12
11 11
10
10
99
88
7
7
S
6
6
5
5
4
4
3
32
2
11
24 24
23
23
22
22
21
21
20 20 19
19
S S
18 18 17
1716 16
15 15
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13
13
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12
11
11
10
10
99
88
77
S
66
55
44
33
2
2
1
1
24
24 23
2322
22
21
21
20
20
19
19
SS
18 18
17 17
16 16
15
15
14 14 13
1312 12
11 11
10 10
9
9
88
7
7
S
6
655
4
4
33
2
2
1
1
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
V
0
125
0
1
125
1
G
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
V
0
129
0
1
129
1G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
V
0
133
0
1
133
1
G
0
133
1
133
2
133
3
133
0
1
2
3
0
133
1
133
2
133
3
133
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
V
0229
0
1229
1
G
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0230
0
1230
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0232
0
1232
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
V
0233
0
1233
1
G
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1
2
3
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
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21
22
22
23
23
24
24
25
25
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29
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30
30
31
31
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32
33
33
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35
35
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36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_102217
(I XILINX¢ DI I EDD-EDD IDDDDIDD I I DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD IEEEEEEEDIDDDDI Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-134
Figure 3-134: FSGD2104 Package—XCVU11P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
28
30
3433
29
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2929
29
29
2929
3527
29
29
29
29
26
26
26
26
2626
26262626
26262626
2626
2525
25
25
3825
25
25
2525
25
25
25
25
32
31
37
36
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
nn
n
n
n
n
nnn
n
n
nn
n
n
n
n
n
nn
nn
nn
nnnn
nn nn
nn
nn
nn
n
n nn
nnn
n
n
n
n
n
nn
nn
n
n
n
nn
nn
nn
nn
n
n
n
nnn
n
n
n
n
nnnn
nn
nn nn
nn n
n
n
n n
nnn
n
n
nn
nn nn
nn
n
n
n
n
n
n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_102217
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Chapter 3: Device Diagrams
FIGD2104 (XCVU13P)
X-Ref Target - Figure 3-135
Figure 3-135: FIGD2104 Package—XCVU13P I/O Bank Diagram
24
24
23
23
22 22
21
21
20
20
19
19
S
S
18 18
17
17
16
16
15
15
14
14 13 13
12
12 11 11
10 10
99
8
8
77
S
665
5
443
32
2
1
1
24 24
23
23
22
22
21 21
20
20
19 19
S
S
18 18
17 17
16
16
15 15
14 14
13
13
12 12
11 11
10 10
9
9
8
87
7
S
6
6
55
44
33
221
1
24
24
2323
22
22
2121
20
20
1919
SS
18
18
17
17
16
16
15
15
1414
13131212
11111010
99
88
7
7
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23 23
22 22 21 21
20 20
19 19
S
S
18
18
17
17
16
16
15 15
14 14
13
13
12
12
11 11
10 10
9
9
88
77
S66
55
4
4
33
22
1
12424
23
23
22
22
212120
20
19
19S
S
18
18
17
17
1616
1515
1414
13131212
1111 1010
99
88
77
S
66
554
4
3
3
2
2
11
24
24
23
23
2222
2121
2020
1919
S
S
18
181717
16
16
15
15
14141313
1212
1111 1010
998
8
7
7S
66
5
5
44
3322
11
24
24
2323
2222
2121
20
20
19
19
S
S1818
17
17 1616
1515
14
14
1313
1212
1111
10
10
9
98
8
7
7
S
6
6
5
5
44
3
3
22
1
1
2424
23
23
2222
2121
2020
19
19
S
S
18
1817
17
1616
1515
1414
1313
12
1211
111010
9
9
88
7
7
S
6
6
5
5
4
4
3
3
22
1
1
2424
2323
2222
2121
202019
19S
S
18
18
1717
1616
1515
14
1413
13 121211
11 1010
99
88
77
S
6
65
5
4
43
3
2
2
1
1
2424
23
23
22
22
21
21
20
20
1919
SS 18
1817
17
1616
15
15
1414
13
13
12
12
11
11 10
10
99
88
77
S
6
65
544
33
2
2
1
1
24 24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15
1514
14
13 13
12
12
11 11
10
10
99
88
7
7
S
6
6
5
5
4
4
3
32
2
11
24 24
23
23
22
22
21
21
20 20 19
19
S S
18 18 17
1716 16
15 15
14
14
13
13
12
12
11
11
10
10
99
88
77
S
66
55
44
33
2
2
1
1
24
24 23
2322
22
21
21
20
20
19
19
SS
18 18
17 17
16 16
15
15
14 14 13
1312 12
11 11
10 10
9
9
88
7
7
S
6
655
4
4
33
2
2
1
1
0
120
0
1
120
1
0
120
1
120
2
120
3
120
0
1
2
3
0
120
1
120
2
120
3
120
0
1
2
3
0
121
0
1
121
1
G
V
0
121
1
121
2
121
3
121
0
1
2
3
0
121
1
121
2
121
3
121
0
1
2
3
0
122
0
1
122
1
0
122
1
122
2
122
3
122
0
1
2
3
0
122
1
122
2
122
3
122
0
1
2
3
0
123
0
1
123
1
0
123
1
123
2
123
3
123
0
1
2
3
0
123
1
123
2
123
3
123
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
V
0
129
0
1
129
1G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
V
0
133
0
1
133
1
G
0
133
1
133
2
133
3
133
0
1
2
3
0
133
1
133
2
133
3
133
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
V
0229
0
1229
1
G
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0230
0
1230
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0232
0
1232
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
V
0233
0
1233
1
G
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1
2
3
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_100_062217
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 61
Bank 62
Bank 63
Bank 64
Bank 65
Bank 66
Bank 67
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Quad 120
Quad 121
Quad 122
Quad 123
Quad 128
Quad 129
Quad 130
Quad 131
Quad 133
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
{I XILINX¢ I DUI I DUDE-EDD DIDDDDID DDDEDDDD IDDDDIDD I I D III-III... Ill-Ill- DDDDDDDDDDDDDDDDDDD IIIIIIIIIIIIIIIIIII DDDDDDDDDDDDDDDDD DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD IEEEEEE IDDDDI Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-136
Figure 3-136: FIGD2104 Package—XCVU13P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
28
30
3433
29
29
2929
29
29
2929
3527
29
29
29
29
26
26
26
26
2626
26262626
26262626
2626
2525
25
25
3825
25
25
2525
25
25
25
25
32
31
37
36
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
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A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_100_062217
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FIGD2104 (XCVU27P)
X-Ref Target - Figure 3-137
Figure 3-137: FIGD2104 Package—XCVU27P I/O Bank Diagram
24
24
23
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22 22
21
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20
19
19
S
S
18 18
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16
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15
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12 11 11
10 10
99
8
8
77
S
665
5
443
32
2
1
1
24 24
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S
S
18 18
17 17
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14 14
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11 11
10 10
9
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8
87
7
S
6
6
55
44
33
221
1
24
24
2323
22
22
2121
20
20
1919
SS
18
18
17
17
16
16
15
15
1414
13131212
11111010
99
88
7
7
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23 23
22 22 21 21
20 20
19 19
S
S
18
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15 15
14 14
13
13
12
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11 11
10 10
9
9
88
77
S66
55
4
4
33
22
1
12424
23
23
22
22
212120
20
19
19S
S
18
18
17
17
1616
1515
1414
13131212
1111 1010
99
88
77
S
66
554
4
3
3
2
2
11
24
24
23
23
2222
2121
2020
1919
S
S
18
181717
16
16
15
15
14141313
1212
1111 1010
998
8
7
7S
66
5
5
44
3322
11
24
24
2323
2222
2121
20
20
19
19
S
S1818
17
17 1616
1515
14
14
1313
1212
1111
10
10
9
98
8
7
7
S
6
6
5
5
44
3
3
22
1
1
2424
23
23
2222
2121
2020
19
19
S
S
18
1817
17
1616
1515
1414
1313
12
1211
111010
9
9
88
7
7
S
6
6
5
5
4
4
3
3
22
1
1
2424
2323
2222
2121
202019
19S
S
18
18
1717
1616
1515
14
1413
13 121211
11 1010
99
88
77
S
6
65
5
4
43
3
2
2
1
1
2424
23
23
22
22
21
21
20
20
1919
SS 18
1817
17
1616
15
15
1414
13
13
12
12
11
11 10
10
99
88
77
S
6
65
544
33
2
2
1
1
24 24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15
1514
14
13 13
12
12
11 11
10
10
99
88
7
7
S
6
6
5
5
4
4
3
32
2
11
24 24
23
23
22
22
21
21
20 20 19
19
S S
18 18 17
1716 16
15 15
14
14
13
13
12
12
11
11
10
10
99
88
77
S
66
55
44
33
2
2
1
1
24
24 23
2322
22
21
21
20
20
19
19
SS
18 18
17 17
16 16
15
15
14 14 13
1312 12
11 11
10 10
9
9
88
7
7
S
6
655
4
4
33
2
2
1
1
0
120
1
120
0
1
0
120
1
120
0
1
K
120
K
V
0
121
1
121
0
1
0
121
1
121
0
1
K
121
K
G
0
122
1
122
0
1
0
122
1
122
0
1
K
122
K
0
123
1
123
0
1
0
123
1
123
0
1
K
123
K0
128
1
128
0
1
0
128
1
128
0
1
K
128
K
V
0
129
1
129
0
1
0
129
1
129
0
1
K
129
K
G
0
130
1
130
0
1
0
130
1
130
0
1
K
130
K
0
131
1
131
0
1
0
131
1
131
0
1
K
131
K
V
0
133
1
133
0
1
0
133
1
133
0
1
K
133
K
G
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
1228
0
1
0
228
1
228
0
1
K228
K
V
0229
1229
0
1
0
229
1
229
0
1
K229
K
G
0230
1230
0
1
0
230
1
230
0
1
K230
K
0231
1231
0
1
0
231
1
231
0
1
K231
K
0232
1232
0
1
0
232
1
232
0
1
K232
K
V
0233
1233
0
1
0
233
1
233
0
1
K233
K
G
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
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30
30
31
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33
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36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_xcvu27pfigd2104_010819
SelectIO Pins
#IO_L#P
#IO_L#N
SIO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
GMGTRREF
Transceiver Pins
#MGT[M, H or Y]RXP#
#MGT[M, H or Y]RXN#
#MGT[M, H or Y]TXP#
#MGT[M, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 61
Bank 62
Bank 63
Bank 64
Bank 65
Bank 66
Bank 67
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Dual 120
Dual 121
Dual 122
Dual 123
Dual 128
Dual 129
Dual 130
Dual 131
Dual 133
Quad 224
Quad 225
Quad 226
Quad 227
Dual 228
Dual 229
Dual 230
Dual 231
Dual 232
Dual 233
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-138
Figure 3-138: FIGD2104 Package—XCVU27P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
28
30
3433
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29
2929
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29
2929
3527
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29
29
29
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26
2626
26262626
26262626
2626
2525
25
25
3825
25
25
2525
25
25
25
25
32
31
37
36
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
n n
n n n n
n n n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n
n n n n
n n n n
n n
n n
n n
n n
n n
n n n n
n n
n n n nn n
n n
n n n n
n n
n n n nn n
n n n n
n n n n
n n n n
n n nn n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n n n
n n n n
n n n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
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13
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27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_xcvu27pfigd2104_010819
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
INT
GT VCCINT_GT
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
EMGTAVCC
VMGTAVTT
V
MGTVCCAUX
RRSVDGND
Dedicated Pins
0CCLK_0
2D00_MOSI_0
3D01_DIN_0
4D02_0
5D03_0
6DONE_0
7DXP
8DXN
9INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
(I XILINX¢ manna—manna—ma—mw » a % m umnuumuumumnuu gamma-u.» W a a n m E —# Ennnnnnnnnufl““‘ D a %mu nun—unnuunu n— 090096 ®_H=H_ 000009 Send Feed back
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Chapter 3: Device Diagrams
FIGD2104 (XCVU29P)
X-Ref Target - Figure 3-139
Figure 3-139: FIGD2104 Package—XCVU29P I/O Bank Diagram
24
24
23
23
22 22
21
21
20
20
19
19
S
S
18 18
17
17
16
16
15
15
14
14 13 13
12
12 11 11
10 10
99
8
8
77
S
665
5
443
32
2
1
1
24 24
23
23
22
22
21 21
20
20
19 19
S
S
18 18
17 17
16
16
15 15
14 14
13
13
12 12
11 11
10 10
9
9
8
87
7
S
6
6
55
44
33
221
1
24
24
2323
22
22
2121
20
20
1919
SS
18
18
17
17
16
16
15
15
1414
13131212
11111010
99
88
7
7
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23 23
22 22 21 21
20 20
19 19
S
S
18
18
17
17
16
16
15 15
14 14
13
13
12
12
11 11
10 10
9
9
88
77
S66
55
4
4
33
22
1
12424
23
23
22
22
212120
20
19
19S
S
18
18
17
17
1616
1515
1414
13131212
1111 1010
99
88
77
S
66
554
4
3
3
2
2
11
24
24
23
23
2222
2121
2020
1919
S
S
18
181717
16
16
15
15
14141313
1212
1111 1010
998
8
7
7S
66
5
5
44
3322
11
24
24
2323
2222
2121
20
20
19
19
S
S1818
17
17 1616
1515
14
14
1313
1212
1111
10
10
9
98
8
7
7
S
6
6
5
5
44
3
3
22
1
1
2424
23
23
2222
2121
2020
19
19
S
S
18
1817
17
1616
1515
1414
1313
12
1211
111010
9
9
88
7
7
S
6
6
5
5
4
4
3
3
22
1
1
2424
2323
2222
2121
202019
19S
S
18
18
1717
1616
1515
14
1413
13 121211
11 1010
99
88
77
S
6
65
5
4
43
3
2
2
1
1
2424
23
23
22
22
21
21
20
20
1919
SS 18
1817
17
1616
15
15
1414
13
13
12
12
11
11 10
10
99
88
77
S
6
65
544
33
2
2
1
1
24 24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15
1514
14
13 13
12
12
11 11
10
10
99
88
7
7
S
6
6
5
5
4
4
3
32
2
11
24 24
23
23
22
22
21
21
20 20 19
19
S S
18 18 17
1716 16
15 15
14
14
13
13
12
12
11
11
10
10
99
88
77
S
66
55
44
33
2
2
1
1
24
24 23
2322
22
21
21
20
20
19
19
SS
18 18
17 17
16 16
15
15
14 14 13
1312 12
11 11
10 10
9
9
88
7
7
S
6
655
4
4
33
2
2
1
1
0
120
1
120
0
1
0
120
1
120
0
1
K
120
K
V
0
121
1
121
0
1
0
121
1
121
0
1
K
121
K
G
0
122
1
122
0
1
0
122
1
122
0
1
K
122
K
0
123
1
123
0
1
0
123
1
123
0
1
K
123
K0
128
1
128
0
1
0
128
1
128
0
1
K
128
K
V
0
129
1
129
0
1
0
129
1
129
0
1
K
129
K
G
0
130
1
130
0
1
0
130
1
130
0
1
K
130
K
0
131
1
131
0
1
0
131
1
131
0
1
K
131
K
V
0
133
1
133
0
1
0
133
1
133
0
1
K
133
K
G
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
1228
0
1
0
228
1
228
0
1
K228
K
V
0229
1229
0
1
0
229
1
229
0
1
K229
K
G
0230
1230
0
1
0
230
1
230
0
1
K230
K
0231
1231
0
1
0
231
1
231
0
1
K231
K
0232
1232
0
1
0
232
1
232
0
1
K232
K
V
0233
1233
0
1
0
233
1
233
0
1
K233
K
G
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 61
Bank 62
Bank 63
Bank 64
Bank 65
Bank 66
Bank 67
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Dual 120
Dual 121
Dual 122
Dual 123
Dual 128
Dual 129
Dual 130
Dual 131
Dual 133
Quad 224
Quad 225
Quad 226
Quad 227
Dual 228
Dual 229
Dual 230
Dual 231
Dual 232
Dual 233
SelectIO Pins
#IO_L#P
#IO_L#N
SIO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
GMGTRREF
Transceiver Pins
#MGT[M, H or Y]RXP#
#MGT[M, H or Y]RXN#
#MGT[M, H or Y]TXP#
#MGT[M, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_xcvu29pfigd2104_010819
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-140
Figure 3-140: FIGD2104 Package—XCVU29P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
28
30
3433
29
29
2929
29
29
2929
3527
29
29
29
29
26
26
26
26
2626
26262626
26262626
2626
2525
25
25
3825
25
25
2525
25
25
25
25
32
31
37
36
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
n n
n n n n
n n n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n
n n n n
n n n n
n n
n n
n n
n n
n n
n n n n
n n
n n n nn n
n n
n n n n
n n
n n n nn n
n n n n
n n n n
n n n n
n n nn n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n n n
n n n n
n n n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
INT
GT VCCINT_GT
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
EMGTAVCC
VMGTAVTT
V
MGTVCCAUX
RRSVDGND
Dedicated Pins
0CCLK_0
2D00_MOSI_0
3D01_DIN_0
4D02_0
5D03_0
6DONE_0
7DXP
8DXN
9INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_xcvu29pfigd2104_010819
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Chapter 3: Device Diagrams
FSVH2104 (XCVU33P)
X-Ref Target - Figure 3-141
Figure 3-141: FSVH2104 Package—XCVU33P I/O Bank Diagram
24
24
23 23
22 22
21 21
20 20
19 19
S
S
18 18
17 1716 16
15
15
14 1413 13
12
12
11 11 10
10
99
8
8
77
S
66
5
5
44
332
211
2424
23
23
22
22
21
21
2020
19
19 S
S
1818
17
17
16
16
15
15
1414
13
13
12
12
1111
1010
9
9
8
8
77
S6
6
5
54
4
33
2211
2424
2323
22
22
21
21
202019
19
S
S18
18
1717
16
16
15
15
1414
1313
12
12
1111
10109
9
88
77
S
6
6
5
5
4
43
3
221
124 24
23 23
22
22 21 21
20
20
19
19
S S
18
18 17 17 16
16
15 15
14 14 13
13
12 12
11
11
10 10
9
9
88
77
S
66
5
544
33
2211
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
V
0
125
0
1
125
1
G
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 64
Bank 65
Bank 66
Bank 67
Quad 124
Quad 125
Quad 126
Quad 127
Quad 224
Quad 225
Quad 226
Quad 227
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_031518
(I XILINX¢ DIDDDDIDD DUD- DI IDDD DUDE DUDE-DD DIDDDDB EDD-LET IDDDUIH DDlDJjfi DDDDDDB DDDDDDI DUD- IDDD DUDE DUDE-DEBBIE- DIDDDDDDDDDB DDDIDDDDIDDI DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD DDDDDD IUD- Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-142
Figure 3-142: FSVH2104 Package—XCVU33P Configuration/Power Diagram
0 R
2
3
4
5
6
8 7
9
10 11
12
13
14
15
16
17
18
1920
22
2124
23
2830
3433
29
29
29
29
292929
29
35
27 29
29
2929
26
26
26
26
2626
2626
26
26
2626
262626
26
2525
2525
38
25
25
25
25
25
25
2525
25
323137
36 r
rr r
r
r
r rr
r rr r
Rr r r
r r r r
r r r
r
r
r
r
r
r
rrrr
r
r r r
r r
r
r
r
r r
r
r
rrr
r
r
r
R
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r r
rr
r
r
r
r
r
r
rr HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n
nn
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
nn
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n
n
n
nn
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
nn
n
n
n
n
n
n
n
n
nn
n
n
n
n
n
n
n
n
n
n
nn
n n
n
n
n
n
n
n
n
n
n
n
n
nn
n
n
n
n
n
n
n
n
n
n
n
nn
n
n
n
nn
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
r RSVD
R RSVDGND
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
HBM
AUX VCCAUX_HBM
HBM
VCC VCC_HBM
HBM
IO VCC_IO_HBM
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_031518
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Chapter 3: Device Diagrams
FSVH2104 (XCVU35P)
X-Ref Target - Figure 3-143
Figure 3-143: FSVH2104 Package—XCVU35P I/O Bank Diagram
24
24
23 23
22 22
21 21
20 20
19 19
S
S
18 18
17 1716 16
15
15
14 1413 13
12
12
11 11 10
10
99
8
8
77
S
66
5
5
44
332
211
2424
23
23
22
22
21
21
2020
19
19 S
S
1818
17
17
16
16
15
15
1414
13
13
12
12
1111
1010
9
9
8
8
77
S6
6
5
54
4
33
2211
2424
2323
22
22
21
21
202019
19
S
S18
18
1717
16
16
15
15
1414
1313
12
12
1111
10109
9
88
77
S
6
6
5
5
4
43
3
221
124 24
23 23
22
22 21 21
20
20
19
19
S S
18
18 17 17 16
16
15 15
14 14 13
13
12 12
11
11
10 10
9
9
88
77
S
66
5
544
33
2211
24
24
2323 22
22
21
21
2020
19
19
S
S
18
18
17
171616
15
15
14
14
1313
1212
1111
10
10 99
8877S
6
6
554
4
33
2
2
1
1
2424 23
23
2222
2121 20
201919 S S
18
18
17
17
16
16
1515
1414
1313 12
12
11
11
1010
9
9
88
7
7S
6
6
5
5
4
4
3
32
2
11
24 24
23
23
22 22
21 21
20
2019
19S S
18
18
17
17
16 1615
15
14 14
13 13
12 12
11 11
10
10
9
9
8
8
77
S
6
65
54
4332
211
24
24
23 23 22 22
21 21 20 20
19 19 S S
18 1817 17 16
1615
15
14 1413
13 12 12
11 11
10
10
99
8
8
7
7
S6
6
55
4
43
322
1
1
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
V
0
125
0
1
125
1
G
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
30228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
V
0229
0
1229
1
G
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0230
0
1230
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_031518
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-144
Figure 3-144: FSVH2104 Package—XCVU35P Configuration/Power Diagram
0 R
2
3
4
5
6
8 7
9
10 11
12
13
14
15
16
17
18
1920
22
2124
23
2830
3433
29
29
29
29
292929
29
35
27 29
29
2929
26
26
26
26
2626
2626
26
26
2626
262626
26
2525
2525
38
25
25
25
25
25
25
2525
25
323137
36 r
rr r
r
r
r rr
r rr r
Rr r r
r r r r
r r r
r
r
r
r
r
r
rrrr
r
r r r
r rrr
r
r
r
r r
r
r
rrr
r
r
r
R
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r r
rr
r
r
r
r
r
r
HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
r RSVD
R RSVDGND
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
HBM
AUX VCCAUX_HBM
HBM
VCC VCC_HBM
HBM
IO VCC_IO_HBM
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_031518
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Chapter 3: Device Diagrams
FLGA2577 (XCVU9P)
X-Ref Target - Figure 3-145
Figure 3-145: FLGA2577 Package—XCVU9P I/O Bank Diagram
1212
1111 10
109
9
8
8
77
S
665
54
4
3
3
2
21
1
2424 23
232222 21
21
2020
19
19S
S
1818
17171616
15151414
13
13
1212
1111
1010
99
8
8
7
7
S
6
655
443
3
2
2
11
S12
12
11 11
24 24
23
23
22 22
21
21
20 20
19 19
S
S
18
18
17
17
16
16
15
15
14
14 13
13
12
12
11 11
10
10
99
88
77
S
6
6
55
4
4
33
2
2
1
1
2424
23
23
2222
2121
20
20
1919
S
S
18
18
1717
1616 1515
1414
1313
12
12
11
11
10
10 9
9
8
8
77
S
6
6
5
5
4
4
3
3
2
2
11
24
2423
23 22
22
21
2120
20
1919
S
S
18
18
17
17
16
16
15
15
14
14 13
13
1212
1111
1010 9
98
8
77
S
6
6
5
544
33
22
1
1
24 24
23
23
22
22
21
21
20
20
19 19
S
S
18
18
17 17
16
16
15 15
14 14
13 13
12
12
11
1110 10
99
8
8
77
S
66
5
54
433
2
2
11
24
24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15 15
14 14
13
13
12 12
11 11
10 10
9
9
88
77S
6
6
55
44
33
22
1
1
24
2423
23
22 22
21 21
20
2019 19
S
S
18
18
17 17
16
16
15
1514 14
13 13
12 12
11
11
10
10
9
9
88
7
7
S
6
6
55
4
4
33
2
2
1
1
24
24
23
23
22
2221
21
202019
19
S
S18
18 17
17
16
161515
14
14
1313
1212
11
11
10
1099
88
7
7
S
66
55
4
4
3
3
22
1
1
0
119
0
1
119
1
0
119
1
119
2
119
3
119
0
1
2
30
119
1
119
2
119
3
119
0
1
2
3
0
120
0
1
120
1
0
120
1
120 2
120
3
120
0
1 2
3
0
120
1
120
2
120
3
120
0
1
2
3
0
121
0
1
121
1
V
G
0
121
1
121
2
121
3
121
0
12
3
0
121
1
121
2
121
3
121
0
1
2
3
0
122
0
1
122
1
0
122
1
122
2
122
3
122
0
1
2
3
0
122
1
122
2
122
3
122
0
1
2
3
0
123
0
1
123
1
0
123
1
123
2
123
3
123
0
1
2
3
0
123
1
123
2
123
3
123
0
1
2
3
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
0
125
0
1
125
1
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
V
G
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
0
129
0
1
129
1
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
V
G
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0
132
0
1
132
1
0
132
1
132
2
132
3
132
0
1
2
3
0
132
1
132
2
132
3
132
0
1
2
3
0
133
0
1
133
1
0
133
1
133
2
133
3
133
01
2
3
0
133
1
133
2
133
3
133
0
1
2
3
0219
0
1219
1
0219
1219
2219
3219
0
1
2
3
0
219
1
219
2
219
3
219
0
1
2
3
0220
0
1220
1
0220
1220
2220
3220
0
12
3
0
220
1
220
2
220
3
220
0
1
2
3
0221
0
1221
1
V
G
0221
1221 2221
3221
0
1 2
3
0
221
1
221
2
221
3
221
0
1
2
3
0222
0
1222
1
0222
1222
2222
3222
0
1
2
3
0
222
1
222
2
222
3
222
0
1
2
3
0223
0
1223
1
0223
1223
2223
3223
0
1
2
3
0
223
1
223
2
223
3
223
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0225
0
1225
1
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
V
G
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0229
0
1229
1
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0230
0
1230
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
V
G
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0232
0
1232
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
0233
0
1233
1
0233 1233
2233
3233
0 1
2
3
0
233
1
233
2
233
3
233
0
1
2
3
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
VCCO
72
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
Bank 61
Bank 62
Bank 63
Bank 65
Bank 66
Bank 67
Bank 68
Bank 70
Bank 71
Bank 72
Quad 119
Quad 120
Quad 121
Quad 122
Quad 123
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 219
Quad 220
Quad 221
Quad 222
Quad 223
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-146
Figure 3-146: FLGA2577 Package—XCVU9P Configuration/Power Diagram
8 7
24
23
21
22
10
11
9
12
R
15
13
6
14
19
18
16
4
2
5
3
20
0
17
28 30
34
33
29 29
29
29
29 29
29 29
35
27
29
29
29
29
26
26
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26
26 26
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26 26
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26 26
25 25
25 25
38
25
25
25
25 25
25
25
25 25
32
31
37
36
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V V
V V
V V
V V
V
V
V
V
V
V
V
V
V V
V V
V V
V V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VV
V V
VV
V V
VV
V V
V
V
V
V
V
V
V
V
VV
V V
VV
V V
VV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
n n n n n n n n
n n n n n n n n
n n n n n n n n
n n n n n n n n
n n n n
n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
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21
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22
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24
24
25
25
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27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
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36
37
37
38
38
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39
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40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FLGA2577 (XCVU11P)
X-Ref Target - Figure 3-147
Figure 3-147: FLGA2577 Package—XCVU11P I/O Bank Diagram
S12
12
11 11
24 24
23
23
22 22
21
21
20 20
19 19
S
S
18
18
17
17
16
16
15
15
14
14 13
13
12
12
11 11
10
10
99
88
77
S
6
6
55
4
4
33
2
2
1
1
2424 23
232222 21
21
2020
19
19S
S
1818
17171616
15151414
13
13
1212
1111
1010
99
8
8
7
7
S
6
655
443
3
2
2
11
2424
23
23
2222
2121
20
20
1919
S
S
18
18
1717
1616 1515
1414
1313
12
12
11
11
10
10 9
9
8
8
77
S
6
6
5
5
4
4
3
3
2
2
11
24
2423
23 22
22
21
2120
20
1919
S
S
18
18
17
17
16
16
15
15
14
14 13
13
1212
1111
1010 9
98
8
77
S
6
6
5
544
33
22
1
1
24 24
23
23
22
22
21
21
20
20
19 19
S
S
18
18
17 17
16
16
15 15
14 14
13 13
12
12
11
1110 10
99
8
8
77
S
66
5
54
433
2
2
11
24
24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15 15
14 14
13
13
12 12
11 11
10 10
9
9
88
77S
6
6
55
44
33
22
1
1
24
2423
23
22 22
21 21
20
2019 19
S
S
18
18
17 17
16
16
15
1514 14
13 13
12 12
11
11
10
10
9
9
88
7
7
S
6
6
55
4
4
33
2
2
1
1
24
24
23
23
22
2221
21
202019
19
S
S18
18 17
17
16
161515
14
14
1313
1212
11
11
10
1099
88
7
7
S
66
55
4
4
3
3
22
1
1
1212
1111 10
109
9
8
8
77
S
665
54
4
3
3
2
21
1
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
0
125
0
1
125
1
V
G
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
2
3
0
127
0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
0
129
0
1
129
1
V
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0
132
0
1
132
1
0
132
1
132
2
132
3
132
0
1
2
3
0
132
1
132
2
132
3
132
0
1
2
3
0
133
0
1
133
1
V
G
0
133
1
133
2
133
3
133
0
1
2
3
0
133
1
133
2
133
3
133
0
1
2
3
0
134
0
1
134
1
0
134
1
134
2
134
3
134
01
2
3
0
134
1
134
2
134
3
134
0
1
2
3
0
135
0
1
135
1
0
135
1
135
2
135
3
135
0
1
2
3
0
135
1
135
2
135
3
135
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0225
0
1225
1
V
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0229
0
1229
1
V
G
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0230
0
1230
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0232
0
1232
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
0233
0
1233
1
V
G
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1
2
3
0234
0
1234
1
0234 1234
2234
3234
0 1
2
3
0
234
1
234
2
234
3
234
0
1
2
3
0235
0
1235
1
0235
1235
2235
3235
0
1
2
3
0
235
1
235
2
235
3
235
0
1
2
3
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
1
1
2
2
3
3
4
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51
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
ug575_c3_100_030817
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 65
Bank 66
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Bank 75
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 134
Quad 135
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
Quad 234
Quad 235
{I XILINX¢ I D D I D IDDDIDDD IDDD D DID l D l D D IDDDIDDD DDDDDDDDDDDDDD DDDDDDDDD DDDDDDDDDDDDDDD I BEBE! IDDDDI Send Feed back
UltraScale Device Packaging and Pinouts 330
UG575 (v1.12) March 20, 2019 www.xilinx.com
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-148
Figure 3-148: FLGA2577 Package—XCVU11P Configuration/Power Diagram
8 7
24
23
21
22
10
11
9
12
R
15
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6
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28 30
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E
E
E
E
E
E
E
E
E E
E
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E
E
E
E
E
E
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E
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E
E
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E
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E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V V
V V
V V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VV
V V
VV
V V
VV
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n nn nn n n n n n n nn n n
n n n nn n n n n n n n nn n n
n n nn nn n n n n n n nn n n
n n n nn n n n n n n n nn n n
n n n n n n nn n n n n nn n n n n n nn n
n n n n n n nn n n n n n n n n n n nn n nn n
n n n n n nn n n n nn n n n n n nn n
n n n n n n n n n n n n n n n n nn n n
n n n n n n n n n n n n n nn n
n n n n n n n n n n n n n n n n nn n n
1
1
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
{I XILINX¢ xx u (DOOOOO DD® 000600 Send Feed back
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Chapter 3: Device Diagrams
FLGA2577 and FSGA2577 (XCVU13P)
X-Ref Target - Figure 3-149
Figure 3-149: FLGA2577 and FSGA2577 Packages—XCVU13P I/O Bank Diagram
S12
12
11 11
24 24
23
23
22 22
21
21
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19 19
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S
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18
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17
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10
99
88
77
S
6
6
55
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2
2
1
1
2424
23
23
2222
2121
20
20
1919
S
S
18
18
1717
1616 1515
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10 9
9
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8
77
S
6
6
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5
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11
24
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23 22
22
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2120
20
1919
S
S
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13
1212
1111
1010 9
98
8
77
S
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544
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1
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13 13
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1110 10
99
8
8
77
S
66
5
54
433
2
2
11
1212
1111 10
109
9
8
8
77
S
665
54
4
3
3
2
21
1
2424 23
232222 21
21
2020
19
19S
S
1818
17171616
15151414
13
13
1212
1111
1010
99
8
8
7
7
S
6
655
443
3
2
2
11
24
24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15 15
14 14
13
13
12 12
11 11
10 10
9
9
88
77S
6
6
55
44
33
22
1
1
24
2423
23
22 22
21 21
20
2019 19
S
S
18
18
17 17
16
16
15
1514 14
13 13
12 12
11
11
10
10
9
9
88
7
7
S
6
6
55
4
4
33
2
2
1
1
24
24
23
23
22
2221
21
202019
19
S
S18
18 17
17
16
161515
14
14
1313
1212
11
11
10
1099
88
7
7
S
66
55
4
4
3
3
22
1
1
0
120
0
1
120
1
0
120
1
120
2
120
3
120
0
1
2
30
120
1
120
2
120
3
120
0
1
2
3
0
121
0
1
121
1
V
G
0
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1
121 2
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3
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1 2
3
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2
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1
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2
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0
12
3
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1
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3
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0
1
2
3
0
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0
1
123
1
0
123
1
123
2
123
3
123
0
1
2
3
0
123
1
123
2
123
3
123
0
1
2
3
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
2
3
0
124
1
124
2
124
3
124
0
1
2
3
0
125
0
1
125
1
V
G
0
125
1
125
2
125
3
125
0
1
2
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
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2
126
3
126
0
1
2
3
0
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0
1
127
1
0
127
1
127
2
127
3
127
0
1
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
1
2
3
0
129
0
1
129
1
V
G
0
129
1
129
2
129
3
129
0
1
2
3
0
129
1
129
2
129
3
129
0
1
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
1
2
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
2
3
0
132
0
1
132
1
0
132
1
132
2
132
3
132
0
1
2
3
0
132
1
132
2
132
3
132
0
1
2
3
0
133
0
1
133
1
V
G
0
133
1
133
2
133
3
133
0
1
2
3
0
133
1
133
2
133
3
133
0
1
2
3
0
134
0
1
134
1
0
134
1
134
2
134
3
134
01
2
3
0
134
1
134
2
134
3
134
0
1
2
3
0
135
0
1
135
1
0
135
1
135
2
135
3
135
0
1
2
3
0
135
1
135
2
135
3
135
0
1
2
3
0220
0
1220
1
0220
1220
2220
3220
0
1
2
3
0
220
1
220
2
220
3
220
0
1
2
3
0221
0
1221
1
V
G
0221
1221
2221
3221
0
12
3
0
221
1
221
2
221
3
221
0
1
2
3
0222
0
1222
1
0222
1222 2222
3222
0
1 2
3
0
222
1
222
2
222
3
222
0
1
2
3
0223
0
1223
1
0223
1223
2223
3223
0
1
2
3
0
223
1
223
2
223
3
223
0
1
2
3
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
0225
0
1225
1
V
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1
2
3
0229
0
1229
1
V
G
0229
1229
2229
3229
0
1
2
3
0
229
1
229
2
229
3
229
0
1
2
3
0230
0
1230
1
0230
1230
2230
3230
0
1
2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2
3
0232
0
1232
1
0232
1232
2232
3232
0
1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
0233
0
1233
1
V
G
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1
2
3
0234
0
1234
1
0234 1234
2234
3234
0 1
2
3
0
234
1
234
2
234
3
234
0
1
2
3
0235
0
1235
1
0235
1235
2235
3235
0
1
2
3
0
235
1
235
2
235
3
235
0
1
2
3
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
63
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
74
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
VCCO
75
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
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31
32
32
33
33
34
34
35
35
36
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37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
Bank 61
Bank 62
Bank 63
Bank 65
Bank 66
Bank 70
Bank 71
Bank 73
Bank 74
Bank 75
Quad 120
Quad 121
Quad 122
Quad 123
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 134
Quad 135
Quad 220
Quad 221
Quad 222
Quad 223
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
Quad 234
Quad 235
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_100_030817
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-150
Figure 3-150: FLGA2577 and FSGA2577 Packages—XCVU13P Configuration/Power Diagram
8 7
24
23
21
22
10
11
9
12
R
15
13
6
14
19
18
16
4
2
5
3
20
0
17
28 30
34
33
29 29
29
29
29 29
29 29
35
27
29
29
29
29
26
26
26
26
26
26 26
26
26
26
26 26
26
26
26 26
25 25
25 25
38
25
25
25
25 25
25
25
25 25
32
31
37
36
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V V
V V
V V
V V
V V
V V
V
V
V
V
V
V
V
V
V V
V V
V V
V V
V V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VV
V V
VV
V V
VV
V V
V
V
V
V
V
V
V
V
VV
V V
VV
V V
VV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
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14
14
15
15
16
16
17
17
18
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19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
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36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
R RSVDGND
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
ug575_c3_100_030817
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Chapter 3: Device Diagrams
FSGA2577 (XCVU27P)
X-Ref Target - Figure 3-151
Figure 3-151: FSGA2577 Package—XCVU27P I/O Bank Diagram
24
24
23
23
22 22
21
21
20
20
19
19
S
S
18 18
17
17
16
16
15
15
14
14 13 13
12
12 11 11
10 10
99
8
8
77
S
665
5
443
32
2
1
1
24 24
23
23
22
22
21 21
20
20
19 19
S
S
18 18
17 17
16
16
15 15
14 14
13
13
12 12
11 11
10 10
9
9
8
87
7
S
6
6
55
44
33
221
1
24
24
2323
22
22
2121
20
20
1919
SS
18
18
17
17
16
16
15
15
1414
13131212
11111010
99
88
7
7
S
6
6
55
4
4
3
3
2
2
1
1
24
24
23 23
22 22 21 21
20 20
19 19
S
S
18
18
17
17
16
16
15 15
14 14
13
13
12
12
11 11
10 10
9
9
88
77
S66
55
4
4
33
22
1
12424
23
23
22
22
212120
20
19
19S
S
18
18
17
17
1616
1515
1414
13131212
1111 1010
99
88
77
S
66
554
4
3
3
2
2
11
24
24
23
23
2222
2121
2020
1919
S
S
18
181717
16
16
15
15
14141313
1212
1111 1010
998
8
7
7S
66
5
5
44
3322
11
24
24
2323
2222
2121
20
20
19
19
S
S1818
17
17 1616
1515
14
14
1313
1212
1111
10
10
9
98
8
7
7
S
6
6
5
5
44
3
3
22
1
1
2424
23
23
2222
2121
2020
19
19
S
S
18
1817
17
1616
1515
1414
1313
12
1211
111010
9
9
88
7
7
S
6
6
5
5
4
4
3
3
22
1
1
2424
2323
2222
2121
202019
19S
S
18
18
1717
1616
1515
14
1413
13 121211
11 1010
99
88
77
S
6
65
5
4
43
3
2
2
1
1
2424
23
23
22
22
21
21
20
20
1919
SS 18
1817
17
1616
15
15
1414
13
13
12
12
11
11 10
10
99
88
77
S
6
65
544
33
2
2
1
1
24 24
23 23
22 22
21 21
20
20
19 19
S
S
18 18
17
17
16
16
15
1514
14
13 13
12
12
11 11
10
10
99
88
7
7
S
6
6
5
5
4
4
3
32
2
11
24 24
23
23
22
22
21
21
20 20 19
19
S S
18 18 17
1716 16
15 15
14
14
13
13
12
12
11
11
10
10
99
88
77
S
66
55
44
33
2
2
1
1
24
24 23
2322
22
21
21
20
20
19
19
SS
18 18
17 17
16 16
15
15
14 14 13
1312 12
11 11
10 10
9
9
88
7
7
S
6
655
4
4
33
2
2
1
1
0
120
1
120
0
1
0
120
1
120
0
1
K
120
K
V
0
121
1
121
0
1
0
121
1
121
0
1
K
121
K
G
0
122
1
122
0
1
0
122
1
122
0
1
K
122
K
0
123
1
123
0
1
0
123
1
123
0
1
K
123
K0
128
1
128
0
1
0
128
1
128
0
1
K
128
K
V
0
129
1
129
0
1
0
129
1
129
0
1
K
129
K
G
0
130
1
130
0
1
0
130
1
130
0
1
K
130
K
0
131
1
131
0
1
0
131
1
131
0
1
K
131
K
V
0
133
1
133
0
1
0
133
1
133
0
1
K
133
K
G
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
1228
0
1
0
228
1
228
0
1
K228
K
V
0229
1229
0
1
0
229
1
229
0
1
K229
K
G
0230
1230
0
1
0
230
1
230
0
1
K230
K
0231
1231
0
1
0
231
1
231
0
1
K231
K
0232
1232
0
1
0
232
1
232
0
1
K232
K
V
0233
1233
0
1
0
233
1
233
0
1
K233
K
G
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_xcvu27pfigd2104_010819
SelectIO Pins
#IO_L#P
#IO_L#N
SIO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
GMGTRREF
Transceiver Pins
#MGT[M, H or Y]RXP#
#MGT[M, H or Y]RXN#
#MGT[M, H or Y]TXP#
#MGT[M, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 61
Bank 62
Bank 63
Bank 64
Bank 65
Bank 66
Bank 67
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Dual 120
Dual 121
Dual 122
Dual 123
Dual 128
Dual 129
Dual 130
Dual 131
Dual 133
Quad 224
Quad 225
Quad 226
Quad 227
Dual 228
Dual 229
Dual 230
Dual 231
Dual 232
Dual 233
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-152
Figure 3-152: FSGA2577 Package—XCVU27P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
28
30
3433
29
29
2929
29
29
2929
3527
29
29
29
29
26
26
26
26
2626
26262626
26262626
2626
2525
25
25
3825
25
25
2525
25
25
25
25
32
31
37
36
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
n n
n n n n
n n n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n
n n n n
n n n n
n n
n n
n n
n n
n n
n n n n
n n
n n n nn n
n n
n n n n
n n
n n n nn n
n n n n
n n n n
n n n n
n n nn n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n n n
n n n n
n n n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
ug575_c3_xcvu27pfigd2104_010819
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
INT
GT VCCINT_GT
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
EMGTAVCC
VMGTAVTT
V
MGTVCCAUX
RRSVDGND
Dedicated Pins
0CCLK_0
2D00_MOSI_0
3D01_DIN_0
4D02_0
5D03_0
6DONE_0
7DXP
8DXN
9INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
(I XILINX¢ manna—manna—ma—mw » a % m umnuumuumumnuu gamma-u.» W a a n m E —# Ennnnnnnnnufl““‘ D a %mu nun—unnuunu n— 090096 ®_H=H_ 000009 Send Feed back
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Chapter 3: Device Diagrams
FSGA2577 (XCVU29P)
X-Ref Target - Figure 3-153
Figure 3-153: FSGA2577 Package—XCVU29P I/O Bank Diagram
24
24
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20
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S
S
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99
8
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77
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665
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443
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S
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S
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221
1
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24
2323
22
22
2121
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20
1919
SS
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1414
13131212
11111010
99
88
7
7
S
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6
55
4
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3
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2
1
1
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19 19
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S
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11 11
10 10
9
9
88
77
S66
55
4
4
33
22
1
12424
23
23
22
22
212120
20
19
19S
S
18
18
17
17
1616
1515
1414
13131212
1111 1010
99
88
77
S
66
554
4
3
3
2
2
11
24
24
23
23
2222
2121
2020
1919
S
S
18
181717
16
16
15
15
14141313
1212
1111 1010
998
8
7
7S
66
5
5
44
3322
11
24
24
2323
2222
2121
20
20
19
19
S
S1818
17
17 1616
1515
14
14
1313
1212
1111
10
10
9
98
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7
S
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6
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5
44
3
3
22
1
1
2424
23
23
2222
2121
2020
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19
S
S
18
1817
17
1616
1515
1414
1313
12
1211
111010
9
9
88
7
7
S
6
6
5
5
4
4
3
3
22
1
1
2424
2323
2222
2121
202019
19S
S
18
18
1717
1616
1515
14
1413
13 121211
11 1010
99
88
77
S
6
65
5
4
43
3
2
2
1
1
2424
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22
22
21
21
20
20
1919
SS 18
1817
17
1616
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15
1414
13
13
12
12
11
11 10
10
99
88
77
S
6
65
544
33
2
2
1
1
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22 22
21 21
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20
19 19
S
S
18 18
17
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1514
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13 13
12
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11 11
10
10
99
88
7
7
S
6
6
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5
4
4
3
32
2
11
24 24
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22
22
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21
20 20 19
19
S S
18 18 17
1716 16
15 15
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11
11
10
10
99
88
77
S
66
55
44
33
2
2
1
1
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24 23
2322
22
21
21
20
20
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19
SS
18 18
17 17
16 16
15
15
14 14 13
1312 12
11 11
10 10
9
9
88
7
7
S
6
655
4
4
33
2
2
1
1
0
120
1
120
0
1
0
120
1
120
0
1
K
120
K
V
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121
1
121
0
1
0
121
1
121
0
1
K
121
K
G
0
122
1
122
0
1
0
122
1
122
0
1
K
122
K
0
123
1
123
0
1
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123
1
123
0
1
K
123
K0
128
1
128
0
1
0
128
1
128
0
1
K
128
K
V
0
129
1
129
0
1
0
129
1
129
0
1
K
129
K
G
0
130
1
130
0
1
0
130
1
130
0
1
K
130
K
0
131
1
131
0
1
0
131
1
131
0
1
K
131
K
V
0
133
1
133
0
1
0
133
1
133
0
1
K
133
K
G
0224
0
1224
1
0224
1224
2224
3224
0
1
2
3
0
224
1
224
2
224
3
224
0
1
2
3
V
0225
0
1225
1
G
0225
1225
2225
3225
0
1
2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2
3
0227
0
1227
1
0227
1227
2227
3227
0
1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
1228
0
1
0
228
1
228
0
1
K228
K
V
0229
1229
0
1
0
229
1
229
0
1
K229
K
G
0230
1230
0
1
0
230
1
230
0
1
K230
K
0231
1231
0
1
0
231
1
231
0
1
K231
K
0232
1232
0
1
0
232
1
232
0
1
K232
K
V
0233
1233
0
1
0
233
1
233
0
1
K233
K
G
VCCO
61
VCCO
61
VCCO
61
VCCO
62
VCCO
62
VCCO
62
VCCO
63
VCCO
63
VCCO
63
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
VCCO
72
VCCO
72
VCCO
72
VCCO
73
VCCO
73
VCCO
73
VCCO
74
VCCO
74
VCCO
74
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
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27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
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36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Bank 61
Bank 62
Bank 63
Bank 64
Bank 65
Bank 66
Bank 67
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Dual 120
Dual 121
Dual 122
Dual 123
Dual 128
Dual 129
Dual 130
Dual 131
Dual 133
Quad 224
Quad 225
Quad 226
Quad 227
Dual 228
Dual 229
Dual 230
Dual 231
Dual 232
Dual 233
SelectIO Pins
#IO_L#P
#IO_L#N
SIO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
GMGTRREF
Transceiver Pins
#MGT[M, H or Y]RXP#
#MGT[M, H or Y]RXN#
#MGT[M, H or Y]TXP#
#MGT[M, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-154
Figure 3-154: FSGA2577 Package—XCVU29P Configuration/Power Diagram
0
R
2
3
4
5
6
8 7
9
10
11
12
13
14
15
16
17
18
19
20
22
2124
23
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30
3433
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2929
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2929
3527
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29
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26
2626
26262626
26262626
2626
2525
25
25
3825
25
25
2525
25
25
25
25
32
31
37
36
E
E
E
E
E
E E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
INT
GT
n n
n n n n
n n n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n
n n n n
n n n n
n n
n n
n n
n n
n n
n n n n
n n
n n n nn n
n n
n n n n
n n
n n n nn n
n n n n
n n n n
n n n n
n n nn n n
n n n n n n
n n n n
n n n n n n
n n n n
n n n n n n n n
n n n n
n n n n n n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
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20
21
21
22
22
23
23
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25
25
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27
27
28
28
29
29
30
30
31
31
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33
34
34
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36
37
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38
38
39
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40
40
41
41
42
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44
44
45
45
46
46
A A
B B
C C
D D
EE
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
INT
GT VCCINT_GT
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
EMGTAVCC
VMGTAVTT
V
MGTVCCAUX
RRSVDGND
Dedicated Pins
0CCLK_0
2D00_MOSI_0
3D01_DIN_0
4D02_0
5D03_0
6DONE_0
7DXP
8DXN
9INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FSVH2892 (XCVU35P)
X-Ref Target - Figure 3-155
Figure 3-155: FSVH2892 Package—XCVU35P I/O Bank Diagram
24 24
23
23
22
22
21
21
20 20
19 19
S
S
18
18 17
17 16 16
15 15
14 14
13 13
12
12
11
11
10
10 9
9
88
7
7
S6
655
4
4
3
3
2
2
11
24
24
2323
2222 2121
20
20
1919S
S
1818
1717
16
16
1515
14
14
1313
1212
11
11
10
10
99
8877
S66
5
5
44
3
3
22
11
2424
23
23
2222
2121 2020
19
19
S
S
18181717
16
16
15
15
1414
13
13
1212
1111 1010
9988
7
7
S
6
6
5
5
4
4
332
2
1
1
24
24
2323
22
22
21
21
2020
1919
S
S
1818
1717
1616
1515
141413
13
12
12
11
11
10
10
9
9
8
87
7
S6
6
5
5
44
3
3
22
11
24
24
23 23 22 22
21 21 20 20
19 19 S S
18 1817 17 16
1615
15
14 1413
13 12 12
11 11
10
10
99
8
8
7
7
S665
544
3322
11
24 24 23 23 22
2221
21
20 20
19 19 S S
18 18
17
17
16 16
15
1514 14
13
1312
12
11
11
10 10
9
98
87
7S
6
655
4
4
3322
11
24
24 23 23 22 22
21 21
20 20 19 19
S S 18 18
17 17
16
16
15
15
14 14
13
13
12 1211
1110 10
99
8
8
77
S
665
5
4
4
3322
11
24 24
23
23
22 22
21 21 20 20
19 19 S S 18 18
17 17
16
16
15 15
14 14
13
13
12
12
11
11
10
10
9
9
8
8
77
S
6
6
55
443
3
2211
0
124
0
1
124
1
0
124
1
124
2
124
3
124
0
1
23
0
124
1
124
2
124
3
124
01
2
3
V
0
125
0
1
125
1
G
0
125
1
125
2
125
3
125
0
12
3
0
125
1
125
2
125
3
125
0
1
2
3
0
126
0
1
126
1
0
126
1
126
2
126
3
126
0
1
2
3
0
126
1
126
2
126
3
126
0
1
23
0
127
0
1
127
1
0
127
1
127
2
127
3
127
01
2
3
0
127
1
127
2
127
3
127
0
1
2
3
0
128
0
1
128
1
0
128
1
128
2
128
3
128
0
1
2
3
0
128
1
128
2
128
3
128
0
12
3
V
0
129
0
1
129
1
G
0
129
1
129
2
129
3
129
0
1
23
0
129
1
129
2
129
3
129
01
2
3
0
130
0
1
130
1
0
130
1
130
2
130
3
130
0
12
3
0
130
1
130
2
130
3
130
0
1
2
3
0
131
0
1
131
1
0
131
1
131
2
131
3
131
0
1
2
3
0
131
1
131
2
131
3
131
0
1
23
0224
0
1224
1
0224
1224
2224 3224
0
1
2 3
0
224
1
224
2
224
3
224
0 1
2
3
V
0225
0
1225
1
G
0225
1225 2225
3225
0
1 2
3
0
225
1
225
2
225
3
225
0
1
2
3
0226
0
1226
1
0226
1226
2226
3226
0
1
2
3
0
226
1
226
2
226
3
226
0
1
2 3
0227
0
1227
1
0227 1227
2227
3227
0 1
2
3
0
227
1
227
2
227
3
227
0
1
2
3
0228
0
1228
1
0228
1228
2228
3228
0
1
2
3
0
228
1
228
2
228
3
228
0
1 2
3
V
0229
0
1229
1
G
0229
1229
2229 3229
0
1
2 3
0
229
1
229
2
229
3
229
0 1
2
3
0230
0
1230
1
0230
1230 2230
3230
0
1 2
3
0
230
1
230
2
230
3
230
0
1
2
3
0231
0
1231
1
0231
1231
2231
3231
0
1
2
3
0
231
1
231
2
231
3
231
0
1
2 3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
67
VCCO
67
VCCO
68
VCCO
68
VCCO
68
VCCO
69
VCCO
69
VCCO
69
VCCO
70
VCCO
70
VCCO
70
VCCO
71
VCCO
71
VCCO
71
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
BM BM
BN BN
BP BP
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Quad 124
Quad 125
Quad 126
Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 224
Quad 225
Quad 226
Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
ug575_c3_031518
(I XILINX¢ l D I D l D l D l D l D I D l l l l I l l l u DDDIDDDDIDDD u IDDDDIDDDDID l DDIDDDDIDDDDI IDDDDIDDDDIDD l IDDI SHEEN I DDDDDD UDUUDUDDUDDUDUU DDDDDDDDD DUUDUDDUDDUDUU Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-156
Figure 3-156: FSVH2892 Package—XCVU35P Configuration/Power Diagram
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R
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rr HBM
AUX
HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
AUX
HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
E
E
E
E
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E
E
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
BM BM
BN BN
BP BP
ug575_c3_031518
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
r RSVD
R RSVDGND
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
HBM
AUX VCCAUX_HBM
HBM
VCC VCC_HBM
HBM
IO VCC_IO_HBM
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
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Chapter 3: Device Diagrams
FSVH2892 (XCVU37P)
X-Ref Target - Figure 3-157
Figure 3-157: FSVH2892 Package—XCVU37P I/O Bank Diagram
24 24
23
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88
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2222 2121
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99
8877
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2222
2121 2020
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S
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1111 1010
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5
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2323
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S
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S665
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99
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665
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2020
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988
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1
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2019
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121111
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99887
7S6
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88
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S6
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554
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11
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19S S
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98
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77S
665
54
4
332
211
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1
23
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G
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3
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0229
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G
0229
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2 3
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3
229
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3
0230
0
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0230
1230 2230
3230
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1 2
3
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3
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2231
3231
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2
3
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1
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3
231
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1
2 3
0232
0
1232
1
0232 1232
2232
3232
0 1
2
3
0
232
1
232
2
232
3
232
0
1
2
3
V
0233
0
1233
1
G
0233
1233
2233
3233
0
1
2
3
0
233
1
233
2
233
3
233
0
1 2
3
0234
0
1234
1
0234
1234
2234
3234
0
1
2
3
0
234
1
234
2
234
3
234
0 1
2
3
0235
0
1235
1
0235
1235
2235
3235
0
1
2
3
0
235
1
235
2
235
3
235
0
1
2
3
VCCO
64
VCCO
64
VCCO
64
VCCO
65
VCCO
65
VCCO
65
VCCO
66
VCCO
66
VCCO
66
VCCO
67
VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
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VCCO
73
VCCO
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VCCO
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VCCO
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VCCO
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VCCO
75
VCCO
75
1
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
BM BM
BN BN
BP BP
Bank 64
Bank 65
Bank 66
Bank 67
Bank 68
Bank 69
Bank 70
Bank 71
Bank 72
Bank 73
Bank 74
Bank 75
Quad 124
Quad 125
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Quad 127
Quad 128
Quad 129
Quad 130
Quad 131
Quad 132
Quad 133
Quad 134
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Quad 224
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Quad 227
Quad 228
Quad 229
Quad 230
Quad 231
Quad 232
Quad 233
Quad 234
Quad 235
SelectIO Pins
#IO_L#P
#IO_L#N
S IO (single−ended)
#IO_L#P_GC
#IO_L#N_GC
VRP
Dedicated Pins
VREF
V
MGTAVTTRCAL
G MGTRREF
Transceiver Pins
#MGT[R, H or Y]RXP#
#MGT[R, H or Y]RXN#
#MGT[R, H or Y]TXP#
#MGT[R, H or Y]TXN#
#MGTREFCLK#P
#MGTREFCLK#N
ug575_c3_110317
{I XILINX¢ u DDDIDDDDIDDD u IDDDDIDDDDID l DDIDDDDIDDDDI IDDDDIDDDDIDD l DDDDDD SHEEN EEI DDDDDDDDD D D I UDUUDUDDUDDUDUU DUUDUDDUDDUDUU Send Feed back
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Chapter 3: Device Diagrams
X-Ref Target - Figure 3-158
Figure 3-158: FSVH2892 Package—XCVU37P Configuration/Power Diagram
0
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AUX
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AUX
HBM
VCC
HBM
VCC
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VCC
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VCC
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VCC
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VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
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VCC
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VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
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VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
AUX
HBM
AUX
HBM
AUX
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
VCC
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
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HBM
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IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
HBM
IO
E
E
E
E
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A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
A
W AW
AY AY
BA BA
BB BB
BC BC
BD BD
BE BE
BF BF
BG BG
BH BH
BJ BJ
BK BK
BL BL
BM BM
BN BN
BP BP
Power Pins
GND
VBATT
VCCAUX_IO
VCCAUX
VCCINT
VCCINT_IO
VCCO
VCCBRAM
VCCADC
GNDADC
nNC
r RSVD
R RSVDGND
E MGTAVCC
V MGTAVTT
V
MGTVCCAUX
HBM
AUX VCCAUX_HBM
HBM
VCC VCC_HBM
HBM
IO VCC_IO_HBM
Dedicated Pins
0 CCLK_0
2 D00_MOSI_0
3 D01_DIN_0
4 D02_0
5 D03_0
6 DONE_0
7 DXP
8 DXN
9 INIT_B_0
10 M0_0
11 M1_0
12 M2_0
13 POR_OVERRIDE
14 PROGRAM_B_0
15 PUDC_B_0
16 RDWR_FCS_B_0
17 TCK_0
18 TDI_0
19 TDO_0
20 TMS_0
21 VP
22 VN
23 VREFP
24 VREFN
Multi−Function I/O Pins
25 A[16 to 28]
26 A[00 to 15]_D[16 to 31]
27 CSI_ADV_B
28 DOUT_CSO_B
29 D[04 to 15]
30 EMCCLK
31 FOE_B
32 FWE_FCS2_B
33 I2C_SCLK
34 PERSTN1_I2C_SDA
35 PERSTN0
38 SMBALERT
36 RS0
37 RS1
(I X|L|NX.
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Chapter 4
Mechanical Drawings
Summary
This chapter provides mechanical drawings (package specifications) of the UltraScale and
UltraScale+ device packages. Table 4-1 is a cross-reference to the mechanical drawings by
device and package combination.
All Kintex and Virtex UltraScale+ devices are available in packages with eutectic BGA balls.
To order these packages, the device type starts with an XQ vs. XC and the third digit in the
package name replaces the V or G with a Q to delineate the use of eutectic balls on an
otherwise XC package. For information on ordering the XQ non-ruggedized eutectic Sn/Pb
ball packages, see the XQ UltraScale+ FPGA Ordering Information in the XQ UltraScale
Architecture Data Sheet Overview (DS895) [Ref 2]. For the XQ non-ruggedized eutectic
Sn/Pb ball packages mechanicals, refer to the XC packages in Table 4-1 because they are
built with an XC style package and lid using Pb-free solder inside.
In Table 4-1, the full Defense-grade XQ ruggedized packages are delineated by an R in the
third digit of the package code.
Table 4-1: Cross-Reference to Mechanical Drawings by Package
Package Figure Device Package Status
FBVA676 Figure 4-1
Figure 4-2 XCKU035 XCKU040 Production
FFVA676
FFQA676 Figure 4-3 XCKU3P XCKU5P Production
FFVB676
FFQB676 Figure 4-3 XCKU3P XCKU5P Production
FFRB676 Figure 4-4 XQKU5P Production
RBA676 Figure 4-5 XQKU040 Production
SFVA784 Figure 4-6 XCKU035 XCKU040 Production
SFVB784
SFQB784 Figure 4-7 XCKU3P XCKU5P Production
SFRB784 Figure 4-8 XQKU5P Production
(I XILINXG Send Feed back
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Chapter 4: Mechanical Drawings
FBVA900 Figure 4-9
Figure 4-10 XCKU035 XCKU040 Production
FFVD900
FFQD900 Figure 4-11 XCKU3P XCKU5P XCKU11P Production
FFVE900
FFQE900 Figure 4-11 XCKU9P XCKU13P Production
FFVA1156
FFQA1156(1)
Figure 4-12 XCKU025 XCKU035 XCKU040 Production
Figure 4-13 XCKU060 XCKU095 XCKU11P Production
Figure 4-14 XCKU15P Production
FFRA1156 Figure 4-15 XQKU15P Production
RFA1156 Figure 4-16 XQKU040 Production
Figure 4-17 XQKU060 XQKU095 Production
FFVA1517 Figure 4-18 XCKU060 Production
FLVA1517 Figure 4-21 XCKU085 XCKU115 Production
FFVC1517
FFQC1517(1)
Figure 4-18 XCKU095 XCVU065 XCVU080 XCVU095 Production
Figure 4-19 XCVU3P Production
FFRC1517 Figure 4-20 XQVU3P Production
FFVD1517 Figure 4-18 XCVU080 XCVU095 Production
FLVD1517 Figure 4-21 XCKU115 XCVU125 Production
FFVE1517
FFQE1517 Figure 4-19 XCKU11P XCKU15P Production
FFRE1517 Figure 4-20 XQKU15P Production
RLD1517 Figure 4-22 XQKU115 Production
FFVA1760
FFQA1760 Figure 4-23 XCKU15P Production
FFVB1760 Figure 4-24 XCKU095 XCVU080 XCVU095 Production
FLVB1760 Figure 4-25 XCKU085 XCKU115 XCVU125 Production
FFVE1760
FFQE1760 Figure 4-26 XCKU15P Production
FLVD1924 Figure 4-27 XCKU115 Production
FLVF1924 Figure 4-27 XCKU085 XCKU115 Production
FLGF1924
FLQF1924 Figure 4-28 XCVU11P Production
RLF1924 Figure 4-29 XQKU115 Production
FSVH1924
FSQH1924 Figure 4-30 XCVU31P Production
FFVA2104 Figure 4-31 XCVU080 XCVU095 Production
Table 4-1: Cross-Reference to Mechanical Drawings by Package (Cont’d)
Package Figure Device Package Status
(I XILINXG Send Feed back
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Chapter 4: Mechanical Drawings
FHGA2104
FHQA2104 Figure 4-32 XCVU13P Production
FLVA2104
FLQA2104(1)
Figure 4-34 XCKU115 XCVU125 Production
Figure 4-35 XCVU5P XCVU7P Production
FLRA2104 Figure 4-36 XQVU7P Production
FLGA2104
FLQA2104 Figure 4-37 XCVU9P Production
FFVB2104 Figure 4-31 XCKU095 XCVU080 XCVU095 Production
FHGB2104
FHQB2104 Figure 4-33 XCVU13P Production
FLVB2104
FLQB2104(1)
Figure 4-34 XCKU115 XCVU125 Production
Figure 4-35 XCVU5P XCVU7P Production
FLRB2104 Figure 4-36 XQVU7P Production
FLGB2104
FLQB2104(1)
Figure 4-38 XCVU160 XCVU190 Production
Figure 4-39 XCVU9P XCVU11P Production
FFVC2104 Figure 4-41 XCVU095 Production
FHGC2104
FHQC2104 Figure 4-33 XCVU13P Production
FLGC2104
FLQC2104(1)
Figure 4-38 XCVU160 XCVU190 Production
Figure 4-42 XCVU9P Production
Figure 4-39 XCVU11P Production
FLRC2104 Figure 4-40 XQVU11P Production
FLVC2104
FLQC2104(1)
Figure 4-43 XCVU125 Production
Figure 4-44 XCVU5P XCVU7P Production
FIGD2104
FIQD2104(1)
Figure 4-45 XCVU13P Production
Figure 4-45 XCVU27P XCVU29P Evaluation
Only
FSGD2104
FSQD2104
Figure 4-46 XCVU9P Production
Figure 4-47 XCVU11P Production
FSVH2104
FSQH2104
Figure 4-48 XCVU33P Production
Figure 4-49 XCVU35P Production
FLGB2377 Figure 4-50 XCVU440 Production
FLGA2577
FLQA2577(1)
Figure 4-51 XCVU190 Production
Figure 4-52 XCVU9P XCVU13P Production
Figure 4-53 XCVU11P Production
Table 4-1: Cross-Reference to Mechanical Drawings by Package (Cont’d)
Package Figure Device Package Status
(I XILINXa Send Feed back
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Chapter 4: Mechanical Drawings
FSGA2577
FSQA2577
Figure 4-54 XCVU13P Production
Figure 4-54 XCVU27P XCVU29P Evaluation
Only
FLGA2892 Figure 4-55 XCVU440 Production
FSVH2892
FSQH2892
Figure 4-56 XCVU35P Production
Figure 4-57 XCVU37P Production
Notes:
1. The XQ devices with non-ruggedized eutectic Sn/Pb ball packages are only available in Kintex and Virtex
UltraScale+ devices.
Table 4-1: Cross-Reference to Mechanical Drawings by Package (Cont’d)
Package Figure Device Package Status
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Chapter 4: Mechanical Drawings
FBVA676 Bare-die Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040)
X-Ref Target - Figure 4-1
Figure 4-1: Package Dimensions for FBVA676 (XCKU035 and XCKU040)
ug575_c4_01_082014
(I XILINXa CH‘P CAPAC‘TOR LAYOUT Pw ‘ LD. ma m 77a PACKAGE wmmnoN DESERWQN 57° mm TYPE EAPAUTDR AREA ”“575 DEV‘CE TVPE Know n m 29 gg W m: 5sz [mm] m u as m ‘ m M KEEPDUT AREA (mm) J ”29 “a m ‘7 35 am no “15 m: KEEPfluT AREA rm" (“KL Q Q Send Feed back
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Chapter 4: Mechanical Drawings
X-Ref Target - Figure 4-2
Figure 4-2: FBVA676 Package (XCKU035 and XCKU040) Die Dimensions with Capacitor Locations
ug575_c4_02_082014
(I X|L|NXm ”k W ooooooouuooooooooooooouooo ooooooouooaaoooooooooooooe TOP V‘EW 1W) PIN l [D . 0' a 2 F c H E : g 5 n; v m L , M m m w ’5 gg *7 2210 MAX m M w L A2 2 MILLIMETERS E B T E MIN‘ NDM‘ MAX‘ E A 113 331 355 A1 0‘40 050 mu A2 2‘61 881 3m 2700 BASIC 25m BASIC 1 @ L00 BASIC wk: 0‘50 0‘50 070 2 non 4» 4,, 020 (c: 4w w 025 3- mm w 4‘, 025 ass w a» mu M as 2 E FFVAE7$ 7 Sn/Ag/Cu SEILDER BALL: FFVBE76 7 Sn/Ag/CM SDLDER HALLS NOTES: V ALL DLMENSLONS AND TOLERANCES CONFORM T0 ANSL Y14,5M*1994 SYMBOL 'M‘ S THE BALL MATRLX SLZE, CONFORMS TO JEDEC M870347AAL71 Send Feed back
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Chapter 4: Mechanical Drawings
FFVA676 and FFVB676 Flip-Chip, Fine-Pitch BGA
(XCKU3P and XCKU5P)
X-Ref Target - Figure 4-3
Figure 4-3: Package Dimensions for FFVA676 and FFVB676 (XCKU3P and XCKU5P)
ug575_c4_ffva676_ffvb676_ku3p_ku5p_041917
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Chapter 4: Mechanical Drawings
FFRB676 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU5P)
X-Ref Target - Figure 4-4
Figure 4-4: Package Dimensions for FFRB676 (XQKU5P)
ug575_c4_ffrb676_010819
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Chapter 4: Mechanical Drawings
RBA676 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU040)
X-Ref Target - Figure 4-5
Figure 4-5: Package Dimensions for RBA676 (XQKU040)
ug575_c4_r1_032417
(I X|L|NXm BOTTOM VTEW ‘ni'zwnflmmmn mu” m: T oooooooooao oooooooooooog oooooooeooo ooooooeooooeo . ooocooooeooe cooooeooeoooe c ooooooooooao 0000000000000 .1 oooooooaooao ooooaoooooooo : ooooocooooao oooooooooooeoo F ooocooooeooe cooooeooeoooe L oooooooooooo ooooooooooooo A oooooooacoao 00500050000004 oouoeaooeaao ooooooeooooeuo A ooocooooeoae oeooaoooocoooc L oooooooooooo ooooooooooooo u ooooooooooao ooooooooooooo . aoacocoa ooouoc coc- oooceoooeooc cocooeooaoooe . oooooooooooo ooooooooooooo V oooooooacoao ooooaoooooooo u ooooooooaooo ooooooooooouoo v oooceoooeoac cocooeooaoooe . oooooooooooo ooooooooooooo v oooocooacoao ooooacooooooo .. oaoauaoouooo noooooeoocoeoc .. ooocoooooooc cocoooooeoooe K oooooooooooo ooooooooooooo m oooocooocoao ooooooooooooo ( oaoouooouoco oooaoouaooouoc A: ooocooooeooa cooaoeooaoooa .1 00000 000000 ooooooooooooOvu 79¢X/ SEATING PLANE TOP VTEW r PINIID #- d g-<4><> Lm // CC: C T :pr T s ; MILLIMETERS g B T E MINT NDM‘ MAX‘ E A 3‘12 3‘32 352 A1 use 0‘40 044 A2 2‘72 2‘92 312 2300 BASIC El also BASIC E 080 BASIC am 045 use 055 um) «M «a ma cc: 4», «M 020 ow w. a» 015 see «M «a one M 28 a .._.._..J A2 Y ea mm ea c A TBT Weee ea) c SFVA784 7 SW/Ag/CM SEILDER BALLS T T A ’”'—"T T T J EH“? T “RH NOTES: 1. ALL DTMENSTONS AND TOLERANCES CONEORM TO ANST TULSA/14994 2 SYMBOL 'M' TS THE BALL MATRTX STZE 3, CONEORMS TO JEDEC Mfli216 EAUiT Send Feed back
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Chapter 4: Mechanical Drawings
SFVA784 Flip-Chip, Chip-Scale (0.8 mm) BGA
(XCKU035 and XCKU040)
X-Ref Target - Figure 4-6
Figure 4-6: Package Dimensions for SFVA794 (XCKU035 and XCKU040)
ug575_c4_23_070615
(I X|L|NXm BOWOM V‘EW TOP V‘EW 1W0 r [PIN 1 LDL «w oocooooocoo oceaoocooaoo aoaacuacuoaoncaoaaoaoaucuoc . oooooooooocco aoooooaooooooo c oooooooooouoo coeocecooaoooo . 00050auocuoconcoocoocooucuoc E oaooocoocooao aeoceoaoooeooc F ooooccoooouoo coucocoooooooo : oooouoaoouooo ooeoooooonouoo N oaoooooooooao aeoceoaooocooc; cooooooooooco coeooooooooooo « cooonoaooooooaooeoooooouocoo L occaceoocooco coocoocooaeooc .. ooooooooooeoo coeoooocoooooo n eooocoooocooo ooeoooooocoooo . E so a a a . ooooooooooeoo oooooooooooooo r ecoocooooouoo ococoocooaoooo u onoonauoouocoaauoaaooooucuoa y ooooooooooeoo oooooooooooooo . eooocoooooooo oceocecooaoooo v ocooucuacuoaoaauocuuooouauoc .. oaoooooooooco aooaooaooooooc u cocoocoooouoo ooeooooooacooo K ccoonouoouooonooooooooououoo m occuceoocooao aeoceoaooocooc K cooooooooooco 00000000000000 3 oooonoooooooo ooeoooooococoo m ocean oooooco ceoceocoooeo 784x / Lm SEATING PLANE $¢ddd®c A‘B‘ meeecmc S srva754 7 WWW mum BALLS ; MILLIMETERS g E T E MIN NDM MAX E A 292 312 3 32 0‘36 U40 0‘44 252 E‘7E 252 2300 BASIC NOTES: 2150 BASIC 1. ALL D‘MENS‘ONS AND TOLERANCES CONFORM UBU BASIC TO ANSL v145M4994 ‘4 L L r , U 5 ”5” 055 2. SYMBOL M ‘5 THE BALL MATRLX SLZE ”84/ "9/ 020 cc: 4,, w 020 3. CONFORMS TO JEDEC M07216 EAUrT ddd W/ 48;, 015 see fly, KM 0‘08 M 28 E Send Feed back
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Chapter 4: Mechanical Drawings
SFVB784 Flip-Chip, Super-Fine Pitch (0.8 mm) BGA
(XCKU3P and XCKU5P)
X-Ref Target - Figure 4-7
Figure 4-7: Package Dimensions for SFVB794 (XCKU3P and XCKU5P)
ug575_c4_sfvb784_ku3p_ku5p_041917
(I X|L|NXm BOTIOM VIEW TOP VIEW :-<4><> «ooooeoooaooooooeooooocooo occococoaauoccooccoaaoccoooc . ooaooeoouooocaooeooauooaoooe c ooaeaooooooooaeoooooooocacao u ocoooooooooooooooooooooooooos coooeoocaaoccocooocaoeoooocos ooaaoooaoooeooooooaooooooono a oooaooaooooooooooooooooooooo N aooooocooooooooooooooooooooo 4 aaoooooooooaooooooooooaooooo. acoooooooooooooooooocooooooeI ccoococooooccoouoooaoocooooo . ocaooeocaaacccoooooaaoccoooc u ooaoooooaooooaooeoouoooaowo ; coo woo (woo woo 0000 o . aonooooooooooooocooooeoooooov eaooooocoooooocooocoooooonno I ooaooooaooooooooooaooooooono v oooooooooooooooooooooooooooo . oooooooooooooooooooooooooooc v oaoocooooooooooooooooouooooo u acooccoooooooooccooooooooooo I. cocococoaauoococcooaaoccoooc I: ocaooeocaaoocaooeocaaoccoooc m ooaaooooooooaaaooooooooaaaao I: ooooaoooooooooooooooooooooeo w aooooooooooooooooocooooooooo .5 ounce oeoooeeeeoooeoooeeonno SEATING PLANE Z MILLIMETERS g E T E MINI NDM‘ MAX‘ 5 A 3‘12 132 352 A, 035 mu 0‘44 A2 2‘72 2‘92 112 E/I 23qu BASIC 21‘60 BASIC U‘BU BASIC 0‘45 0‘50 055 w w 020 (Cc 4w w 020 and m, 4&4 0‘15 229 w. w. 008 M as 2 PIN 1 L11 L E L' D LID I I InnI‘DD V A2 W I EAL II I "“0 ‘ $mddd®CAIBI wees-(8)5 SFRE7E4 7 Evy/Pk) SEILDER HALLS SFRC784 7 Evy/Pk) SEILDER BALLS NOTES: I ALL DIMENSIONS AND IOLERANCES CONFORM TO ANSI YI4,5M7I994 2, SYMBOL ’M' IS THE BALL MATRIX SIZE 3. CONFORMS TO JEDEC MOiZIE BAUiI Send Feed back
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Chapter 4: Mechanical Drawings
SFRB784 Ruggedized Flip-Chip, Super Fine-Pitch
BGA (XQKU5P)
X-Ref Target - Figure 4-8
Figure 4-8: Package Dimensions for SFRB784 (XQKU5P)
ug575_c4_sfrb784_010719
(I X|L|NXm EH .—@— Lumzvz‘zs’fla’fiflamn'" Ts T: W“: ‘7 5 s ‘ 3 BOWOM V‘EW 2, wooooooooooooe oocoooooocooo“ TOP V‘EW :-<4><> E PINIID cmcnun Am occeccuoccoccoo 000003000000 3 naooaoooooooooo oooooenoooooen c oooecoeocoeooee occaoecoecooeo n u oooeooooooeoooe oooooooooooooo a oooouoooooouooo oouoooooouoooo c oooouoooooooooe oooooeooooooeo H - occeucoocceccoo 090003009000“ 4 uaaooeaoccooeao aooeaooaooacou x a uooouoooooouooo oouooouoouooou L aooeooooooeoooe 00000000000000 u a ocoooeooooooooo eoooeooeoocooo , w aoooooooooooooo 00000000090000 .1 oooeooooooeoooo cocooeooocooeo , a ucoouaaocaouaoo aouaoouaoucaou u uoooooooooooooo oooooooooooooo v a ooooooooooouooc oooooooooooooo w oeeoooooceooooo oooeeoooooeooo u ' uooouoooaoouooo oouooouoouooou m . oooeooooooeoooe oeuooeooooooeo w oooooeoooooaooo oeoooooeoocooa LE uooouoooooouooo oouooouoouooou » occuncooccoccoo 090003009000“ w r, a uacooooocaooooo aooccooaooccou m ooocooeoooeooec oeaoeeooeaooco Al noooooooooooooo oooooooooaoooe i m: 17;: «mm AREA (A5 mu am) (in 3mm 25m SEATING PLANE ‘—~J EJL H “4 5-1-35] : mam-E ; MILLIMETERS E EEVAsuu 7 :n/Ag/Cu SEILDEE BALL: 5 T E MINT NIIIMT MAX 5 A 2‘40 250 ago A; 0‘40 050 (men A2 150 am aau NOTES; D/E 31‘00 BASIC ME, 2900 BASIC 1. ALL DTMENSTONS AND TOLERANCES CONFORM 9 L00 BASIC To ANST VT4V5M4994 um 050 men 070 2, SYMBOL ‘M’ Ts THE BALL MATRTX STZE °““ ”V” ”V 0‘2” 3V CONFORMS To JEDEC M87034 (DEPOPULATED) CE: W, my 035 dad my My 030 4, SEE NEXT PAGE FOR CHTP CAPACTTOR LDCATTON DTMENSTONS see w w, mm M an 3 Send Feed back
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Chapter 4: Mechanical Drawings
FBVA900 Bare-die Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040)
X-Ref Target - Figure 4-9
Figure 4-9: Package Dimensions for FBVA900 (XCKU035 and XCKU040)
ug575_c4_24_041615
(I X|L|NXm CH‘P CAPAC‘TOR LAYOUT TOP V‘EW 1m mm: wmnwm nsscmpnnu mu mmg WPE mm; m om: mg wow "‘7 n ma “mi ' ' ' ' , DE 5sz (mm) am m n 35 new "w M xgwnm Am (mm) 4‘ 7““ .m m was m: KEEFEIUT AREA n1: Send Feed back
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Chapter 4: Mechanical Drawings
X-Ref Target - Figure 4-10
Figure 4-10: FBVA900 Package (XCKU035 and XCKU040) Die Dimensions with Capacitor Locations
ug575_c4_25_041615
(I X|L|NXm 80mm vxgw A_(m TOP V‘EW L] .m IEI —@— PIN 1 In L “222; 37 a 5 ‘ a 2 L moooooommauooooooooooow L 0' ooooooooooumauocooooooooooou a — cocoooooooumauococoooooooow c occcooooooooouuooocccooooooooo n occccocoooooooooccoccccocooooo E occccaeooooooocccocccccccooooo ; occccccoooooooooeeecccccecoooo a eceeccccooooooooecccecccccoooo H cceeecccoooooooooooeeeecccoooo J oeeeccccoooooooooooeeeccoooooo K oeecooooooaoooooooooccoooooooo L X moooooooamommmooooom L ( moooooooomammooooooooa N 2 00000000000ooaaomooooooooooo , 00000000000ooooomooooooooooo » D ”000000000ooooooooooooooooooo Y a, 50000000000ooooomooooooooooo L m 50000000000oucoooooooooooooooo v m 00000000000mauooooooooooom w 00000009000mauocooooooooooou , cocooooooouuoaaaocooooooooom M occcooooooooooooococcooooooooo La occccooooooooooooooccccooooooo m occcccooooooooooooocoocoooooao w occccccoooooooooooooooooocoooo .2 ececccecooooooooooooooooccoooo L: oceeecccooooooooooooooocceoooo .5 eecccocoooooooooooooooccoooooo M eeeeooooooaaaooooooooooooooooa M moooooooaaooooooooooooooooae«i ESLIU MAX 4 L L SEATING PLANE Ljfigmunwmwwrmmmwv—‘i “m A; EH Lmbj‘ a-wdddluD-Ifl S flees-«'4!- ; MILLIMETERS g rrvngoo 2 Sn/Ag/Cu SDLDER BALLS E T FFVEQUD * Sn/Ag/Cu SDLDER BALLS El L MINL NDM‘ MAX‘ E A 302 322 342 A; we use use A2 252 2‘72 292 NOTES D/E 311m BASIC 1M, 9900 BASIC L ALL DLMENSLONS AND TOLERANCES CONFORM E 100 BASIC TO ANSL M45M4994 Lab use use mu 2. SYMBOL 'M' Ls THE BALL MATRLX SLZE m W W ‘ 030 3. CONFORMS TO JEDEC M32034 (DEPOPULATED) CC: 22., 4w 035 add ”y, ”e, 030 999 4y, 454/ 0‘10 M 30 2 Send Feed back
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Chapter 4: Mechanical Drawings
FFVD900 (XCKU3P, XCKU5P, and XCKU11P) and
FFVE900 (XCKU9P and XCKU13P)
X-Ref Target - Figure 4-11
Figure 4-11: Package Dimensions for FFVD900 (XCKU3P, XCKU5P, and XCKU11P) and
FFVE900 (XCKU9P and XCKU13P)
ug575_c4_16_041716
(I X|L|NXm BOWOM VLEW TOP VLEW ‘ fi‘fST’Eg‘Vszf‘uflm’Wo‘ T7"Ts”u"u‘“a ‘7 5 5 ‘ 2 3 oaooooooooooocooooaoooooooeooaoo oooooooooooooooooooooooooooooooo oooouooooeooooooooooouocoooooooo ooooocooocoouooouoooooucoocoouooou aooooooooeooooooooooooooooaooooaoo anooooaooooaooaooaooaooaooooaooao oocoooooococoooouoooooooocooococoa ooooooooeooonoaooooooooooooooooaoo ooooaooaoooooooaoooocaooaooooouoao oooooooooooooucooooooooooooooouoou oooaooooococooaooaooaooooococooaoo oaocaoaaoouoauoaooaocaoaaoouoacoon oooeoooooooooooooooocoooooooooooou oooooocoooneDoceooooooooooooonocoo ooocaocccocoocoooooooaoccoccoocooo oooooooooocooooooooocooooooooooooo ooooooooococoonooocooooooocooooooo oaoccoocoocoooooooococoocoucoaoooo oooooooooooooooooooooooooooooooooo ooooooouoooooooeooooouocuoooocooco ooooaaooouoacocooooooaacoocoacoooo oooooooooaooooaeooooeoooooeooooano oeooaooooaooaooaooeoouooaoooooooco oooooooooccoocoouoocoouoooucoocooo ooooooooeooooooooooooooooeooonoaoo ooooaooaocoooooaooooeaooaoooooooao ooooooooooooouoouoooooooooooooooou oooaooooococoonooaooaoooooaooooaoo oaooauaaooooauoaooaoeaoaaooaoaucoo ooocoooooooooocouoooooooocooooooou ooooeocooooonocoooooooocoooconocoo ooooaoccoooooccooooocaocaoocooccoo oooooooooouooooooooocooooooooooooo ooooooooocoooooooooooooooocooooooer T co“ co co E H Eggzgcimzssaq“«hurnxmmmm 9370 EDT MAX SEATING PLANE EEvAnSs , Sn/Ag/Cu qunm BALLS : ; MILLIMETERS g E r E MINT NIIIMT MAXT E A 3 DE 322 3 42 0‘40 0‘50 060 NOTES 5‘55 5‘75 3‘99 T, ALL DTMENSTONS AND TOLERANCES CONFORM 3500 BASIC To ANST YTA.5M7T994 3300 BASIC , , mu BASIC 2 SYMBOL M Ts THE BALL MATRTX STZE nan Del] U70 4 3. CONFORMS To JEDEC MSrDMrAARrT m“ "" ”5" ”‘20 4. ACTUAL SOLDER BALL COUNT : 1156 cc: w 454/ 0‘35 ddd my, ”34, 030 m 4,, a» 010 M 34 2 Send Feed back
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Chapter 4: Mechanical Drawings
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU025, XCKU035, and XCKU040)
X-Ref Target - Figure 4-12
Figure 4-12: Package Dimensions for FFVA1156 (XCKU025, XCKU035, and XCKU040)
ug575_c4_05_041716
(I X|L|NXm BOTTOM VTEw TOP VTEW (4X) El PIN l LDT {seaagivaaufieew =7 6 s ‘ a 2 T caooaooaoccoocoocuaooaooaoccoacooo“ A aoooooooooooooooooooooaoooooooom a ocooooooocooooooooooooooooooocoooo c ammmmmoommmamm a oooooaoemmmommmoooom E oaooaooaocoooooeooaooaooaoocooooao ; aocooooooeoaocoooaocmoooooaoooeo c aooooaoeoaooomooooooooeooooomo H aomooamoomooomooamooam L aouomooooooooooo”00000000000000 K aommmooomommoommm L c.amooammmowomamoemo . aoooooooooooooooao00000000000000” N anommooommmmmmmoo , aomooamoemooomooamoemo A ooooooooooooooomooooaoooooooooou v aommomoomaoommmoooco L ommmomommmammm v aooooooooeoooooouo”00000000000000 w oomommommommemmm v awwwmamooocoooamocamm M oooooamooommooooaoeoooomw .3 acoocooaocuoanoooceoocooaoocoauooo m aooooooomaoooooaocooooooooaoooeo Ln aoooooomoooomoooooooooooooeooo L ccoooooaocoooooeooooooooao¢aoooooo A: aouomooooaoooooo00050000000000” m amemmmmaommmmm M (laceaooaooouaaooooaooaooaooaocaooo N aooooooooooooooooo”00000000000000 .x aoomomommommomoomoo L aomooaoeooemooomommemo w aoooooooooooooomoucoooooooooooou A mmmmoomoemommomcer - 29‘70 SGT MAXT SEATING PLANE rrvAnSs , MW mm BALL; 3 A MILLIMETERS g B T u a L MINT NDMT MAX 311 331 351 DAD BSD USU NOTES 2‘61 281 T 301 T, ALL DTMENSTONS AND TOLERANCES CONFORM 3500 HASH: To ANST YM.5M71994 33‘00 BASIC T , 2 SYMBOL M Ts THE BALL MATRTX STZE L00 BASIC nan usu mu 4 3. CONFORMS To JEDEC MSrDMrAARr ”‘0 ”v ”EU 4. ACTUAL SOLDER BALL COUNT 1155 (cc Irv W2 025 add w m, use see 4,, N 0‘10 M 34 2 Send Feed back
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Chapter 4: Mechanical Drawings
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU060, XCKU095, and XCKU11P)
X-Ref Target - Figure 4-13
Figure 4-13: Package Dimensions for FFVA1156 (XCKU060, XCKU095, and XCKU11P)
ug575_c4_06_041716
(I X|L|NXm may BOTTOM VT EW “zy’fiv’szsz‘nzfivflm mHflh H%‘7‘s TOP VTEW PIN I LD oeoooocoooooooeee ooooooooooooooeoo ooooooooooooooeoo ooooooooooooooooo oooooooocoooooooo ooooooecacaoooooo oooooooaacaoooooo cocooooecccoaoooo ooauooccecooanooo ocuuooacccacucooc oouuoooooaccunooo oocoooooooooaaooo eoocooooooooooooo eoocooooooooooeoo ooooaooooocoooeeo oooooocooooooocee ooooooooooooooeoo ooooooooooooeoooc ooooocooooooeoooo oooocoooooooocooo ooooooooooaoooooo ooooooocaoooooooo ooeooocccoooooooo oooooaaccoooooooo ooooocccooouooooo uuoooeeaaoonoouua uuooccoocooaouuuu Dooocccocoonoouuu woooooooooonooooo cocooooocooooooco cooooooocooooooco oouoooooooooeeooo ooooccooooooeoooo ooooocooooooeoooo fi coooooooooooooeeo ooooooooooooaoooo ooooooocaaoaooooo oooeooeeaacoooooo ooooeoeaccaoooooo cocooooocccouoooo ooauooaceaooanooo ouuuooococcounoou oouwoooooooocnooo oocoooooooooaoeoo eoocooooooooooeoo oooooooooccoooeoo oeooooooooooaoueo oooooooooooooooco ooooooooooooooeoo oooooooooooooooce oooooooooooooooo oooooccoooooceooo oooooooooaooooooo ooooooaaaoooooooo ooooceaccoaoooooe ooeooaaccoooooooo ooooocccooouooooo uueocaeaaoonoouua uuooaaoocouaoauuu aoooaaooooonoooau cooooooooooneoooo oooooooccoooeoooo oooooococoooeoooo ooooooooooooceooo oooocooooooocoooo oooocoooooooeoooo oooooooooooooeooo ooooooooaoooooooo ussx SEATING PLANE s L MILLIMETERS g a T E MINI NDM‘ MAXI E A 3‘31 3‘51 371 A: 0‘40 050 men A2 2‘51 3‘01 321 E/I 35 on BASIC 33m) BASIC E 1‘00 BASIC ms use use 070 am 4y 4y 020 (Cc w. w. 035 dad «a w, 030 as? 4,, 4,, mm M 34 E EEEEQEE rrvnnss , sA/Ag/nu suanw BALLS NOTE ALL DTMENSTONS AND TOLERANCES CONFORM TO ANST Y14.5M*1994 2 SYMBOL 'M' TS THE BALL MATRTX STZE 3 CONFORMS TO JEDEC MS*034*AAR 1 Send Feed back
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Chapter 4: Mechanical Drawings
FFVA1156 Flip-Chip, Fine-Pitch BGA (XCKU15P)
X-Ref Target - Figure 4-14
Figure 4-14: Package Dimensions for FFVA1156 (XCKU15P)
ug575_c4_ffva1156_ku15p_041917
(I X|L|NXm BOWOM VLEW TOP VLEW Eiilflafl <4x7 e="" h="" vaflfily="" ”wm="" h="" pm="" 11m="" ”mun="" ‘°2u’57”zs"n"z€“v="" a="" a="" v="" ooaaaoaouaoaoouacoeuooooooauoaaao€="" onoooooooooooooooooooooooonnoooooo="" oooccoeeoooooooocoaeeooooooaocaaeo="" o0aaooooooooooaooooeoooooouuaooooo="" ooocoooooocooouooooooooooeuaaocooo="" odococoooooueoooooooooooecococoooo="" onoooocoooooeooooooooooocouocooooo="" coooooooooooeouacooooooooeuuoooooo="" ocoooooooooooouooooooooooea0000000="" coooooooooooeooeooooooooooauoocooo="" ooeooaooaaoaeouoooooooaooouooooooo="" oocccoccuuoaoouaccecooueooaacoecoe="" ouaacocaeaooooaocoooouoocoucoooaoo="" oooocoeeoooooooocoeoeeoooooooceeee="" ooaaaoeeooooooaacooeoooooouuaooooo="" onoooooooooooouaoooooooooeuaaooooo="" o0acocoooocoooaaooooooocceooaooooo="" onooooooooooeooooooooooooouoaooooo="" ooocoocooooooouoooooooooouoooooooo="" ococooooooooeouoooooooooouuuoooooa="" onocoooooooooouoooooooooooauoooooo="" o00oooooowooeooooooooooooooooooooo="" ooooooooowooeoouoooooowooouuooooog="" ouacaeaooaoooouoaeoouaaooounccoacu="" ooooeocouooooocaccooooooeoaaoaaeoo="" aoooooooooooooooooooooooooonoooooo="" ooocoooeoooooouaaooeooooooaaoooooo="" o0acocooooooooaooooooooooeoucooooo="" odoooooooooooooooooooooooouuoooooo="" ooocoocoooooeooooooooooooooocooooo="" ooocoooooooocouoooooooooouuuoooooa="" ooocoooooooooouaooooooooooauaooooo="" r5="" 5535'="" a‘="" *="" a.)="" ie]="" rrranss="" ,="" ml="" my:="" ball:="" 3="" frknnss="" ,="" gm="" my:="" ball:="" ;="" millimeters="" g="" a="" r="" e="" min‘="" niiim‘="" max‘="" e="" a="" 3‘31="" 3‘51="" 371="" notes'="" 0‘40="" 050="" 060="" '="" 2‘81="" 3‘01="" 3‘31="" 1="" all="" dlmenslons="" and="" tolerances="" conform="" 3qu="" basic="" to="" ansl="" m45m71994="" 3300="" basic="" ,="" ,="" mo="" basic="" 2.="" symbol="" m="" ls="" the="" ball="" matrlx="" slze="" nan="" use="" 070="" 3.="" conforms="" to="" jedec="" m570347aar71="" w="" ”w="" "‘1’="" 0‘30="" 4="" see="" next="" page="" for="" eerehse="" package="" dlmenslons="" (cc="" mu="" (m="" 035="" ddd="" 4y,="" rm="" 0‘30="" 999="" w,="" 4,,="" u="" m="" m="" 34="" 2="" send="" feed="" back="">
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Chapter 4: Mechanical Drawings
FFRA1156 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU15P)
X-Ref Target - Figure 4-15
Figure 4-15: Package Dimensions for FFRA1156 (XQKU15P)
ug575_c4_ffra1156_010718
(I X|L|NXm BOWOM VLEW L—Ifi ”135%.qufizé'uzwfly.‘ Mm'fiflu'“. “ 7 ‘ a ‘ L 1 L TOP VLEW :-<4>0 —l—TI a PIN l I I] oooocooouu Deacon aooeoooo 09000900 00000000 oaooooaoooooooo e a oaooooaeoooaooooo‘ aooooaooeocoooooaoooo oooeuaoooouuooooaooeo :- o o o uaooooooooooaoooo oaooooaooooaoocoo d ocaooooaooeoc unaooonuoooua 0590005900000 ooaoooooooeoo oooooooaoocoo ooaoooouooooooooo ooaooooooocooaooo onooooooeooouaoooo ooaooooaooeooooeooaooou 00005 06000 aooeo ooogaooogaooeooooeoo oouuaoocncooouoaooun ooooaooooaoooooooeoo ooeoooeeooooooauooeo ram- a— ma ; RrAuss 7 ML. mu BALL: ; MILLIMETERS g a r E MIN‘ NEIM‘ MAX‘ E A 3 32 3‘42 3 62 A! 0‘40 0‘50 050 A2 2‘72 2‘92 312 NOTES. El 35 DO BASIC 1 ALL D‘MENS‘DNS AND TOLERANCES CONFORM 3300 REF T0 ANSL V145M71994 IE IUD BASIC 2 SYMBOL 'M‘ ‘5 THE BALL MATR‘X S‘ZE a” “‘5“ ”‘6” 0‘7” 4 3 CONFORMS TO JEDEC M370347AAR4 am: as“ w» 020 CE: W W 035 4. ACTUAL SOLDER BALL COUNT : 1155 add 4., 4» nan 99? w, W/ 0‘10 M 34 2 Send Feed back
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Chapter 4: Mechanical Drawings
RFA1156 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU040)
X-Ref Target - Figure 4-16
Figure 4-16: Package Dimensions for RFA1156 (XQKU040)
ug575_c4_r2_032417
(I X|L|NXm BOWOM V‘EW TOP V‘EW :-<4x) i?!="" i="" e="" my="" ga‘u’wm'="" :="" mu'wwyu="" ;="" pin="" ‘="" ‘="" i‘n‘sy”="" 2="" d="" 2:22s:23:2:gssgggggggggggggsggg°="" acoosoaoooooaoooooooaooooaaeooo="" 0°00soaoooooaaoooooaoeooooooooo="" oncecoaqdooooouo°doan°°doo°e°°="" 0°00onaooooogaoooooaoeooooooooo="" acooonaoooooaaeooooooeoooaooooo="" 050°anaoooanaaoe°aouou°°naaooau="" doe="" oeoooooooo="" aeoo="" aeoeooaooooooaeoe="" oooouucooounaaooo="" ooooooooooooooeoo="" o="" o="" o="" oeooooaooooaaaooog="" o="" o="" o="" aooooouooooo="" oaeeeoaaoooo="" oucououooooouuooo="" oooouuoooouoonooo="" ooooooooooooooooo="" oeooooaoooonaoooo="" oooonuaaooanaauoo="" 00000900aonenuooooonaoooonaoooonn¢="" seating="" plane="" “mada-be="" s="" ermss="" ,="" sum="" mm="" ball:="" l="" millimeters="" g="" a="" t="" e="" min="" ndm="" max="" e="" a="" 332="" 353="" 372="" a)="" 0="" au="" 0="" 50="" 0="" eu="" a2="" 2‘82="" 3‘02="" 322="" notes:="" 35m]="" basic="" 1="" all="" d‘mens‘ons="" and="" tolerances="" conform="" 3300="" ref="" t0="" ans‘="" w="" 4.5m71994="" e="" 100="" basic="" 2="" symbol="" ’m'="" ‘5="" the="" ball="" matr‘x="" s‘ze="" ”b="" 0‘50="" 0‘60="" 0‘70="" 4="" 3,="" conforms="" t0="" jedec="" msiomimriw="" qed="" ”84»="" ’n/="" 020="" w="" w="" w="" 035="" 4.="" actual="" solder="" ball="" count="" :="" 1156="" ddd="" 43,,="" ”y,="" 030="" 5'99="" "va="" ”84/="" u="" 10="" m="" 34="" e="" send="" feed="" back="">
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Chapter 4: Mechanical Drawings
RFA1156 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU060 and XQKU095)
X-Ref Target - Figure 4-17
Figure 4-17: Package Dimensions for RFA1156 (XQKU060 and XQKU095)
ug575_c4_r3_032417
(I X|L|NXm BOWOM vwa 4x TOP MW [3 ' fl—’ ‘ / PIN 1 LD‘ 3 “RS?$2141“?“272%“:zazzxefismn‘fls’fla” n’" 9 " 7 " 5 ‘ a a 1 ioooooonaaooaoooooa oouoooooaooouooont: d ooooooouuaaoooooucu ooooooocuaooooooo oooooooouoooeooooou oooooooauoooooooo ooooooooooooooooooo ooooooooooooooooo ooooooonaooguoooooa oouoogooaoooeooon a o o aoooooouuaaoooooucu ooooooowuaoooooooo oooooooouoooeooooou ooooooocuoooeooooc an o a o aoooooonaaoouoooooa oouoooooaooouooo 5:;«(nmxxrnmmunT \ E H aooooouuunnooooouuu oooocouounnooooou An aooooooouaaooooouwu ooooooowucooooooo m oooooooouoooeoooooo oooooooaooooooooo N ooooooooooaoooooooo ooooooooooooooooo Ax aoooooonaaoouoooooa oouoooooaooouoooa 2: uooouuuuuuuoooouuou ooooouuuuuoooocuu m uaaauuuuuuoaoouuuuu mooauuuuuuuooauuuuu w unooanuunnonaoanuun oneneauunnnnaoanuun AR aoooooooucaooooooou ooooooooucoooooooou w oooooooooooeooooao ooooooocooooeoooociw 3310 :0 MAX LID \ W wanna) C A‘B‘ $ 0999(8) C @4‘7 m» : FFVA1517 7 Sn/Ag/Cu SEILDER BALLS ; MILLIMETERS S FFVC1517 7 Sm/Ag/Cu SEILDER EALLS E , rrvman 7 Sn/Ag/Cu SIIILDER BALLS L MIN‘ NIIIM‘ MAX‘ E A 311 331 351 A; mm 050 men A? 351 231 am D/E 4mm BASIC NOTES: Dx/EJ EEUU BAXIE 9 1m BASIC 1, ALL D‘MENS‘ONS AND TOLERANCES CONFORM an m m am To ASME Y14,5M71994 ”” ”‘3” 2, SYMBOL "M" \5 THE PW MATR‘X S‘ZE. 7~, mm «a 7w 085 "v 7» ~57 0‘25 3, CONFORMS TO JEDEC M870347AAU71 (DEPOPULATED) 7a., 010 M 39 E Send Feed back
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Chapter 4: Mechanical Drawings
FFVA1517, FFVC1517, and FFVD1517 Flip-Chip,
Fine-Pitch BGA (XCKU060, XCKU095, XCVU065,
XCVU080, XCVU095)
X-Ref Target - Figure 4-18
Figure 4-18: Package Dimensions for FFVA1517 (XCKU060),
FFVC1517 (XCKU095, XCVU065, XCVU080, and XCVU095) and FFVD1517 (XCVU080 and XCVU095)
ug575_c4_07_041816
(I X|L|NXm BOWOM vwa 4x TOP MW [3 ' fl—’ ‘ / PIN 1 LD‘ 3 “RS?$2141“?“272%“:fizxefismn‘fls’fla” n’" 9 " 7 " 5 ‘ a Z 1 iaooooonuaoouoooooa oouoooooaooouooont-t d a nun own co 00 once ooooooocuo 00 0000000000 ooooooooooooooooo co coon oouoooooao on a o o aoooooounaaoooooucu ooooooowuaoooooooc oooooooouoooeooooou ooooooocuoooeooooc an o a o aoooooonaooouoooooa oouoooooaooouooo 53((afluxrnmmunw \ E H ooooooooucoooooooou w ooeoooocooooeoooociw aoooooo aaoooooo oo o o 3310 :0 MAX LID \ W EM IIIII ab 69 wanna) C A‘B‘ 0999(8) C FFVC1517 7 Sn/Ag/Cu SDLDER BALLS FFVE1517 7 Sn/Ag/Cu SDLDER EALLS Elm- MILLIMETERS MIN‘ NIIIM‘ MAX‘ A 311 331 351 A; mm 050 men A? 351 231 301 D/E 4mm BASIC NOTES: Dx/EJ 3500 BAXIE 1, ALL D‘MENS‘ONS AND TOLERANCES CONFORM e 100 BASIC an 050 men 07D TO ASME Y14V5M71994 ”w ”‘3” 2, SYMBOL "M" \5 THE PW MATR‘X S‘ZE. «4, mm «a «w 085 w a» w 025 3, CONFORMS TO JEDEC M870347AAU71 (DEPOPULATED) My 010 M 39 E Send Feed back
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Chapter 4: Mechanical Drawings
FFVC1517 (XCVU3P) and FFVE1517 (XCKU11P and
XCKU15P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-19
Figure 4-19: Package Dimensions for FFVC1517 (XCVU3P) and FFVE1517 (XCKU11P and XCKU15P)
(I X|L|NXm BOWOM V‘EW TOP V‘EW aisa€%§‘ufix”eszse123§‘efeang‘iq‘“n“n“u’iu‘" , ' 7 ‘ : ‘ a A L +76 PIN 1 ML igsgggsgzgsszggsggg sagsgggsgggsgwséx n’ §§§§§§§§§§§§§§§§§§§ §§§§§§§§§§ §§§§ H»»{«(zfluxrxummn 2:222 2:222 2:222 gassgggggssgsgsgggs asssgsssggsssgsgsgs 2288828338838888822 gagsgssssgsgszsssgs a 2888228228822888828 8888888882288328838 2888228822832288888 8888882882288388822 if 2222222222232222222 aggggggggggsgzgggzg :: °zgggzzszgzzzgzgzgz :gzgzgzgggzsgzzzga N FFRE1517 7 Sn/Pb SDLDER BALLS FFRC1517 7 Sn/Pk: SEILDER BALLS FFREISN 7 Sw/Pk} SEILDER BALLS MILLIMETERS MIN‘ NIIIM‘ MAX‘ A 331 351 371 m mm 050 [men “2 231 am 321 NOTESi D/E 4U 00 HASH: 1. ALL D‘MENS‘ONS AND TOLERANCES CONFORM M‘ 38‘0“ BASIC TO ASME Y14.5M71994 9 100 BASIC ab 0‘50 new m 2. SYMBOL “M“ ‘8 THE PW MATW S‘ZE. ““0 43‘, ”Na D‘EU W W W 025 3. CONFORMS TO JEDEC MS7O$47AAU71 (DEPOPULATED) m 7» 7» M35 see 7w 7&4 ma M 39 a Send Feed back
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Chapter 4: Mechanical Drawings
FFRC1517 (XQVU3P) and FFRE1517 (XQKU15P)
Ruggedized Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-20
Figure 4-20: Package Dimensions for FFRC1517 (XQVU3P) and FFRE1517 (XQKU15P)
ug575_c4_ffrc1517_ffre1517_010719
(I X|L|NXm BOWOM vwa D M TOP vwa a?"“371saf‘ajlsxlnecuvzisuzaflexgnwmnmlaummu”3 B 7 A a ‘ a E l oaoooooooaoooooooa ooooooaaomooaaa» d ogggggggggggggggggg 88828822888822288835 agssssggggssssggggs ssggggssssggsgsssssg ggzgaggggzsgagggggs sagggggsaggggggsggg: ggzgggggggsggggggzs :gggggsszggggggsggg :3 2228888882288883822 8883822288882822888 r: LID wwtfl) C A\B\ 69 weee® c FLVA1517 7 Sn/Ag/Cu SEILDER BALL: FLVDISU 7 Sh/Ag/Cu SDLDER BALLS MILLIMETERS Mm NEIM‘ MAX‘ A 3 as 3 as 4 09 A; 1140 0‘50 050 “2 319 3 39 359 D/E 4mm BASIC NOTES' WE; EB‘UU BASIC E 100 BASIC 1. ALL D‘MENS‘ONS AND TOLERANCES CONFORM 0 0‘60 070 TO ASME Y146M71994 6k: 05 ”v ”v 03“ 2. SYMBOL "M" \5 THE PW MAW 5ng man ”‘14 ”w 025 m w w 065 3. CONFORMS TO JEDEC M370347AAU4 (DEPOPULATED) 995 4v» «.41 0‘10 M 39 2 Send Feed back
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Chapter 4: Mechanical Drawings
FLVA1517 (XCKU085 and XCKU115) and FLVD1517
(XCKU115 and XCVU125) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-21
Figure 4-21: Package Dimensions for FLVA1517 (XCKU085 and XCKU115) and
FLVD1517 (XCKU115 and XCVU125)
ug575_c4_08_010715
(I X|L|NXm 50mm vwa m 020 M TOP V‘EW r—-—‘ P IN 1 LD‘ 31"2i‘n’S9E.’iu'haha‘gfaaxgfiv"u“u“uRu" ‘ ' 7 ‘ a ‘ a 2 n§§§§§§§§§§§§§§§§§§ §§§§§§§§§§§§§§§§° <5 [ed="" “hmrkiuvx.="" mmwn.="" :wa="" lid="" eh="" l="" a‘="" ”7="" aauatfl)="" e="" a‘b‘="" $9298)="" [2="" man="" 7="" flo/sn="" 5mm="" balls="" millimeters="" mm="" neim‘="" max‘="" a="" 3="" 74="" 3="" 94="" 414="" m="" a="" 40="" u="" so="" n="" an="" a2="" 3‘24="" 3‘44="" 15::="" we="" 4n="" an="" basic="" notes:="" mm="" 35m="" basic="" e="" ina="" basic="" 1,="" all="" d‘mens‘ons="" and="" tolerances="" conform="" to="" asme="" y14‘5mi1994="" ab="" man="" 050="" mu="" "w="" "v="" ”3“="" z.="" symbol="" “m"="" ‘5="" the="" pw="" maw="" 5‘25="" blah="" "51/="" w="" 025="" m="" w="" 0,,="" d25="" 3.="" conforms="" to="" jedec="" m370347aau4="" (depopulated)="" “9="" w,="" w,="" dju="" m="" 39="" 2="" send="" feed="" back="">
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Chapter 4: Mechanical Drawings
RLD1517 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU115)
X-Ref Target - Figure 4-22
Figure 4-22: Package Dimensions for RLD1517 (XQKU115)
ug575_c4_r4_032417
(I X|L|NXm BOWOM WEW TOP V‘EW 020 4X fifi:“’>§‘n’“a€‘affi"‘zf'a755$} x“n“n“|s"n‘zn‘"v”w‘a‘ 1‘ l 122::33:23::s32:23::sggzzszzgsszsszzsssw / PIN 1 L11 “38823882388238823882888388238823882388223 u i :znsnzmmgmen «6mm mmm. SEATING PLANE a i2 Em- fiba‘ WW (8) C MB‘ @222 Q) C 3 FFVA1760 , SH/Ag/Cu SDLDER BALLS ; MILLIMETERS E E T E NDM‘ MAX‘ E 3‘51 371 U50 0‘60 3‘01 321 SD BASIC ‘00 BASIC NOTES: ‘00 BASIC 1, ALL D‘MENS‘ONS AND TOLERANCES CONFORM 0‘60 070 TO ASME Y14.5M71994 ”‘k 0‘30 2. SYMBOL "M" ‘5 THE P‘N MATR‘X 5‘25 as” 025 W 035 3' CONFORMS TO JEDEC M570347AAV71 (DEPOPULATED) 4&4 [110 M 42 2 Send Feed back
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Chapter 4: Mechanical Drawings
FFVA1760 Flip-Chip, Fine-Pitch BGA (XCKU15P)
X-Ref Target - Figure 4-23
Figure 4-23: Package Dimensions for FFVA1760 (XCKU15P)
ug575_c4_ffva1760_ku15p_041917
(I X|L|NXm BOWOM WEW 4X TOP V‘EW @ E r. PIN 1 ID '5I'Dgemewsx’“af'zfl§‘afl fwn",,“n'lu‘“v ' , ‘ 5‘ a t I / £§§§§§§§§§§§§§§§§§§§§ §§§§§§§§§§§§§§§§§§§§z O A 8§§§§§§§§§§§§§§§§§§§§ EIIIBEBIIIIEBIEBL SEATING PLANE L Em- : ; MILLIMETERS g E T E MIN NDM MAX E A 3‘31 3‘51 171 A: mm use 050 A2 8‘81 3‘01 321 EVI 42 50 BASIC @- 41‘00 BASIC NOTES: E L00 BASIC 1 BB 0‘50 0‘50 070 mm w, w 020 2 BBB w, a» 025 dad I» 0,, 025 3' see 4,, 4,, 010 M 42 2 LID I ”k“ mm 09 c A‘B‘ fleei- ® c FFVEUSD * Sn/Ag/Cu SEILDER BALLS ALL D‘MENS‘ONS AND TOLERANCES CONFORM TO ASME WAN/14994 SYMBOL " ‘ ‘8 THE P‘N MATR‘X S‘ZE. CONFORMS T0 JEDEC MSrOMeAAVrT (DEPOPULATED) Send Feed back
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Chapter 4: Mechanical Drawings
FFVB1760 Flip-Chip, Fine-Pitch BGA (XCKU095,
XCVU080, and XCVU095)
X-Ref Target - Figure 4-24
Figure 4-24: Package Dimensions for FFVB1760 (XCKU095, XCVU080, and XCVU095)
ug575_c4_09_041617
(I X|L|NXm EOWOM V‘EW TOP V‘EW ’E‘ x_1 PIN 1 L11 r- E m firki'afie‘nxn‘ai'fls‘z fi'i."n“u"u‘lu".' 1‘ 5‘ ,5 \ .uununwnunuuuawnuunn unuuunuawuuauouawn ‘aanaaaaaamanmanm wannaaamaamanawd. Rampxns‘flz «(mun mum“. .mmnmaamaamama amawaamaamaamaa wee-e ® [2 erweu 7 Sw/Ag/Cu XEILDER BALLS MILLIMETERS MIN‘ NDM‘ MAX‘ A 3 71 391 411 A1 U 4U U 5D [I SD A? 321 3‘41 361 El/I 4250 BASIC EV. 4mm BASIC E 1‘00 BASIC 1. ALL D‘MENS‘ONS AND TOLERANCES CONFORM wk: USO 0‘60 070 T0 ASME Y14V5Mi1994 NOTES: m ”‘V ”‘V 0‘3” 2 SYMBOL "M" \5 THE PW MATR‘X S‘ZE km a» a» 025 mm 0", 0” 025 3 CONFORMS T0 JEDEC MSifXHiMViT (DEPOPULATED) 599 (M W» 010 M 4E E Send Feed back
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Chapter 4: Mechanical Drawings
FLVB1760 Flip-Chip, Fine-Pitch BGA (XCKU085,
XCKU115, and XCVU125)
X-Ref Target - Figure 4-25
Figure 4-25: Package Dimensions for FLVB1760 (XCKU085, XCKU115, and XCVU125)
ug575_c4_111_041615
(I X|L|NXm BOWOM WEW TOP V‘EW 020 4X fifi:“’>§‘n’“a€‘affi"‘zf'a755$} x“n“n“|s"n‘zn‘"v'v‘a‘ 1‘ l 122::33:23::s32:33::sggzzszzgsszzszzsssw / PIN 1 L11 “38823882388238823882888388238823882388223 u i :znsnmmumen («mm mmm. SEATING PLANE a i2 Em- fiba‘ WW (8) C MB‘ @222 Q) C 3 FFVE1760 , SH/Ag/Cu SDLDER BALLS ; MILLIMETERS E E T E NDM‘ MAX‘ E 3‘51 371 U50 0‘60 3‘01 321 SD BASIC ‘00 BASIC NOTES: ‘00 BASIC 1, ALL D‘MENS‘ONS AND TOLERANCES CONFORM 0‘60 070 TO ASME Y14.5M71994 ”‘k 0‘30 2. SYMBOL "M" ‘5 THE P‘N MATR‘X 5‘25 as” 025 W 035 3' CONFORMS TO JEDEC M570347AAV71 (DEPOPULATED) 4&4 [110 M 42 2 Send Feed back
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Chapter 4: Mechanical Drawings
FFVE1760 Flip-Chip, Fine-Pitch BGA (XCKU15P)
X-Ref Target - Figure 4-26
Figure 4-26: Package Dimensions for FFVE1760 (XCKU15P)
ug575_c4_ffve1760_ku15p_042017
(I X|L|NXm BOTTOM VTEW TOP VTEW u‘au 4X I3 —@— PIN 1 Lu 15y‘<9 i»="" add="" w="" w="" 025="" 3‘="" conforms="" to="" jedec="" m37034iaaw4="" (depopulated)="" 99?="" w="" 4»="" 0‘10="" except="" for="" dtmenston="" "moo"="" send="" feed="" back="">
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Chapter 4: Mechanical Drawings
FLVD1924 (XCKU115) and FLVF1924 (XCKU085 and
XCKU115) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-27
Figure 4-27: Package Dimensions for FLVD1924 (XCKU115) and FLVF1924 (XCKU085 and XCKU115)
ug575_c4_10_010715
(I X|L|NXm BOWOM V‘EW fitmwfiamfiflfvg‘a ? TOP V‘EW U‘EU 4X PINIID +- mmuwammmwm ‘ uwauwanwanmnwuux 228338233282233328383 0' uuunuuuauuuauuuunuucilbii “”35“; “(mummmn‘m 1924x : L MILLIMETERS E E T E MIN‘ NDM‘ MAX‘ 5 A 384 4‘04 424 A, 0‘40 0‘50 050 A2 3‘34 3‘54 374 E 4500 BASIC 4300 BASIC El 100 BASIC me 11 SD D so 0 70 man 4,, 4., use blob «M W 035 ow my my mas 9?? w; 4y; 040 M 44 fieeefl) C Rama 7 Sn/Au/Cu smug: BALLS NOTES‘ 1 ALL D‘MENS‘ONS AND TOLERANCES CONFORM TO ASME Y14,5M71994 2, SYMBOL "M" ‘5 THE PW MATR‘X S‘ZE. 3. CONFORMS TO JEDEC MSiOMiAAWiT (DEPOPULATED) Send Feed back
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Chapter 4: Mechanical Drawings
FLGF1924 (XCVU11P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-28
Figure 4-28: Package Dimensions for FLFG1924 (XCVU11P)
ug575_c4_flgf1924_040217
(I X|L|NXm W TOP V‘EW BOWOM ME “‘20 4X @ El E WIN 1 1D "\x‘m"zfi?%fl%fl;‘z ‘a‘!.“n“u“n"n”.',‘ 3‘ :5 .:§§§§§§§§§§§§§§§§§§§ EEEEEEEEEEEEEEEEézsg [5 ZZZZEZZ ZZEZZZZZEZEZZZZZZZZZZ mzmmmzzgmz “ma-“Hamm- 2:22:33 assgsgzsasaassazsm T :EATING PLANE mm: c A‘B‘ flees-fl) c away 7 Wu suLnER BALLS s ; MILLIMETERS g E Y E MIN NEIM MAX E A 3475 3495 4415 A; BAD U450 060 NOTES‘ A2 3425 3445 3465 my 4500 54m 4, ALL 044494540445 AND TOLERANCES CONFORM 43400 REF T0 ASME Y14.5M71994 El 140“ BASIC 2. SYMBOL "M" 43 THE PW MATRLX S‘ZE ma 0 50 D 60 0 7D 3 m W, 4‘, use 3. ACTUAL SOLDER BALL COUNT : 4924 ”b” ”V ”V 095 4 cowrows TO JEDEC 44370347»:er (DEPOPULATED) dad W w 0425 see 4w 4w 0410 M 44 a Send Feed back
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Chapter 4: Mechanical Drawings
RLF1924 (XQKU115) Ruggedized Flip-Chip,
Fine-Pitch BGA
X-Ref Target - Figure 4-29
Figure 4-29: Package Dimensions for RLF1924 (XQKU115)
ug575_c4_r5_032417
TOP V‘EW W 4x U‘ED ,i Ermflfiflfin snrrmga mm c w weee® c FSVH1924 7 Sn/Ag/Cu 3mm BALLS 3 (11 DEPTH) AXM‘SS // bkzb C STIFFENEH BOWOM V‘EW ‘mrahhesaw'nag SEATING PLANE j MAX Send Feed back (DEPOPULATED) SECT‘ON AiA ALL D‘MENS‘ONS AND TOLERANCES CONFORM TO ASME Y145M71994 2, SYMBOL "M" ‘3 THE PW MATR‘X S‘ZE 3 CONFORMS TO JEDEC M570347AAW71 1. NOTES: 4‘51 060 4 01 L09 0 7n u 30 0‘25 025 (no NEIM 4‘31 man 3 81 089 060 mu BASIC 44 MILLIMETERS MIN 411 0‘40 3 ex 059 (I X|L|NXm ISEAX 4500 BASIC 431m EASIC ”84/ 4w 4‘, w, m, w 4., 4» 050 a a a bb a A; A2 A El- E/I El we a
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Chapter 4: Mechanical Drawings
FSVH1924 (XCVU31P) Flip-Chip, Fine-Pitch, Lidless
with Stiffener Ring, BGA
X-Ref Target - Figure 4-30
Figure 4-30: Package Dimensions for FSVH1924 (XCVU31P)
(I X|L|NXm BOWOM VIEW DIED 4X TOP VIEW E E —@—I‘EI PIN 1 [D mymfimaxrafi ,"a‘fi."n“n"n'=u“.'w' v ,1 . I mm;zmmmmn:m<«w~mmxm=n km="" [3="" i="" uh="" i="" al="" i“="" j="" 21m="" seating="" plane="" s="" ;="" millimeters="" n="" g="" i="" l="" ncim‘="" maxi="" e="" 3‘66="" 386="" 050="" 060="" 3‘16="" 336="" 50="" basic="" ‘00="" basic="" iou="" basic="" 0‘60="" (170="" 4y.="" oed="" w="" 025="" w="" 025="" ”so="" 010="" i,="" ei‘ii"="" inky—fl="" i="" mm="" c="" aiei="" $¢eee®="" c="" rrwam="" ,="" sn/ag/eu="" mm="" am:="" frvaeuu="" ,="" sn/ag/cu="" mm="" mm="" notes:="" all="" dimensions="" and="" iolerances="" conform="" io="" asme="" viismi‘iqs‘i="" .="" symbol="" "m"="" is="" the="" pin="" matrix="" size="" conforms="" to="" jedec="" msiom="" aayi2="" (depopulated)="" send="" feed="" back="">
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Chapter 4: Mechanical Drawings
FFVA2104 (XCVU080 and XCVU095) and FFVB2104
(XCKU095, XCVU080, and XCVU095) Flip-Chip,
Fine-Pitch BGA
X-Ref Target - Figure 4-31
Figure 4-31: Package Dimensions for FFVA2104 (XCVU080, and XCVU095) and
FFVB2104 (XCKU095, XCVU080, and XCVU095)
ug575_c4_11_010715
(I X|L|NXm TOP V‘Ew MV m 1 1n Semsn nan 4x [E] :Euuxumwuflfiu wwwfinfieuym 21u4x FHaAamo , Sn/hg/Cu sums»: am: SEATING PLANE m E m U W M R mm 0 D F ( W 2 E, c mm B A m WA, A W30 R AOU E M :0 m4me 9P 0 D9 CE NWEEN A, HDE MTEM MSSJW 4‘0 wwu TR MYM 80 EE; Mfr WMmWW gamma HOYOX ATSCE S 1. 2.3. T O N X404 0055 S A257 7322M R M403mmcuouou E 83m T M AAA 404 a E DDSSEBBewwwwe M N403000u 4 I 500 L ‘ ESL L N404S4 U I IBA3 5 M M303 U 12! made AAA/ anus E abug Send Feed back
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Chapter 4: Mechanical Drawings
FHGA2104 (XCVU13P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-32
Figure 4-32: Package Dimensions for FHGA2104 (XCVU13P)
ug575_c4_fhga2104_vu13p_041917
TOP VTEW 52mm mazm 7 Sn/Ag/Cu suLnER BALLS macaw 7 Snug/cu suLnER ML: pm 1 1994 n‘ao 4x (mm VTEW (I X|L|NXm ALL DTMENSTONS AND TOLERANCES CONEDRM T0 ASME YMjM 2. SYMBOL ”M“ TS THE PTN MATRTX STZE 3. CONEORMS TO JEDEC MS I“!!! DEPOPULATED) ( Send Feed back *2 i034iABE EXCEPT FOR DTMENSTON "auu" H S. V E T T I(Era?Iuanpllvvvuflnxvnfiuuuuuuumwwnuunz 0 m N w mmmmm E m Nari .n mmmm m E w mmmm p X 202 005 S w mmmmmm a S A368 7322M m new” m R M403mmcuuuuu ”a. mmmmmm m E M S m a T A A . s M u E 0 fl; E DB56BBB6wwwW/6 mmm M N403000u 4 $33 I 5 0 0 “Eu” L E 5 L m ”33” L N E u 2 S 4 u I I 9 4 4 5 M mmmm M M 3 D 3 a w $33 1 z a n d e “a mmmmmm SVMEDL A A A E w u b d e w xxx E a b a e 21mm
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Chapter 4: Mechanical Drawings
FHGB2104 (XCVU13P) and FHGC2104 (XCVU13P)
Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-33
Figure 4-33: Package Dimensions for FHGB2104 (XCVU13P) and FHGC2104 (XCVU13P)
ug575_c4_fhgb2104_fhgc2104_vu13p_041917
(I X|L|NXm EOWOM WW —I— 9'.,‘s‘Vsa-J‘g‘nxnmz."mma 39%.".7‘m‘h'éum. ' , ' a‘ z 1 TOP V‘EW 4X PIN 1 [D ugzsggzggzzzgasgzszgz 33533533382333333339120 ‘ d ugumzum;mamszr
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Chapter 4: Mechanical Drawings
FLVA2104 (XCKU115 and XCVU125) and FLVB2104
(XCKU115 and XCVU125) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-34
Figure 4-34: Package Dimensions for FLVA2104 (XCKU115 and XCVU125) and
FLVB2104 (XCKU115 and XCVU125)
ug575_c4_114_041615
(I X|L|NXm EOTIOM VIEW E TOP VIEW 0‘20 4x sn-y“;m;a;s;”§‘flf PINIID l—E—m 6 (zmnnzgswuer‘x-mm“ E H x u: emx SEATING MILLIMETERS MINI NDMI MAXI manz 3‘71 3‘91 411 0‘40 0‘50 (160 > p » rmmx
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Chapter 4: Mechanical Drawings
FLVA2104 (XCVU5P and XCVU7P) and FLVB2104
(XCVU5P and XCVU7P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-35
Figure 4-35: Package Dimensions for FLVA2104 (XCVU5P and XCVU7P) and
FLVB2104 (XCVU5P and XCVU7P)
ug575_c4_flvx_040217
(I X|L|NXm BOWOM VIEW nan 4x TOP VIEW —-—‘ E —I:I— Sa‘h‘é:‘°:i'§f§="zfix%%‘ Namamfifinmxru'7‘s»? PM 1 m Iuggggfiggfigfiggggfiggfigfig gagsgsggsgggzggsggggfi r5 Sggggggggggggzgg‘éfiggfig Eggggggggggggggggggggg § i ag§§§§§§5§§§§§§§§§§§§§§ §§§§§§§§§§§§§§§§§§§§3¥ 21U4X m W mm c I I ,1 SEATING PLANE A2 7I addd® C AIEI meee® C mm 7 Sn/Fb mm HALLS 3 rLRaama , snm, smug: am: L MILLIMETERS E E T E NDMI MAXI E 3‘91 4‘11 050 DIED 3‘41 361 5!] BASIC IUU BASIC IUU BASIC I. ALL DIMENSIONS AND IOLERANCES CONEUNM 0‘60 070 I0 ASME YI4V5MiI994 av, 0‘30 2 SYMBOL "M" IS THE PIN MATRIX SIZE NOTES. 4‘“ 0‘35 3 CONFORMS T0 JEDEC M57034 W72 (DEPOPULATED) w 025 mu 0‘10 Send Feed back
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Chapter 4: Mechanical Drawings
FLRA2104 (XQVU7P) and FLRB2104 (XQVU7P)
Ruggedized Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-36
Figure 4-36: Package Dimensions for FLRA2104 (XQVU7P) and FLRB2104 (XQVU7P)
ug575_c4_flra2104_flrb2104_010819
(I X|L|NXm W m p o T n W P x 4 O 2 a ELIE] ivazrnxzxLany.ruvvvunkluummmuA~MuuHMNWMMnxmxr w mmmmmmmmmmmmmmmmcmmmmmmmmmmmm M 1 wwwwwmuwwwwnnwmwwwwwnmw wwwwwuwumwwwwwwwuwwwwu o u a a W I ”wwwummuwflwfifimwfiEfimmumwmwfimfiw Issuzgazzsazz \mraxwwnesgs‘m’vg fiz."i,"n“,a“n“u‘". -,- 5‘ 2‘ LUZ 21u4x I // bbk: C SEATING PLANE mm c AIBI weeecg) c 69 FLGAEIM 7 Sn/Ag/Cu sumo: BALLS NOTES: ALL DIMENSIONS AND TOLERANCES CONFORM IO ASME Y145Mi1994 2V SYMBOL "M" IS THE PIN MATRIX SIZE 1 3V CONFORMS IO JEDEC MSiO34 AAYiZ (DEPOPULATED) 424 0‘60 3 74 0‘70 0‘30 0‘25 0‘25 (110 4‘04 0‘50 354 1‘00 BASIC 0‘60 MILLIMETERS NDM 3‘84 0‘40 334 4750 BASIC 4300 BASIC USU WW Wasp way WW/ 46 SYMBDL A; A2 mm mm bbb ohm E'EE' Send Feed back
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Chapter 4: Mechanical Drawings
FLGA2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-37
Figure 4-37: Package Dimensions for FLGA2104 (XCVU9P)
ug575_c4_flga2104_040217
(I X|L|NXm TOP VIEW 0‘20 4X EOTIOM VIEW E PIN 1 1n :EE7:Ellvvhanfimzflmn: Ip,-«,As,mi-zm'$lwza# Fm.".,"n“u% , 1‘93 Isagsnuzzgsoa: 22232209282 LID MIME) c AIEI weee® c I // km»; (3 SEATING PLANEj ama- 2104X rLaBaJm 7 Sn/Ag/Eu smug: BALLS macaw 7 Sn/Ag/Eu mm BALLS NOTES ALL DIMENSIONS AND IOLERANCES CONFORM T0 ASME Y14.5M*1994 1V 2. SYMBOL HMH IS THE PIN MATRIX SIZE, 7034 AAY72 (DEPOPULAIED) 3. CONFORMS IO JEDEC MS 43? 0‘60 3‘82 070 U BU 025 1325 0‘10 4‘12 050 3 62 1‘00 BASIC 0‘60 MILLIMETEPS 39E 0‘40 3 42 4750 BASIC 4500 BASIC 050 ray, 4» «yr/w WW (may, 46 mm mm dad eas- Send Feed back
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Chapter 4: Mechanical Drawings
FLGB2104 (XCVU160 and XCVU190) and FLGC2104
(XCVU160 and XCVU190) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-38
Figure 4-38: Package Dimensions for FLGB2104 (XCVU160 and XCVU190) and
FLGC2104 (XCVU160 and XCVU190)
ug575_c4_115_120215
(I X|L|NXm TOP VIEW EDTIOM VIEW 0‘20 4x E E H $§n~§r5¥$ffi§fiféfi$3¥flf fifi.“,,”,;x,%“.‘,u'1E FIN 1 m 033883333328323383283 ““Egggggggggggggggaou ‘ O unnonoouoaoouoanoaoou aouoaoouaouoaoouoa ‘ m5mqmnnrkmnw. EIDAX SEATING m C E - weee® c anaamo , st/m mm WI: S mam , swam mm w: ; MILLIMETERS N s I El L NDMI MAXI E 4‘12 432 050 0‘60 3‘62 382 SD BASIC IDU BASIC I00 BASIC NOTES: 0‘60 0‘70 I. ALL DIMENSIONS AND TOLERANCES CONFORM 45V USU T0 ASME YM 5M71994 ’M 0‘35 2 SYMBOL ”M" IS THE PIN MATRIX SIZE W 025 ”w 010 mm bkzb add gee 3 CONFORMS T0 JEDEC M84334 MYi2 (DEPOPULATED) Send Feed back
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Chapter 4: Mechanical Drawings
FLGB2104 (XCVU9P and XCVU11P) and
FLGC2104 (XCVU11P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-39
Figure 4-39: Package Dimensions for FLGB2104 (XCVU9P and XCVU11P)
and FLGC2104 (XCVU11P)
ug575_c4_flgb_vu9p_vu11p_040417
(I X|L|NXm W 02!] 4X w ~—I— Iii—@— PIN 1 m wsrawzisiss‘sfiMa-i ;'z,?“.."n”,a“n"n”.' 7 ‘ v f S§§§§§§§§§§§§§§§§§§§§ ggzagégggéaaéaégggagz‘ r5 z:zmmmmanr«um-"um”- mamam”mm“.mmanmmmnmoa.4 2104X LID SEATING PLANE «mum Am meee® C mam , gm mm m: s ; MILLIMETERS g E T E NDM‘ MAX‘ E 427 4‘47 0‘50 0‘60 3‘77 357 ‘50 BASIC NOTES. ‘00 BASIC 1. ALL D‘MENS‘ONS AND TOLERANCES CONFURM ‘00 BASIC T0 ASME Hmswwm 0‘60 0‘70 2 swam “M" ‘5 THE PW MAW S‘ZE mm mm 41/ 030 W 025 3 CONFORMS TO JEDEC MSiGM AAYiZ (DEPOPULATED) fly. «a mm W 0y 025 99? w w 010 Send Feed back
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Chapter 4: Mechanical Drawings
FLRC2104 (XQVU11P) Ruggedized Flip-Chip,
Fine-Pitch BGA
X-Ref Target - Figure 4-40
Figure 4-40: Package Dimensions for FLRC2104 (XQVU11P)
ug575_c4_flrc2104_010819
(I X|L|NXm 90mm V‘EW mm W E —E— FIN 1 LD‘ firwwvsmfifiaf frzxz'iuun"u“u"um‘ '1 ‘ 3‘ 1‘ A ;;;;;;;;;;;;;;;;;;;§;;: gzégzggggggggsggggsggg °g§§§§§§3§§§§§§§§§§§§§§ E§§§§§E§§§§§E§§E§§E§EE EIDAX Lin // bkzb C & ‘ 4 SEATING PLANE ‘ A . }—'—( A2 j ~A,J @‘W' 1310*“ ‘ dad Ema- ggeggg A‘B‘ rrvcamo , Sn/Ag/Cu mm am: 3 r: MILLIMETERS E 3 T E MIN‘ NDM‘ MAX‘ E A 3‘64 384 4134 A; (140 050 (160 A2 3‘14 3‘34 354 E/l 4750 BASIC NOTES: EJ/l 45““ BASIC 1. ALL D‘MENS‘ONS AND TOLERANCES CONFORM El 100 BASIC T0 ASME Y14,5M*1994 0k) 050 men 070 u u 2 SYMBOL M ‘8 THE PW MATWX S‘ZE. 4.. 020 4y. w ’N/ 0‘25 3' CONFORMS T0 JEDEC MS*U§4 AAYiz (DEPOFULATED) mm ”3/ ”y 025 M 4w 010 Send Feed back
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Chapter 4: Mechanical Drawings
FFVC2104 (XCVU095) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-41
Figure 4-41: Package Dimensions for FFVC2104 (XCVU095)
ug575_c4_18_041716
(I X|L|NXm TOP VIEW 020 4x I3 PIN I I D ................. v.L2”Emuimzmfifinfifi wwwnwwn wumwuwnwwwwwwfiwwmnmmc BOWOM VIEW fis‘tz‘m‘kfiififfikflaflf P:fl."u“5“n“u‘“. '1 ‘ s‘ ,l Ioggsggsgagag EIDAX LID I A waddfl) c Am weee® c EI‘U' wb—H‘ I M // bkib C I Em- SEATING PLANE macaw; 7 Sw/Ag/Eu mm BALLS NOTES: ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M71994 2, SYMBOL "M‘1 ‘5 THE PIN MATRIX SIZE 1. 3. CONFORMS I0 JEDEC M87034 AAYrZ (DEPOPULAIED) NUT: MAX‘ 4‘24 0‘60 3‘74 0‘70 0‘30 0‘25 0‘25 010 NDM‘ 4‘04 050 354 L00 BASIC 0‘60 MILLIMETERS MIN‘ 3‘84 0‘40 334 4750 BASIC 4500 BASIC 050 was“ “A,“ WW way, 46 XVMBDL wk) mm kabk) dud eves- Send Feed back
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Chapter 4: Mechanical Drawings
FLGC2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-42
Figure 4-42: Package Dimensions for FLGC2104 (XCVU9P)
ug575_c4_flgc_vu9p_040417
(I X|L|NXm w m 4X FOP V‘EW E—E—h PIN 1 m {arm-WVE-‘aflryw Ffl."mumw".'v ‘ 3‘ 1‘ . —J mmmimgmqm.mmmm" E E :22: 210M 212928) C ernemo , swam smug: am: MILLIMETERS manz NDM‘ MAX‘ 38‘; 4‘09 42? use use 359 379 Iii/l 4750 BASIC NOTES: may 45‘0” BASIC 1. ALL D‘MENS‘ONS AND TOLERANCES CONFORM El 1‘00 BASIC T0 ASME ¥14,5M4994 file 1350 0‘60 070 am: A, 4, 030 man my I» 025 3, CONFORMS TO JEDEC M57034 AAH (DEPOPULATED) dad W ”y 025 999 as, Irv 0 ID 53 4:. o 1> 1> 1> rnm1
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Chapter 4: Mechanical Drawings
FLVC2104 (XCVU125) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-43
Figure 4-43: Package Dimensions for FLVC2104 (XCVU125)
ug575_c4_117_041615
(I X|L|NXm TOP WEW ,1 A2 7 LID : 0‘20 4X EUWOM v1Ew KW 211110103) [3 wees-Q) C 1 E‘IL Rib—H ‘ T m/cem , Sn/Ag/Cu suLnER am: ALL DWENS‘ONS AND TOLERANCES CONFORM 3. CONFORMS T0 JEDEC MSi034 AAYiZ (DEPOPULATED) K S E M M W M A P M N W 4 1 P U w E V 7 H H M T 1 5 S W 4 1 D H n ”M m E E L S E 1 w 0 E A B m M O Y P H C S T S A Uh W 1. Z 4. 5:211.1.xtvfiuxzmxxumw"nanny, mm w 1‘ Oaaauwuuauaawaaauauaa aaaaaauauaauaawaaauw W. ummmmmmmmmmmwmm mmmfimmmmmmmm an .H ”mmwmmnwnmfiwfimuw“ ”mmflmuummummwfiwww Nara 2 w “mwnwmwflwmwwmwfimwfim “anwmwwwwmflwwfiwwww x M U 1 u D 5 S m ”anwnmfimnxfifi ”mumwfiwfimfiwfiw” E S A 4 6 5 7 3 e e w .n wwwuuwwwuwwwwuwuumwwuww wuwwuwwwuwuunuwuumwwuw M DA M U 3 m m m 0 D 0 U U mu WmwWW“wnuw”MnmWm”WWWw.WWonwwwwnwnwwmwnmnwwnwwww m E S S S 2 222222222222 222222222222 T 1 A A A 2 222222222222 222222222222 P M 1 0 1 0 m 222222222222”: 2W822u222222 E D S 5 A B B B 6 w w w M6 an menwmwfiwfiuwwfifiwfin Mwmwmwwfififimwfiww m M N 3 0 3 U D 0 u 4 “a 22232222922222822223222: 1 I 5 D n ammmmmmmmmmmmmm mmmmmmmmmmmmm m E ‘ z s 1 m 2232222022022 223222022223 E L N 1 U 1 4 4 0 m; uwmmwumwnwmmuwwmflmmnwm memwfimmwumemefimww S T. I 7 A 2 S um Enumafiwfixfiu wafiwwufifimfifiw M M 3 U 3 u _ 222222222222 222222222222 n 2222222222: 22223222222 um wnwnwumfinnmwnwwwuwuwwm wnwnwnwwwwnwnnwnwufiw? 1 z b n b d e 2 22222220222222 222222022222 :vmnuE A A A w n b a e M a... wmwuwwuwuwmwwwwunmuwuww wmwuwwumuwmwwuwwnmuwuw a b d e 1“ ”mmmmmmmmmmmmm mmmmmmmmmmmm M [11.2222222222222222222222 3 Send Feed back
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Chapter 4: Mechanical Drawings
FLVC2104 (XCVU5P and XCVU7P) Flip-Chip,
Fine-Pitch BGA
X-Ref Target - Figure 4-44
Figure 4-44: Package Dimensions for FLVC2104 (XCVU5P and XCVU7P)
ug575_c4_flvc2104_vu5p_vu7p_041917
(I X|L|NXm BOWOM vLEw mp NEW 11 4X 11 “5 *semxmsn A PIN L m new} 371m B 2923 IEX m E ovsnzm : g a) g - A ~ (my “NEWER; H GUIDE HEILE 3" Rm 3mm u 4 / SEATING PLANEj ' Eun- nmzemo , MW mm ALL; A A MILLIMETERS g SYZ‘WzETEZuA rm "-5 w w w w a T E M[N‘ NEIM MAX‘ E ———T 439 459 MA 0‘50 ”‘60 NOTES: 3‘89 409 115 1556 L ALL DLMENSLONS AND TOLERANCES CONFORM 5n BASIC TO ASME Y14.5M4994 ‘00 BASIC 2V SYMBOL “M" Ls THE PW MATRLX SLZE, LUU BASIC 0‘60 0‘70 3, CONFORMS TO JEDEC N570347ABE72 (DEPOPULATED) W W 030 EXCEPT FOR DLMENSLON “m" mob w 4,, 025 m «A w 025 ea? 4y. 43., mm M 46 2 Send Feed back
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Chapter 4: Mechanical Drawings
FIGD2104 (XCVU13P, XCVU27P, and XCVU29P)
Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-45
Figure 4-45: Package Dimensions for FIGD2104 (XCVU13P, XCVU27P, and XCVU29P)
ug575_c4_vu13P_figd2104_102517
3x m ox ussms Euxvz HDLE (nu m um) wdaatfl) C AIEI weee® c TOP vTEw \xax m Fsunzmo 7 SNAD/Cu suLnEE mu Ef—U’ 2110‘“ ‘ ms IAJ : uzu 4x vwxm :iam. NUT: BOTTOM VIEW m,m%¢ws&"zaw nxfi.".,“.,“u'=u'".'n r ,1 SEATING PLANE MAX‘ 4‘59 060 r T r Send Feed back SECTTON AiA IO ASME V14.5M71994 2 SYMBOL "M" TS THE PTN MATRTX STZE. 3 CONFORMS IO JEDEC MSiOM MP? (DEPOPULAIED) 1. ALL DIMENSIONS AND TOLERANCES CONFORM NOTES: 4 09 1‘86 [17!] 0‘30 0‘25 0‘25 [110 NEIM‘ 4‘39 050 3‘89 116 0‘60 46 MILLIMETERS NT MI (I X|L|NXm amox 4750 BASIC 4500 BASIC LUU BASIC 6 9 0 4‘1 0‘4 369 1‘0 4» «a my aw 0,, w 4w 4w 050 A1 A2 mm bbb may see
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Chapter 4: Mechanical Drawings
FSGD2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-46
Figure 4-46: Package Dimensions for FSGD2104 (XCVU9P)
ug575_c4_vu9P_fsgd2104_100717
(I X|L|NXm TOP VTEw BOTTOM VTEW mun 9 2 mm E: H. [Ti 2.223.: .u-ulanxvximfifluunmwmflnxmzr :x m ox ussms (1112 um um) sum: HDLE ,‘xgsnaawmem; Pawn“ mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm emu mmm NAME) I: A‘E‘ ¢EEE® C E N A L P n. w T A E X rsnnem 7 Sn/Aa/Cu mung: BALLS SECTTON ArA m T m W M W R E W D o '2 c KY, 5 SM M E H N R4 M MN n my w4WM , uwnm mama H mwsJ RN, mMWm mum MVMS W7x EFL" W mufr MMLO Dnmw m u SAmmc EL l W 2 Gr: 2 X9096 0055 S Assfle 7322m R M4041mmmunnuu E mm“ T M909 0 E Basemasaewwwwe M N4031000nm 4 I sun L 151 L N909644 u I 11450 5 M M4u31 0 1:: Luanda svnsuLAAA uh 9M Aw a2? Send Feed back
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Chapter 4: Mechanical Drawings
FSGD2104 (XCVU11P) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 4-47
Figure 4-47: Package Dimensions for FSGD2104 (XCVU11P)
ug575_c4_vu11P_fsgd2104_102517
(I X|L|NXm EOWOM \AEW nan 4x TDP \AEw mun E “awash-$1M a.“ n“u"..”n“.'m‘ .‘ I “sun a 55 max:nagznuutismnn‘“““HV'LH‘WH- f amx SEATING PLANE ‘, . . AP] mama) C A‘E‘ mag; c rswam , MW smug: ms MILLIMETERS [A3 me NEIH [
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Chapter 4: Mechanical Drawings
FSVH2104 (XCVU33P) Flip-Chip, Fine-Pitch, Lidless
with Stiffener Ring, BGA
X-Ref Target - Figure 4-48
Figure 4-48: Package Dimensions for FSVH2104 (XCVU33P)
(I X|L|NXm EOWOM VLEW —l— ‘mnmwsfimm‘ flamu'nwnmkml ,‘ v I! TOP VLEW u‘zu 4x nzn “mm255;“;r:z§5k::s=x“<“"“"lu“"f- mm="" mmmam="" bumwmmmomk="" am="" amx="" seating="" plane="" s="" l="" millimeters="" :="" b="" r="" 5="" min‘="" neim‘="" maxi="" e="" a="" 4‘11="" 4‘31="" 451="" ai="" 0="" 4!]="" n="" so="" u="" an="" a2="" 3‘51="" 351="" 4="" m="" a;="" 089="" use="" 1="" as="" 4750="" basic="" 45w="" basic="" el="" l00="" basic="" 1.="" mo="" 0="" an="" a="" so="" u="" 70="" mm="" w,="" m,="" 0‘30="" 2="" high="" my="" 4.,="" 025="" am="" w="" w="" 025="" 3="" 999="" w="" my="" a="" m="" m="" as="" a="" mam:="" meeeqa)="" c="" fsvhaim="" ,="" sn/ag/eu="" sulnei="" am:="" alel="" ”wnw="" smmnz="" [="" mm="" sectlon="" ara="" notes:="" all="" dlmenslons="" and="" tolerances="" confdrm="" to="" asme="" ymsmaqsm="" symbol="" "m”="" ‘5="" the="" pln="" matrlx="" slze,="" conforms="" t0="" jedec="" m37034="" aa‘f2="" (depopulated)="" send="" feed="" back="">
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Chapter 4: Mechanical Drawings
FSVH2104 (XCVU35P) Flip-Chip, Fine-Pitch, Lidless
with Stiffener Ring, BGA
X-Ref Target - Figure 4-49
Figure 4-49: Package Dimensions for FSVH2104 (XCVU35P)
(I X|L|NXm M VTEW BOTTO TOP VTEW u 20 4x “wu‘wuwwmlnflw 2377x ,1 A2 W T 7 E" ” a mxzm , En/Au/Cu sum am: MILLIMETERS NEIM MAX manz 393 413 D‘SU 0‘60 34:! 3‘63 TDD EASIC ‘00 BASIC TUO BASIC 0‘60 070 0‘30 4w w 025 W 025 4,, 010 NOTES: T ALL DTMENSTONS AND TOLERANCES CONEDRM TO ASME YT45M4994 2. SYMBOL “M" TS THE PTN MATRTX STZE 3. CONEORMS TO JEDEC REFERENCE MSrOMeAEArT (DEPOPULATED) EXCEPT FOR DTMENSTON "qua" Send Feed back
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Chapter 4: Mechanical Drawings
FLGB2377 Flip-Chip, Fine-Pitch BGA (XCVU440)
X-Ref Target - Figure 4-50
Figure 4-50: Package Dimensions for FLGB2377 (XCVU440)
ug575_c4_12_100615
TOP VIEW _—E— 7» A2 i» u E a A w Cum mam. sex ET—IL MN PIN 1 ID 1994 0‘20 4x E AP [E] T A L ~Ar1 ALL DIMENSIONS AND TOLERANCES CONEORM TO ASME YT4‘5M Z SYMBOL "M" IS THE PIN MATRIX SIZE. 3, CONEORMS TO JEDEC MS T. NOTES DEPOPULATED) ( Send Feed back 034*ABE72 on" "u EXCEPT FOR DIM ENSTON Em- MAX 431 D 60 3 81 0‘70 0‘30 0‘25 0‘25 010 SEATING PLANE 0mm VIEW (I X|L|NXm 0‘60 51 MILLIMETERS NDM 411 0 50 3 61 5250 BASIC SU‘UU BASIC MIN 391 D 40 3 41 l‘UU BASIC 4" "8:2 2w W, ’7»; I», 4,, 43, 050 A1 A: SVMEUL A W n” .1 a w, a“. u“ u a“ 91k) uua bkzb dad gee El 2577x
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Chapter 4: Mechanical Drawings
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU190)
X-Ref Target - Figure 4-51
Figure 4-51: Package Dimensions for FLGA2577 (XCVU190)
ug575_c4_13_101215
(I X|L|NXm W M 0‘30 4X .5 —TE— : m 1111 “3232232332323323223232 gggggggggggggggggggggg. . I 35555Efffiiiffffifi‘iififi §§§§§§§§§§§§§§§§§§§§§§§§§ . [a] as77x 7‘ SEATING PLANE ‘ A2 W T j am. ET— “J .m was" , WW sum ms 5 ; MILLIMETEPS g E T 5 MIN‘ NDM‘ MAX‘ E A 3‘84 4‘04 424 A; o 40 u 50 u an A2 3‘34 3‘54 374 NOTES WI 5350 BASIC T. ALL DTMENSTONS AND TOLERANCES CONFORM mi 51100 BASIC To ASME YT45M71994 El 1‘00 BASIC z SYMBOL "M" Ts THE PTN MATRTX STZE 21k) use use 070 454/ 0‘30 5, CONFORMS TD JEDEC MS:O§3*ABF*Z [DEPOPULATEM km W] M 025 EXCEPT FOR DTMENSTON uuu ”y w, W 025 4 THS PACKAGE APPUES TO UHWSCU‘6+ XCVUBP & XCVUTSP DEWCES ”so [110 Send Feed back
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Chapter 4: Mechanical Drawings
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU9P and
XCVU13P)
X-Ref Target - Figure 4-52
Figure 4-52: Package Dimensions for FLGA2577 (XCVU9P and XCVU13P)
ug575_c4_flga2577_040217
(I X|L|NXm TOP \AEW 0mm V‘EW PIN 1 m nee 4x 2577x XEATING PLANE Em!- er2577 7 Sn/Aa/cu mum: BALLS DEPOPULATED) ( M R O F W 2 E c mm B A m mu. R , 3c M MOu E M ,u L S, W4WMN D%FC© NWEEM A, HDE SMTrJLM 5 \ N.B D mm” mR YM 0 N ‘ S wg‘ NF \ML T :w : mOWOX S ATSCE m 1 23 N war: 2 X404 0055 S AMéé 7322M R M u3mmc0uu00 E fiSfl T M AA 404 D E 2356:} M N3DBUUDU 1 sun L ‘ EDL L NAD4SS U T. I742 S M M303 u 12 babae vaBnL abueM f2 Ewan: Send Feed back
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Chapter 4: Mechanical Drawings
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU11P)
X-Ref Target - Figure 4-53
Figure 4-53: Package Dimensions for FLGA2577 (XCVU11P)
ug575_c4_flga2577_vu11p_040217
(I X|L|NXm EUWOM WEW EIEZD «X m \AEW 0‘5 *SEmHM 4 a A { A -.-u-.“..'.,~.r,-.*.-,‘..-.. .~.,-.,-‘.w-,.w.'nn.- , } §§§§§aaaasgggaaaaggggaaaa ggsgsaaagggaaaaaaggggaaaa .; > ma§§s§§§§8§§§s§m§§§s §§§§§§§a§§§§§§s§§§§§§§§§§ :- Hex $2;;;;;;;;;;;;;;;;;;;; 22;;;;;;;;;;;;;;;;;;;;; i, [a [a L7 ~ 3§§§§§§§§a§§§§ifizea§§§§§§ ssa . °::s::::::zs::::zz::::: as: V é - m- m axing?) 2577x ”7 n 4L 5mm ME A: lama- Mum: m i a m M MILLIMETERS N mm a g (A: mm“ W W Fm W n 7 1 , , L MIN MAX‘ E . 1 INWWMWWWWWWWWWWWWWW v 4 31 4 51 0‘50 050 W 381 Am L16 1‘25 ‘50 BASIC ‘00 BASIC 1 ALL D‘MENS‘ONS AND TOLERANCES CONFORM ‘00 BASIC T0 ASME mummy 0‘5“ 0‘70 z. SYMBOL "M" ‘5 THE PW MAW S‘ZE. 030 w 3 CONFORMS TO JEDEC MS*034*AEF*2 (DEPOPULATED) 4» W’ ”V” 025 EXCEPT FOR D‘MENS‘ON "aaa" add I» I» 025 «y see 4., 010 M 51 2 NOTES: nno mm Send Feed back
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Chapter 4: Mechanical Drawings
FSGA2577 Flip-Chip, Fine-Pitch BGA
(XCVU13P, XCVU27P, and XCVU29P)
X-Ref Target - Figure 4-54
Figure 4-54: Package Dimensions for FSGA2577 (XCVU13P, XCVU27P, and XCVU29P)
(I X|L|NXm 90mm V‘EW «marmmmgumnv .v . 0 , . TOP WM 020 4x IE mum 2692X W m s \ 7x SEATWG PLANE A U—y—{J 77777777771" lav—IL _H r ' EEEEI. A' “’ ‘JIEIE muss: 7 sn/Ag/Cu some»: BALLS s ; M‘LUMETERS N a ‘2 (L) MW, NOM, MAX, E A 3.73 3.95 4.13 . A! 040 0.50 0.50 NOTES E:- 32; 0554;8‘363 1, ALL D‘MENS‘ONS AND TOLERANCES CONFORM mg 5100 SAN TO ASME Y14,5M4994 El 1-00 SAW 2, SYMBOL "M” \8 THE PW MATW SEE m; 050 060 0.70 a 4y, 030 3. CONFORMS TO JEDEC M87034 A864 (DEPOPULATED) m «y 4,. 0.25 EXCEPT FOR D‘MENS‘ON ”sou" ddd 0y “Ar 0.25 see aw ”84/ 010 M 54 2 Send Feed back
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Chapter 4: Mechanical Drawings
FLGA2892 Flip-Chip, Fine-Pitch BGA (XCVU440)
X-Ref Target - Figure 4-55
Figure 4-55: Package Dimensions for FLGA2892 (XCVU440)
ug575_c4_14_100615
(I X|L|NXm 50mm VTEW TOP VTEW : 0‘20 4x I3 I —@—.m ~ 4x p; ”H2123 ‘ ‘ m \_> 0 :m (r T o m o T sun ’ ‘ \. i, 4‘ '\, 4X nIIIIIIIIII Illllllllll n .. .. - 5m , .. 1 n . . 291$ vm - ., .. zaszx SEATING PLANE AXmLSS “ (1‘1 DEPTH) 3* R” nmm ,1 AZ ,j M w " m A -Im MILLIMETERS MINT NEIM‘ MAX‘ A A11 431 451 M (Ma D‘SU D‘sn A2 3‘51 331 ml A: 0‘89 039 L09 EV. 5500 EASIC EVE! 53mm BASIC E 1‘00 BASIC an 050 0‘50 070 nan w; W D 30 high 4v, 4v, D 25 dad r», W U 25 m w a» mu M 54 rswaage 7 Sn/Ag/Eu 3mm am: 5- A mml E r 3 ‘ m , , n mu W SECTTON AiA STIFFENER 1 NOTES: T ALL DTMENSTONS AND TOLERANCES CONFORM TO ASME MAST/171994 2, SYMBOL "M" TS THE PTN MATRTX STZE 3, CONFORMS TO JEDEC M87034 A8671 (DEPOPULATED) EXCEPT FOR DTMENSTON "uuu" Send Feed back
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Chapter 4: Mechanical Drawings
FSVH2892 (XCVU35P) Flip-Chip, Fine-Pitch, Lidless
with Stiffener Ring, BGA
X-Ref Target - Figure 4-56
Figure 4-56: Package Dimensions for FSVH2892 (XCVU35P)
(I X|L|NXm BOWOM V‘EW TOP WEW A n20»- inan n n n n n n n A " J 1'. 35:15 1 Sun , n n AxmLss ” aasax (1‘1 DEPTH) 3* “‘7 mm y—y—y—Tl/ mm c 1 T /_5 T SEATING PLANE i A LII—T—T Ag 1 : L MILLIMETERS E ‘5 r SECTTON AeA L MIN NEIM MAX E NOTES: 7 A 411 431 451 Ax 040 050 BED A; 351 381 Am NOTES: A: DB9 0‘39 109 my: 5500 mm 1 ALL DTMENSTONS AND TOLERANCES CONFORM EV- 53“ BASIC To ASME ¥145M4994 El [DD BASIC a»: use Dem 070 2. SYMBOL “M" Ts THE PW MATRTX STZE mm Z Z 3:: 3. CONFORMS To JEDEC marosg A8671 (DEPOPULATED) m w w 025 EXCEPT FOR DTMENSTON uuu “5 My w, 010 M 54 a Send Feed back
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Chapter 4: Mechanical Drawings
FSVH2892 (XCVU37P) Flip-Chip, Fine-Pitch, Lidless
with Stiffener Ring, BGA
X-Ref Target - Figure 4-57
Figure 4-57: Package Dimensions for FSVH2892 (XCVU37P)
(I X|L|NX.
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Chapter 5
Package Marking
Introduction
The package top-markings for the UltraScale™ and UltraScale+™ devices are similar to the
examples shown in Figure 5-1, Figure 5-2, Figure 5-3, and Figure 5-4. Figure 5-1 and
Figure 5-2 show both old and changed top markings. In addition to the markings explained
in Table 5-1, refer to the FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+
Products (XTP424) [Ref 12].
The package top-markings for the XQ Kintex UltraScale+ and XQ Virtex UltraScale+ devices
are as shown in Figure 5-5. On XQ products only the Xilinx logo and the 2D bar code are
marked.
(I X|L|NXm KINTEX UltraScaleTM FFVA ‘7, DXX .—, Samp‘e XILINX® KINTEX® UltraScak-z-TM D 7% XCKUOAOTM 74» FFVAHSéXXXYYWW DXXXXXXXA <—i send="" feed="" back="">
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Chapter 5: Package Marking
X-Ref Target - Figure 5-1
Figure 5-1: Kintex UltraScale Device Package Marking
ug575_c5_01_062217
XCKU040TM
FFVA1156xxxYYWW
DXXXXXXXA
1C ES
XILINX
®
®
Operating Range
Date Code
Lot Code
Engineering Sample
Device Type
Package
Speed Grade
Device Type
Package
2D Bar Code
Date Code
Lot Code
(I X|L|NXm Samp‘e XILINX® VIRTEX® UltraScale‘M ’4’ XCVUO95TM FFVD1924XX>
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Chapter 5: Package Marking
X-Ref Target - Figure 5-2
Figure 5-2: Virtex UltraScale Device Package Marking
XCVU095TM
FFVD1924xxxYYWW
DXXXXXXXA
1C ES
XILINX®
UltraScaleTM
Operating Range
Date Code
Lot Code
Engineering Sample
Device Type
Package
Speed Grade
VIRTEX®
ug575_c5_02_062217
Device Type
Package
2D Bar Code
Date Code
Lot Code
(I X|L|NXm Dewce Type i Package i XILINX® KINTEX® UltraScale+TM XCKU15F’TM FFVEI760xxx i Mask Code i 20 Bay Cade Dewce Type i Package i XILINX® VIRTEX® UItraScale+TM XCVU9PTM FLGBZKMXXX i Mask Code 7 2D Bay Code Send Feed back
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Chapter 5: Package Marking
X-Ref Target - Figure 5-3
Figure 5-3: Kintex UltraScale+ Device Package Marking
ug575_c5_03_031917
X-Ref Target - Figure 5-4
Figure 5-4: Virtex UltraScale+ Device Package Marking
ug575_c5_04_031917
(I X|L|NXm Logo Coumry Of Ongm % XILINX® —7i 2!) Bar Code Send Feed back
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Chapter 5: Package Marking
X-Ref Target - Figure 5-5
Figure 5-5: XQ Kintex UltraScale+ and XQ Virtex UltraScale+ Device Package Marking
ug575_c6_030519
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Chapter 5: Package Marking
Table 5-1: XC Device Marking Definition—Example
Item Definition
Xilinx Logo Xilinx logo, Xilinx name with trademark, and trademark-registered status.
Family
Brand Logo
Device family name with trademark and trademark-registered status. This line is optional and could
appear blank.
1st Line Device name.
2nd Line • Package code: FF
1st digit: F for flip-chip BGA, S for flip-chip BGA with 0.8 mm ball pitch.
2nd digit: F for lidded, L for lidded SSI, B for bare-die, H for overhang SSI, S for lidless SSI
stiffener, and I for overhang lidless SSI stiffener.
• 3rd digit: Pb-free code: V for RoHS 6/6, G for RoHS 6/6 with exemption 15, or for packages with
eutectic BGA balls (R or Q).
All commercial (XC) UltraScale Architecture devices have Pb-free RoHS compliant packaging. For
more details on Xilinx Pb-free and RoHS compliant products, see: www.xilinx.com/pbfree.
• 4th digit: This is the pin out (net list) identifier.
• 5th–8th digits: These are the physical pin count identifiers: A1156 and D1924 are shown in the
Figure 5-1 and Figure 5-2 example marking drawings. Example: A package code of FFVA1517
and FFVC1517 means they have a different pinout (net list) but the same physical ball count and
physical dimensions.
• Three letter circuit design revision, the location code for the wafer fab, and the geometry code
(xxx). Designated as the mask code in some figures.
• When marked, the date code: YYWW (two digit year and work week). This code is not marked
on some devices. Refer to the bar code for more information.
3rd Line When marked, this line describes ten alphanumeric characters for assembly location, 7-digit lot
number, and step information. The last digit is usually an A or an M if a stepping version does not
exist.
This line is not marked on some devices. Refer to the bar code for more information.
4th Line When marked, this line describes the device speed grade (1) and temperature operating range (C).
When not marked on the package, the product is considered to operate at the extended (E)
temperature range.
If a bar code is present on the device, the 4th line might be blank or unmarked. In this case, refer
to the bar code for speed grade and temperature range information. For more information on the
ordering codes, see the UltraScale Architecture and Product Overview (DS890) [Ref 1].
Other variations for the 4th line:
L1I The L1I indicates a -1LI device. The -1LI speed grade offers reduced maximum power
consumption. For more information, see the specific device’s data sheet [Ref 3].
1C xxxx The xxxx indicates a 4-digit SCD device option. An SCD is a special ordering code
that is not always marked in the device top mark.
1C ES
2E ES
L1I ES
The addition of an ES after the operating temperature range code indicates an
engineering sample.
Bar Code A device-specific bar code is marked on each device. Refer to the FAQ: Top Marking Change for 7
Series, UltraScale, and UltraScale+ Products (XTP424) [Ref 12].
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Chapter 6
Packing and Shipping
Introduction
The UltraScale and UltraScale+ devices are packed in trays. Trays are used to pack most of
Xilinx surface-mount devices since they provide excellent protection from mechanical
damage. In addition, they are manufactured using anti-static material to provide limited
protection against ESD damage and can withstand a bake temperature of 125°C.
Table 6-1: Standard Device Counts per Tray and Box
Package Maximum Number of
Devices Per Tray
Maximum Number of
Units In One Internal Box
FBVA676, RBA676 40 200
FFVA676, FFVB676, RRFB676 40 200
SFVA784, SFVB784, SFRB7784 60 300
FBVA900 27 135
FFVD900, FFVE900 27 135
FFVA1156, RFA1156, FFRA1156 24 120
FFVA1517, FFVC1517, FFVD1517, FFVE1517,
FFRC1517, FFRE1517 21 105
FLVA1517, FLVD1517, RLD1517 21 63
FFVA1760, FFVB1760, FFVE1760 12 60
FLVB1760 12 36
FLVD1924, FLVF1924, RLF1924 12 36
FLGF1924 12 36
FSVH1924 12 36
FFVA2104, FLVA2104, FLGA2104, FLRA2104
FFVB2104, FLVB2104, FLGB2104, FLRB2104
FFVC2104, FLVC2104, FLGC2104, FLRC2104
12 36
FHGA2104, FHGB2104, FHGC2104
FIGD2104 10 30
FSGD2104 12 36
FSVH2104 12 36
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Chapter 6: Packing and Shipping
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC, and the third digit in the package name is Q (for example: FFQA1156).
FLGB2377 10 30
FLGA2577 10 30
FSGA2577 10 30
FLGA2892 10 30
FSVH2892 10 30
Table 6-1: Standard Device Counts per Tray and Box (Cont’d)
Package Maximum Number of
Devices Per Tray
Maximum Number of
Units In One Internal Box
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Chapter 7
Soldering Guidelines
Soldering Guidelines
To implement and control the production of surface-mount assemblies, the dynamics of the
Pb-free solder reflow process and how each element of the process is related to the end
result must be thoroughly understood.
RECOMMENDED: Xilinx recommends that customers qualify their custom PCB assembly processes
using package samples.
The primary phases of the Pb-free reflow process are:
• Melting the particles in the solder paste
• Wetting the surfaces to be joined
• Solidifying the solder into a strong metallurgical bond
The peak reflow temperature of a plastic surface-mount component (PSMC) body should
not be more than 250°C maximum (260°C for dry rework only) for Pb-free packages (220°C
for eutectic packages), and is package size dependent. For multiple BGAs in a single board
and because of surrounding component differences, Xilinx recommends checking all BGA
sites for varying temperatures.
The infrared reflow (IR) process is strongly dependent on equipment and loading.
Components might overheat due to lack of thermal constraints. Unbalanced loading can
lead to significant temperature variation on the board. These guidelines are intended to
assist users in avoiding damage to the components; the actual profile should be
determined by those using these guidelines. For complete information on package
moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC
Standard J-STD-020C.
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Chapter 7: Soldering Guidelines
Sn/Pb Reflow Soldering
Figure 7-1 shows typical conditions for solder reflow processing of Sn/Pb soldering using
IR/convection. Both IR and convection furnaces are used for BGA assembly. The moisture
sensitivity of PSMCs must be verified prior to surface-mount flow.
Notes for Figure 7-1:
1. Maximum temperature range = 225°C (body). Minimum temperature range = 205°C
(leads/balls).
2. Preheat dwell 95–180°C for 120–180 seconds.
3. IR reflow must be performed on dry packages.
X-Ref Target - Figure 7-1
Figure 7-1: Typical Conditions for IR Reflow Soldering of Sn/Pb Solder
ug575_c7_01_010719
Time (s)
Temperature (°C)
2–3°C/s
Preheat & drying dwell
120–180 s between
95–180°C (Note 2)
TMAX (body) = 225°C
TMAX (leads) = 235°C
t183
60s < t183< 120s
applies to lead area
T = 183°C
Ramp down
1–3°C/s
<1 C/s
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Chapter 7: Soldering Guidelines
Pb-Free Reflow Soldering
Xilinx uses SnAgCu solder balls for BGA packages. In addition, suitable material are
qualified for the higher reflow temperatures (250°C maximum, 260°C for dry rework only)
required by Pb-free soldering processes.
Xilinx does not recommend soldering SnAgCu BGA packages with SnPb solder paste using
a Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow
temperature of 220°C. At this temperature range, the SnAgCu BGA solder balls do not
properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields
can be compromised.
The optimal profile must take into account the solder paste/flux used, the size of the board,
the density of the components on the board, and the mix between large components and
smaller, lighter components. Profiles should be established for all new board designs using
thermocouples at multiple locations on the component. In addition, if there is a mixture of
devices on the board, then the profile should be checked at various locations on the board.
Ensure that the minimum reflow temperature is reached to reflow the larger components
and at the same time, the temperature does not exceed the threshold temperature that
might damage the smaller, heat sensitive components.
Table 7-1 and Figure 7-2 provide guidelines for profiling Pb-free solder reflow. In general, a
gradual, linear ramp into a spike has been shown by various sources to be the optimal
reflow profile for Pb-free solders (Figure 7-2). This profile has been shown to yield better
wetting and less thermal shock than conventional ramp-soak-spike profile for the Sn/Pb
system. SnAgCu alloy reaches full liquidus temperature at 235°C. When profiling, identify
the possible locations of the coldest solder joints and ensure that those solder joints reach
a minimum peak temperature of 235°C for at least 10 seconds. Reflowing at high peak
temperatures of 260°C and above can damage the heat sensitive components and cause the
board to warp. Users should reference the latest IPC/JEDEC J-STD-020 standard for the
allowable peak temperature on the component body. The allowable peak temperature on
the component body is dependent on the size of the component. Refer to Table 7-2 for
peak package reflow body temperature information. In any case, use a reflow profile with
the lowest peak temperature possible.
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Chapter 7: Soldering Guidelines
Table 7-1: Pb-Free Reflow Soldering Guidelines
Profile Feature Convection, IR/Convection
Ramp-up rate 2°C/s maximum
1°C/s maximum for lidless packages with stiffener ring
Preheat Temperature 150°–200°C 60–120 seconds
Temperature maintained above 217°C 60–150 seconds (60–90 seconds typical)
Time within 5°C of actual peak temperature 30 seconds maximum
Peak Temperature (lead/ball) 230°C—245°C typical (depends on solder paste, board
size, component mixture)
Maximum Peak Temperature (body) 240°C—250°C, package body size dependent (see specific
device data sheets [Ref 3])
Ramp-down rate 2°C/s maximum
Time 25°C to Peak Temperature 3.5 minutes minimum, 5.0 minutes typical, 8 minutes
maximum
X-Ref Target - Figure 7-2
Figure 7-2: Typical Conditions for Pb-Free Reflow Soldering
Wetting time = 60–150 s
217
t
217°C
Ramp up:
2°C/s max (1°C/s max for
lidless packages with stiffener ring)
150–200°C
Time (s)
Preheating
60–120s
Ramp down 2°C/s max
Temperature (°C)
ug575_c7_02_081017
Tbody (MAX) = 240–250°C (package type dependent)
Tlead (MIN) = 230–245°C (10s minimum)
See data sheet for maximum value by package type
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Chapter 7: Soldering Guidelines
For sophisticated boards with a substantial mix of large and small components, it is critical
to minimize the ΔT across the board (<10°C) to minimize board warpage and thus, attain
higher assembly yields. Minimizing the ΔT is accomplished by using a slower rate in the
warm-up and preheating stages. Xilinx recommends a heating rate of less than 1°C/s during
the preheating and soaking stages, in combination with a heating rate of not more than
3°C/s throughout the rest of the profile.
Table 7-2: Peak Package Reflow Body Temperature for Xilinx Packages
(Based on J-STD-020 Standard)
Package Product
Category
Peak Package Reflow
Body Temperature(1) JEDEC Moisture
Sensitivity Level (MSL)
FBVA676
FFVA676, FFVB676
SFVA784, SFVB784
XC Mass reflow: 250°C
Dry rework: 260°C 4
FBVA900
FFVD900, FFVE900
FFVA1156
FFVA1517, FLVA1517, FFVC1517,
FFVD1517, FLVD1517, FFVE1517
FFVA1760, FFVB1760, FLVB1760,
FFVE1760
FLVD1924, FLVF1924, FLGF1924
FFVA2104, FLVA2104, FLGA2104,
FHGA2104
FFVB2104, FLVB2104, FLGB2104,
FHGB2104
FFVC2104, FLVC2104, FLGC2104,
FHGC2104
FLGB2377
FLGA2577
FLGA2892
All Mass reflow: 245°C
Dry rework: 260°C 4
FSVH1924
FSGD2104, FIGD2104, FSVH2104
FSGA2577
FSVH2892
All Mass reflow: 240°C
Dry rework: 260°C 4
RBA676, RFA1156, RLD1517, RLF1924
FFRB676, SFRB784
FFRA1156, FFRC1517, FFRE1517
FLRA2104, FLRB2104, FLRC2104
XQ(2) Mass reflow: 225°C
Dry rework: 235°C 4
Notes:
1. See the specific UltraScale and UltraScale+ device data sheets [Ref 3] for the most up-to-date specifications.
2. For devices with the Pb-free signifier in the package name (labeled as Q vs. V) use the temperatures and MSL listed
for the XQ product category.
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Chapter 7: Soldering Guidelines
It is also important to minimize the temperature gradient on the component, between top
surface and bottom side, especially during the cooling down phase. The key is to optimize
cooling while maintaining a minimal temperature differential between the top surface of
the package and the solder joint area. The temperature differential between the top surface
of the component and the solder balls should be maintained at less than 7°C during the
critical region of the cooling phase of the reflow process. This critical region is in the part of
the cooling phase where the balls are not completely solidified to the board yet, usually
between the 200°C–217°C range. To efficiently cool the parts, divide the cooling section
into multiple zones, with each zone operating at different temperatures.
Post Reflow/Cleaning/Washing
Many PCB assembly subcontractors use a no-clean process in which no post-assembly
washing is required. Although a no-clean process is recommended, if cleaning is required,
Xilinx recommends a water-soluble paste and a washer using a deionized-water. Baking
after the water wash is recommended to prevent fluid accumulation.
Cleaning solutions or solvents are not recommended because some solutions contain
chemicals that can compromise the lid adhesive, thermal compound, or components inside
the package.
Conformal Coating
Xilinx does not have information regarding the reliability of flip-chip BGA packages on a
board after exposure to any specific conformal coating process. Therefore, any process
using conformal coating should be qualified for the specific use case to cover the materials
and process steps.
Ruggedized XQ packages are designed to support conformal coating, with vented lids that
ensure proper cleaning can occur after the etching process and prior to conformal coating.
RECOMMENDED: When a conformal coating is required, Parylene-based material should be used to
avoid potential risk of weakening the lid adhesive used in Xilinx packages.
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Chapter 8
Recommended PCB Design Rules for BGA
Packages
BGA Packages
Xilinx provides the diameter of a land pad on the package side. This information is required
prior to the start of the board layout so the board pads can be designed to match the
component-side land geometry. The typical values of these land pads are described in
Figure 8-1 and summarized in Table 8-1 for 1.0 mm pitch packages. For Xilinx BGA
packages, non-solder mask defined (NSMD) pads on the board are suggested to allow a
clearance between the land metal (diameter L) and the solder mask opening (diameter M)
as shown in Figure 8-1. An example of an NSMD PCB pad solder joint is shown in Figure 8-2.
It is recommended to have the board land pad diameter with a 1:1 ratio to the package
solder mask defined (SMD) pad for improved board level reliability. The space between the
NSMD pad and the solder mask as well as the actual signal trace widths depend on the
capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces
are smaller.
X-Ref Target - Figure 8-1
Figure 8-1: Suggested Board Layout of Soldered Pads for BGA Packages
Solder Mask
e
Opening in
Solder Mask (M)
M
L
Solder Land (L)
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Chapter 8: Recommended PCB Design Rules for BGA Packages
X-Ref Target - Figure 8-2
Figure 8-2: Example of an NSMD PCB Pad Solder Joint
Table 8-1: BGA Package Design Rules
Flip-Chip BGA Packages 1.0 mm Pitch 0.8 mm Pitch
Design Rule Dimensions in mm (mils)
Package land pad opening (SMD) 0.53 mm (20.9 mils) 0.40 mm (15.7 mils)
Maximum PCB solder land (L) diameter 0.53 mm (20.9 mils) 0.40 mm (15.7 mils)
Opening in PCB solder mask (M) diameter 0.63 mm (24.8 mils) 0.50 mm (19.7 mils)
Solder ball land pitch (e) 1.00 mm (39.4 mils) 0.80 mm (31.5 mils)
Notes:
1. Controlling dimension in mm.
Land Pad
SMD
M
BGA Package
BGA Solder Ball
Solder Mask
PCB
UG358_aA_02_110513
L
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Chapter 9
Thermal Specifications
Introduction
UltraScale and UltraScale+ devices are offered exclusively in thermally efficient flip-chip
BGA packages. These flip-chip packages range in pin-count from the smaller 23 x 23 mm
SFVA784 to the 55 x 55 mm FLGA2892. This suite of packages is used to address the various
power requirements of the UltraScale and UltraScale+ devices. UltraScale devices are
implemented in the 20 nm process technology. UltraScale+ devices are implemented in the
16 nm process technology.
Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in a
user application is not known to the component supplier. Therefore, it remains a challenge
for Xilinx to predict the power requirements of a given FPGA when it leaves the factory.
Accurate estimates are obtained when the board design takes shape. For this purpose,
Xilinx offers and supports a suite of integrated device power analysis tools to help users
quickly and accurately estimate their design power requirements. UltraScale and
UltraScale+ devices are supported similarly to previous FPGA products. The uncertainty of
design power requirements makes it difficult to apply canned thermal solutions to fit all
users. Therefore, Xilinx devices do not come with preset thermal solutions. Your design
operating conditions dictate the appropriate solution.
Thermal Resistance Data
Table 9-1 shows the thermal resistance data for UltraScale and UltraScale+ devices
(grouped in the packages offered). The data includes junction-to-ambient in still air,
junction-to-case, and junction-to-board data based on standard JEDEC four-layer
measurements.
IMPORTANT: The data in Table 9-1 is for device/package comparison purposes only. Attempts to
recreate this data are only valid using the transient 2-phase measurement techniques outlined in
JESD51-14.
TIP: The thermal data query for all available devices by package is available on the Xilinx website:
www.xilinx.com/cgi-bin/thermal/thermal.pl.
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Chapter 9: Thermal Specifications
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC, and the third digit in the package name is Q (for example: FFQA1156).
Refer to the XC version of these packages for their thermal resistance data and thermal models.
Table 9-1: Thermal Resistance Data
Package Package
Body Size Devices θJB
(°C/W)(2)
θJC
(°C/W)(2)
θJA
(°C/W)(2)
θJA-Effective (°C/W)(1)(2)
@250 LFM @500 LFM @750 LFM
Kintex UltraScale Devices
FBVA676 27 x 27 XCKU035 2.4 0.03 11.7 7.9 6.6 6.2
XCKU040 2.4 0.03 11.7 7.9 6.6 6.2
RBA676 27 x 27 XQKU040 3.2 0.26 12.4 8.3 6.9 6.5
SFVA784 23 x 23 XCKU035 2.0 0.21 13.1 9.4 7.9 7.3
XCKU040 2.0 0.21 13.1 9.4 7.9 7.3
FBVA900 31 x 31 XCKU035 2.5 0.03 10.5 6.8 5.7 5.3
XCKU040 2.5 0.03 10.5 6.8 5.7 5.3
FFVA1156 35 x 35
XCKU025 2.5 0.21 9.5 5.9 5.0 4.6
XCKU035 2.5 0.21 9.5 5.9 5.0 4.6
XCKU040 2.5 0.21 9.5 5.9 5.0 4.6
XCKU060 1.9 0.15 8.9 5.7 4.7 4.5
XCKU095 1.7 0.10 8.8 5.6 4.7 4.4
RFA1156 35 x 35
XQKU040 3.0 0.26 9.9 6.1 5.1 4.8
XQKU060 2.6 0.18 9.6 6.0 5.0 4.7
XQKU095 2.3 0.12 9.3 5.9 4.9 4.6
FFVA1517 40 x 40 XCKU060 1.9 0.15 7.9 4.8 4.1 3.8
FLVA1517 40 x 40 XCKU085 1.7 0.10 7.8 4.8 4.0 3.8
XCKU115 1.7 0.10 7.8 4.8 4.0 3.8
FFVC1517 40 x 40 XCKU095 1.7 0.10 7.8 4.8 4.0 3.8
FLVD1517 40 x 40 XCKU115 1.7 0.10 7.8 4.8 4.0 3.8
RLD1517 40 x 40 XQKU115 2.1 0.10 7.4 4.3 3.6 3.9
FFVB1760 42.5 x 42.5 XCKU095 1.7 0.10 7.4 4.5 3.7 3.5
FLVB1760 42.5 x 42.5 XCKU085 1.7 0.10 7.4 4.4 3.7 3.5
XCKU115 1.7 0.10 7.4 4.4 3.7 3.5
FLVD1924 45 x 45 XCKU115 1.7 0.10 7.0 4.2 3.5 3.3
FLVF1924 45 x 45 XCKU085 1.7 0.10 7.0 4.2 3.5 3.3
XCKU115 1.7 0.10 7.0 4.2 3.5 3.3
RLF1924 45 x 45 XQKU115 2.1 0.10 7.4 4.3 3.6 3.4
FLVA2104 47.5 x 47.5 XCKU115 1.7 0.10 6.7 3.9 3.3 3.1
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Chapter 9: Thermal Specifications
FFVB2104 47.5 x 47.5 XCKU095 1.7 0.10 6.7 3.9 3.3 3.1
FLVB2104 47.5 x 47.5 XCKU115 1.7 0.10 6.7 3.9 3.3 3.1
Virtex UltraScale Devices
FFVC1517 40 x 40
XCVU065 1.7 0.18 7.8 4.8 4.0 3.8
XCVU080 1.7 0.10 7.8 4.8 4.0 3.8
XCVU095 1.7 0.10 7.8 4.8 4.0 3.8
FFVD1517 40 x 40 XCVU080 1.7 0.10 7.8 4.8 4.0 3.8
XCVU095 1.7 0.10 7.8 4.8 4.0 3.8
FLVD1517 40 x 40 XCVU125 1.6 0.09 7.7 4.7 4.0 3.7
FFVB1760 42.5 x 42.5 XCVU080 1.7 0.10 7.4 4.5 3.7 3.5
XCVU095 1.7 0.10 7.4 4.5 3.7 3.5
FLVB1760 42.5 x 42.5 XCVU125 1.7 0.09 7.4 4.4 3.7 3.5
FFVA2104 47.5 x 47.5 XCVU080 1.7 0.10 6.7 3.9 3.3 3.1
XCVU095 1.7 0.10 6.7 3.9 3.3 3.1
FLVA2104 47.5 x 47.5 XCVU125 1.8 0.09 6.8 3.9 3.3 3.1
FFVB2104 47.5 x 47.5 XCVU080 1.7 0.10 6.7 3.9 3.3 3.1
XCVU095 1.7 0.10 6.7 3.9 3.3 3.1
FLVB2104 47.5 x 47.5 XCVU125 1.8 0.09 6.8 3.9 3.3 3.1
FLGB2104 47.5 x 47.5 XCVU160 1.5 0.06 6.5 3.8 3.2 3.0
XCVU190 1.5 0.06 6.5 3.8 3.2 3.0
FFVC2104 47.5 x 47.5 XCVU095 1.7 0.10 6.7 3.9 3.3 3.1
FLVC2104 47.5 x 47.5 XCVU125 1.8 0.09 6.8 3.9 3.3 3.1
FLGC2104 47.5 x 47.5 XCVU160 1.5 0.06 6.5 3.8 3.2 3.0
XCVU190 1.5 0.06 6.5 3.8 3.2 3.0
FLGB2377 50 x 50 XCVU440 1.4 0.05 6.2 3.6 3.0 2.8
FLGA2577 52.5 x 52.5 XCVU190 1.4 0.06 5.9 3.4 2.8 2.7
FLGA2892 55 x 55 XCVU440 1.5 0.04 5.7 3.2 2.7 2.5
Table 9-1: Thermal Resistance Data (Cont’d)
Package Package
Body Size Devices θJB
(°C/W)(2)
θJC
(°C/W)(2)
θJA
(°C/W)(2)
θJA-Effective (°C/W)(1)(2)
@250 LFM @500 LFM @750 LFM
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Chapter 9: Thermal Specifications
Kintex UltraScale+ Devices
FFVA676 27 x 27 XCKU3P 2.07 0.25 10.2 7.1 6.0 5.6
XCKU5P 2.07 0.25 10.2 7.1 6.0 5.6
FFVB676 27 x 27 XCKU3P 2.07 0.25 10.2 7.1 6.0 5.6
XCKU5P 2.07 0.25 10.2 7.1 6.0 5.6
FFRB676 27 x 27 XQKU5P 2.26 0.27 10.4 7.3 6.1 5.7
SFVB784 23 x 23 XCKU3P 2.06 0.25 11.9 8.7 7.3 6.9
XCKU5P 2.06 0.25 11.9 8.7 7.3 6.9
SFRB784 23 x 23 XQKU5P
FFVD900 31 x 31
XCKU3P 2.22 0.26 9.0 6.1 5.1 4.8
XCKU5P 2.22 0.26 9.0 6.1 5.1 4.8
XCKU11P 1.83 0.14 8.7 5.9 4.9 4.6
FFVE900 31 x 31 XCKU9P 2.33 0.25 9.2 6.1 5.1 4.9
XCKU13P 2.25 0.18 9.1 6.1 5.1 4.8
FFVA1156 35 x 35 XCKU11P 1.97 0.14 7.8 5.1 4.2 4.0
XCKU15P 1.69 0.10 7.6 5.0 4.1 3.9
FFRA1156 35 x 35 XQKU15P 1.92 0.11 7.7 5.1 4.2 4.0
FFVE1517 40 x 40 XCKU11P 1.96 0.14 6.8 4.3 3.6 3.4
XCKU15P 1.76 0.10 6.6 4.2 3.5 3.4
FFRE1517 40 x 40 XQKU15P 1.90 0.11 6.8 4.3 3.5 3.4
FFVA1760 42.5 x 42.5 XCKU15P 1.77 0.10 6.3 3.9 3.2 3.1
FFVE1760 42.5 x 42.5 XCKU15P 1.77 0.10 6.3 3.9 3.2 3.1
Virtex UltraScale+ Devices
FFVC1517 40 x 40 XCVU3P 1.82 0.14 6.7 4.2 3.5 3.4
FFRC1517 40 x 40 XQVU3P 1.95 0.14 6.8 4.3 3.6 3.4
FLGF1924 45 x 45 XCVU11P 1.48 0.07 5.7 3.5 2.9 2.8
FSVH1924 45 x 45 XCVU31P 2.10 0.04 6.2 3.8 3.1 3.0
FLVA2104 47.5 x 47.5 XCVU5P 1.69 0.09 5.5 3.3 2.8 2.7
XCVU7P 1.69 0.09 5.5 3.3 2.8 2.7
FLRA2104 47.5 x 47.5 XQVU7P
Table 9-1: Thermal Resistance Data (Cont’d)
Package Package
Body Size Devices θJB
(°C/W)(2)
θJC
(°C/W)(2)
θJA
(°C/W)(2)
θJA-Effective (°C/W)(1)(2)
@250 LFM @500 LFM @750 LFM
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Chapter 9: Thermal Specifications
FLGA2104 47.5 x 47.5 XCVU9P 1.45 0.06 5.4 3.3 2.7 2.6
FHGA2104 52.5 x 52.5 XCVU13P 1.45 0.05 5.4 3.3 2.7 2.6
FLVB2104 47.5 x 47.5 XCVU5P 1.69 0.09 5.5 3.3 2.8 2.7
XCVU7P 1.69 0.09 5.5 3.3 2.8 2.7
FLRB2104 47.5 x 47.5 XQVU7P
FLGB2104 47.5 x 47.5 XCVU9P 1.45 0.06 5.4 3.3 2.7 2.6
XCVU11P 1.53 0.07 5.5 3.3 2.7 2.6
FHGB2104 52.5 x 52.5 XCVU13P 1.45 0.05 5.4 3.3 2.7 2.6
FLVC2104 47.5 x 47.5 XCVU5P 1.69 0.09 5.5 3.3 2.8 2.7
XCVU7P 1.69 0.09 5.5 3.3 2.8 2.7
FLGC2104 47.5 x 47.5 XCVU9P 1.45 0.06 5.4 3.3 2.7 2.6
XCVU11P 1.53 0.07 5.5 3.3 2.7 2.6
FLRC2104 47.5 x 47.5 XQVU11P
FHGC2104 52.5 x 52.5 XCVU13P 1.45 0.05 5.4 3.3 2.7 2.6
FIGD2104 52.5 x 52.5
XCVU13P 1.54 0.01 7.6 4.4 3.6 3.3
XCVU27P 1.54 0.01 7.6 4.4 3.6 3.3
XCVU29P 1.54 0.01 7.6 4.4 3.6 3.3
FSGD2104 47.5 x 47.5 XCVU9P 1.66 0.01 7.8 4.8 3.9 3.5
XCVU11P 1.63 0.01 7.9 4.9 4.0 3.7
FSVH2104 47.5 x 47.5 XCVU33P 2.10 0.03 5.9 3.5 2.9 2.8
XCVU35P 1.78 0.02 5.6 3.4 2.8 2.7
FLGA2577 52.5 x 52.5
XCVU9P 1.61 0.06 5.0 2.9 2.4 2.3
XCVU11P 1.70 0.07 5.0 2.9 2.5 2.4
XCVU13P 1.63 0.05 5.0 2.9 2.4 2.4
FSGA2577 52.5 x 52.5 XCVU13P 1.61 0.01 7.6 4.4 3.6 3.3
FSGA2577 52.5 x 52.5 XCVU27P 1.61 0.01 7.6 4.4 3.6 3.3
XCVU29P 1.61 0.01 7.6 4.4 3.6 3.3
FSVH2892 55 x 55 XCVU35P 1.91 0.02 4.9 2.9 2.4 2.3
XCVU37P 1.72 0.01 4.8 2.8 2.2 2.2
Notes:
1. All θJA-Effective values assume no heat sink and include thermal dissipation through a standard JEDEC four-layer board. The
Xilinx power estimation tools (Vivado® Power Analysis and Xilinx Power Estimator), which require detailed board dimensions
and layer counts, are useful for deriving more precise θJA-Effective values.
2. This data is for device/package comparison purposes only. Attempts to recreate this data are only valid using the transient
2-phase measurement techniques outlined in JESD51-14.
Table 9-1: Thermal Resistance Data (Cont’d)
Package Package
Body Size Devices θJB
(°C/W)(2)
θJC
(°C/W)(2)
θJA
(°C/W)(2)
θJA-Effective (°C/W)(1)(2)
@250 LFM @500 LFM @750 LFM
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Chapter 9: Thermal Specifications
Support for Thermal Models
Table 9-1 provides the traditional thermal resistance data for UltraScale and UltraScale+
devices. These resistances are measured using a prescribed JEDEC standard that might not
necessarily reflect your actual board conditions and environment. The quoted θJA and θJC
numbers are environmentally dependent, and JEDEC has traditionally recommended that
these be used with that awareness. For more accurate junction temperature prediction,
these might not be enough, and a system-level thermal simulation might be required.
Though Xilinx continues to support these figure of merit data, for UltraScale and
UltraScale+ devices, boundary conditions independent thermal resistor network (Delphi)
models are offered for all UltraScale and UltraScale+ devices. These compact models seek
to capture the thermal behavior of the packages more accurately at predetermined critical
points (junction, case, top, leads, and so on) with the reduced set of nodes as illustrated in
Figure 9-1.
Unlike a full 3D model, these are computationally efficient and work well in an integrated
system simulation environment. Delphi models are available for download on the Xilinx
website (under the Device Model tab).
RECOMMENDED: Xilinx recommends use of the Delphi thermal model during thermal modeling of a
package. The Delphi thermal model includes consideration of the thermal interface material
parameters and the manufacture variation on the thermal solution. Examples of manufacture
variations include the tolerance in airflow from a fan, the tolerance on performance of the heat pipe
and vapor chamber, and the manufacture variation of the attachment of fins to the heat-sink base and
the flatness of the surface.
X-Ref Target - Figure 9-1
Figure 9-1: Thermal Model Topologies
TI
Junction
BI BO
TO
SIDE
UG575_c9_01_081914
DELPHI BCI-CTM Topology for
Flip-Chip BGA
Junction
Rjc
Rjb
Two Resistor Model
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Chapter 10
Thermal Management Strategy
Introduction
As described in this section, Xilinx relies on a multi-pronged approach to consuming less
power and dissipating heat for systems using UltraScale™ and UltraScale+™ devices.
Flip-Chip Packages
UltraScale and UltraScale+ devices are offered in flip-chip BGA packages, which present a
low thermal path. With the exception of the bare-die packages, the flip-chip BGA packages
incorporate a heat spreader with an additional thermal interface material (TIM), as shown in
Figure 10-1.
Materials with better thermal conductivity and consistent process deliver low thermal
resistance to the heat spreader.
A parallel effort to ensure optimized package electrical return paths produces the added
benefit of enhanced power and ground plane arrangement in the packages. A boost in
copper density on the planes improves the overall thermal conductivity through the
laminate. In addition, the extra dense and distributed via fields in the package increase the
vertical thermal conductivity.
X-Ref Target - Figure 10-1
Figure 10-1: Heat Spreader with Thermal Interface Material
Die
Lid-Heat Spreader
Substrate
Thermal Interface Material (TIM)
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Chapter 10: Thermal Management Strategy
System Level Heat Sink Solutions
To complete a comprehensive thermal management strategy, an overall thermal budget
that includes custom or OEM heat-sink solutions depends on the physical and mechanical
constraints of the system. A heat-sink solution, managed by the system-level designer,
should be tailored to the design and specific system constraints. This includes
understanding the inherent device capabilities for delivering heat to the surface.
By considering the system's physical, mechanical, and environmental constraints, the
overall thermal budget is maintained and does not exceed the device’s maximum operating
temperature. The heat sink is an integral part of the thermal management solution to
maintain a safe operating temperature. As a result, the system-level designer must be aware
of the following:
• For lidless packages, the nominal stiffener height can be different from the height of
the die. Therefore, the heat sink must have an island to contact the die.
• Especially for lidless packages, Xilinx advises against direct use of the θJC parameters
(see Table 9-1) to determine the thermal performance of the device in your application.
The calculation of these parameters are done in accordance with the JEDEC standard
JESD51 where system parameters differ greatly from most applications. Instead, run
thermal simulations of the system in worst-case environmental conditions using Delphi
thermal models, which more accurately represent the device thermal performance
under all boundary conditions.
• Consider the mechanical specifications of the package as well as the selection of the
thermal interface between the die and the thermal management solution to ensure the
lowest thermal contact resistance.
• The total thermal contact of the thermal interface material is determined based on
parameters from the thermal interface supplier’s data sheet.
• See the applied pressure recommendation on page 428. Lower pressure runs the risk of
poor thermal contact and higher pressure runs the risk of damaging the device;
therefore, strict control of pressure is required.
• Consider all uncertainties in thermal modeling, including manufacturing variations
from the thermal solutions (for example, fan airflow tolerance, heat pipe or vapor
chamber performance tolerance, variation of the attachment of fins to heat sink base,
and surface flatness).
Thermal Interface Material
When installing heat sinks for UltraScale or UltraScale+ devices, a suitable thermal interface
material must be used. This thermal material significantly aids the transfer of heat from the
component to the heat sink.
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Chapter 10: Thermal Management Strategy
For bare-die flip-chip BGAs, the surface of the silicon contacts the heat sink. For lidded
flip-chip BGAs, the lid contacts the heat sink. The surface size of the bare-die flip-chip BGA
and lidded flip-chip BGAs are different. Xilinx recommends a different type of thermal
material for long-term use with each type of flip-chip BGAs package.
Thermal interface material is needed because even the largest heat sink and fan cannot
effectively cool an UltraScale or UltraScale+ device unless there is good physical contact
between the base of the heat sink and the top of the UltraScale or UltraScale+ device. The
surfaces of both the heat sink and the UltraScale or UltraScale+ device silicon are not
absolutely smooth. This surface roughness is observed when examined at a microscopic
level. Because surface roughness reduces the effective contact area, attaching a heat sink
without a thermal interface material is not sufficient due to inadequate surface contact.
A thermal interface material such as phase-change material, thermal grease, or thermal
pads fills these gaps and allows effective transference of heat between the UltraScale or
UltraScale+ device die and the heat sink.
The selection of the thermal interface material between the package and the thermal
management solution is critical to ensure the lowest thermal contact resistance. Therefore,
the following parameters must be considered.
1. The flatness of the lid and the flatness of the contact surface of the thermal solution.
2. The applied pressure of the thermal solution on the package, which must be within the
allowable maximum pressure that can be applied on the package.
3. The total thermal contact of the thermal interface material. This value is determined
based on the parameters in step 1 and step 2, which are published in the data sheet of
the thermal interface supplier.
Types of TIM
There are many type of TIM available for sale. The most commonly used thermal interface
materials are listed.
• Thermal grease
• Thermal pads
• Phase-change material
• Thermal paste
• Thermal adhesives
• Thermal tape
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Chapter 10: Thermal Management Strategy
Guidelines for Thermal Interface Materials
Five factors affect the choice, use, and performance of the interface material used between
the processor and the heat sink:
•Thermal Conductivity of the Material
•Electrical Conductivity of the Material
•Spreading Characteristics of the Material
•Long-Term Stability and Reliability of the Material
•Ease of Application
•Applied Pressure from Heat Sink to the Package via Thermal Interface Materials
Thermal Conductivity of the Material
Thermal conductivity is the quantified ability of any material to transfer heat. The thermal
conductivity of the interface material has a significant impact on its thermal performance.
The higher the thermal conductivity, the more efficient the material is at transferring heat.
Materials that have a lower thermal conductivity are less efficient at transferring heat,
causing a higher temperature differential to exist across the interface. To overcome this less
efficient heat transfer, a better cooling solution (typically, a more costly solution) must be
used to achieve the desired heat dissipation.
Electrical Conductivity of the Material
Some metal-based TIM compounds are electrically conductive. Ceramic-based compounds
are typically not electrically conductive. Manufacturers produce metal-based compounds
with low-electrical conductivity, but some of these materials are not completely electrically
inert. Metal-based thermal compounds are not hazardous to an UltraScale or UltraScale+
device die itself, but other elements on an UltraScale or UltraScale+ device or the
motherboard can be at risk if they become contaminated by the compound. For this reason,
Xilinx does not recommend the use of electrically conductive thermal interface material.
Spreading Characteristics of the Material
The spreading characteristics of the thermal interface material determines its ability, under
the pressure of the mounted heat sink, to spread and fill in or eliminate the air gaps
between the UltraScale or UltraScale+ device and the heat sink. Because air is a very poor
thermal conductor, the more completely the interface material fills the gaps, the greater the
heat transference.
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Chapter 10: Thermal Management Strategy
Long-Term Stability and Reliability of the Material
The long-term stability and reliability of the thermal interface material is described as the
ability to provide a sufficient thermal conductance even after an extended time or
extensive. Low-quality compounds can harden or leak out over time (the pump-out effect),
leading to overheating or premature failure of the UltraScale or UltraScale+ device.
High-quality compounds provide a stable and reliable thermal interface material
throughout the lifetime of the device. Thermal greases with higher viscosities are typically
more resistant to pump out effects on bare-die devices.
Ease of Application
A spreadable thermal grease requires the surface mount supplier to carefully use the
appropriate amount of material. Too much or too little material can cause problems. The
thermal pad is a fixed size and is therefore easier to apply in a consistent manner.
Applied Pressure from Heat Sink to the Package via Thermal Interface
Materials
RECOMMENDED: Xilinx recommends that the applied pressure on the package be in the range of 20 to
50 psi for optimum performance of the thermal interface material (TIM) between the package and the
heat sink. Thermocouples should not be present between the package and the heat sink, as their
presence will degrade the thermal contact and result in incorrect thermal measurements. The best
practice is to select the appropriate pressure (in the 20 to 50 psi range) for the optimum thermal
contact performance between the package and the thermal system solution, and the mechanical
integrity of the package (with the thermal solution to pass all mechanical stress and vibration
qualification tests).
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Chapter 10: Thermal Management Strategy
RECOMMENDED: Xilinx recommends using dynamic mounting around the four corners of the device
package. On the PCB, use a bracket clip as part of the heat sink attachment to provide mechanical
package support. See Figure 10-2.
Heat Sink Removal
When removing or reworking heat sinks, the phase-change material residue must be
removed from the surface of the die. Laird Technologies, Inc. provides the following
guidance for complete removal of the phase-change material from the component.
X-Ref Target - Figure 10-2
Figure 10-2: Dynamic Mounting and Bracket Clips on Heat Sink Attachment
PKG
Heat SinkHS Base
X15431-111316
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Chapter 10: Thermal Management Strategy
Instructions for Removal of Phase-change Material
1. Separate the Components
2. Scrape Away Thick Residue
3. Clean Remaining Residue with Solvent
4. Working with Laird Material
Separate the Components
At room temperature, if possible, use a back and forth twisting motion to break the bond
between the phase-change thermal interface material and mated components (i.e., heat
sink and FPGA). See Figure 10-3.
For smaller components (typically 15 mm x 15 mm or less), the bond usually breaks free
easily at room temperature. For larger components, in situations where minimal movement
is available, or if using fragile components, heat the component (preferred) or heat sink to
about 40°C–60°C before removal.
The guideline is 40°C–60°C, however, you might find that for your application, heating to
35°C is adequate. You might prefer to heat to 70°C which makes the phase-change thermal
interface material very soft and the components can be easily separated.
Scrape Away Thick Residue
For a faster clean-up once components are separated, scrape away any large residual
material amounts with a plastic spatula or a wooden tongue depressor. A clean dry rag can
be used to wipe away excess material.
X-Ref Target - Figure 10-3
Figure 10-3: Breaking the Bond between Thermal Interface Material and Mated Components
Phase Change
Thermal Interface
Material
Heat Sink
FPGA
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Chapter 10: Thermal Management Strategy
Clean Remaining Residue with Solvent
Using a clean cloth/wipe, wet it with your choice of solvent (see the following list) and wipe
away any remaining residue.
• Toluene (easiest)
• Acetone (very good)
• Isoparaffinic hydrocarbon: Isopar, Soltrol (trade names) (very good)
•Isopropyl alcohol (OK)
Working with Laird Material
Safe handling, disposal, and first-aid measures for working with phase-change material are
included in the Laird Technologies material safety data sheet (MSDS). Read the MSDS
before using or handling. See the Laird Technologies, Inc. website, www.lairdtech.com.
Measurement Debug
When performing in-system thermal testing, to ensure accurate data and not incur damage
to the device, do not place a thermocouple in between the device and the heat sink. On the
extreme side, it might cause additional mechanical and/or thermal stress to the device,
leading to damage. Even if damage does not occur, it often leads to a thicker and or uneven
thermal interface material thickness, leading to a thermal performance difference from a
system without a thermocouple. To obtain the device temperature, use the System Monitor
as a non-invasive means to get accurate device measurements while debugging the system.
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Chapter 11
Heat Sink Guidelines for Bare-die
Flip-Chip Packages
Heat Sink Attachments for Bare-die FB Packages
Heat sinks can be attached to the package in multiple ways. For heat to dissipate effectively,
the advantages and disadvantages of each heat sink attachment method must be
considered. Factors influencing the selection of the heat sink attachment method include
the package type, contact area of the heat source, and the heat sink type.
Silicon and Decoupling Capacitors Height Consideration
When designing heat sink attachments for bare-die flip-chip BGA packages, the height of
the die above the substrate and also the height of decoupling capacitors must be
considered (Figure 11-1). This is to prevent electrical shorting between the heat sink (metal)
and the decoupling capacitors.
X-Ref Target - Figure 11-1
Figure 11-1: Cross Section of Bare-die Flip-chip BGA
Silicon Underfill Substrate
Decoupling
Capacitor
UG575_c11_01_102213
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Chapter 11: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Types of Heat Sink Attachments
There are six main methods for heat sink attachment. Table 11-1 lists their advantages and
disadvantages.
•Thermal tape
•Thermally conductive adhesive or glue
•Wire form Z-clips
•Plastic clip-ons
•Threaded stand-offs (PEMs) and compression springs
•Push-pins and compression springs
Table 11-1: Heat Sink Attachment Methods
Attachment
Method Advantages Disadvantages
Thermal tape • Generally easy to attach and is inexpensive.
• Lowest cost approach for aluminum heat
sink attachment.
• No additional space required on the PCB.
• The surfaces of the heat sink and the chip
must be very clean to allow the tape to
bond correctly.
• Because of the small contact area, the tape
might not provide sufficient bond strength.
• Tape is a moderate to low thermal
conductor that could affect the thermal
performance.
Thermally
conductive
adhesive or glue
• Outstanding mechanical adhesion.
• Fairly inexpensive, costs a little more than
tape.
• No additional space required on the PCB.
• Adhesive application process is
challenging and it is difficult to control the
amount of adhesive to use.
• Difficult to rework.
• Because of the small contact area, the
adhesive might not provide sufficient bond
strength.
Wire form Z-clips • It provides a strong and secure mechanical
attachment. In environments that require
shock and vibration testing, this type of
strong mechanical attachment is necessary.
• Easy to apply and remove. Does not cause
the semiconductors to be destroyed (epoxy
and occasionally tape can destroy the
device).
• It applies a preload onto the thermal
interface material (TIM). Pre-loads actually
improve thermal performance.
• Requires additional space on the PCB for
anchor locations.
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Chapter 11: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Heat Sink Attachment
Component Pick-up Tool Consideration
For pick-and-place machines to place bare-die flip-chip BGAs onto PCBs, Xilinx
recommends using soft tips or suction cups for the nozzles. This prevents chipping,
scratching, or even cracking of the bare die (Figure 11-2).
Plastic clip-ons • Suitable for designs where space on the
PCB is limited.
• Easy to rework by allowing heat sinks to be
easily removed and reapplied without
damaging the PCB board.
• Can provide a strong enough mechanical
attachment to pass shock and vibration
test.
• Needs a keep out area around the silicon
devices to use the clip.
• Caution is required when installing or
removing clip-ons because localized stress
can damage the solder balls or chip
substrate.
Threaded
stand-offs
(PEMs) and
compression
springs
• Provides stable attachments to heat source
and transfers load to the PCB, backing
plate, or chassis.
• Suitable for high mass heat sinks.
• Allows for tight control over mounting
force and load placed on chip and solder
balls.
• Holes are required in the PCB taking
valuable space that can be used for trace
lines.
• Tends to be expensive, especially since
holes need to be drilled or predrilled onto
the PCB board to use stand-offs.
Push-pins and
compression
springs
• Provides a stable attachment to a heat
source and transfers load to the PCB.
• Allows for tight control over mounting
force and load placed on chip and solder
balls.
• Requires additional space on the PCB for
push-pin locations.
Table 11-1: Heat Sink Attachment Methods (Cont’d)
Attachment
Method Advantages Disadvantages
X-Ref Target - Figure 11-2
Figure 11-2: Recommended Method For Using Pick-up Tools
UG575_c11_02_102213
Silicon Substrate
Metal
Tip
Nozzle
Metal Pick Up Tip Nozzle with Soft Tips or
Suction Cups is Preferred
Soft Tips
Decoupling
Capacitor
Preferred
Silicon Substrate
Metal
Tip
Nozzle
Metal Pick Up Tip Nozzle Can Damage
the Exposed Silicon
Decoupling
Capacitor
Incorrect Pickup Method
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Chapter 11: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Heat Sink Attachment Process Considerations
After the component is placed onto the PCBs, when attaching a heat sink to the bare-die
package, the factors in Table 11-2 must be carefully considered (see Figure 11-3).
Table 11-2: Heat Sink Attachment Considerations
Consideration(s) Effect(s) Recommendation(s)
In heat sink attach process,
what factors can cause
damage to the exposed die
and passive capacitors?
• Uneven heat sink placement
• Uneven TIM thickness
• Uneven force applied when
placing heat sink placement
• Even heat sink placement
• Even TIM thickness
• Even force applied when placing heat sink
placement
Does the heat sink tilt or tip
the post attachment?
Uneven heat sink placement will
damage the silicon and can
cause field failures.
• Careful handling not to contact the heat
sink with the post attachment.
• Use a fixture to hold the heat sink in place
with post attachment until it is glued to
the silicon.
X-Ref Target - Fig ure 11-3
Figure 11-3: Recommended Application of Heat Sink
UG575_c11_03_110513
Silicon
Substrate
Decoupling
Capacitor
Even ForceEven Force
Silicon
Heat Sink
Mother Board
Substrate
Even ForceEven Force
Preferred
Preferred
Incorrect Alignment
Silicon
Substrate
Decoupling
Capacitor
Incorrect Force
Silicon
Substrate
Decoupling
Capacitor
Preferred application of heat sink
1. Heat sink is aligned parallel to silicon
2. Even bond line thickness of TIM
3. Even compressive force is applied on all sides
Improper application of heat sink can cause damage
to heat sink
1. Heat sink is not aligned parallel to silicon
2. Uneven bond line thickness of TIM
3. Uneven force is applied
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Chapter 11: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Standard Heat Sink Attach Process with Thermal Conductive Adhesive
Prior to attaching the heat sink, the UltraScale or UltraScale+ device needs be surface
mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
2. Thermoset material (electrically non-conductive) is applied over the backside surface of
silicon in a pattern using automated dispensing equipment. Automated dispensers are
often used to provide a stable process speed at a relatively low cost. The optimum
dispensing pattern needs to be determined by the SMT supplier.
Note: Minimal volume coverage of the backside of the silicon can result in non-optimum heat
transfer.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the adhesive spreads to cover the backside silicon. A force transducer is
normally used to measure and limit the placement force.
4. The epoxy is cured with heat at a defined time.
Note: The epoxy curing temperature and time is based on manufacturer’s specifications.
Standard Heat Sink Attach Process with Thermal Adhesive Tape
Prior to attaching the heat sink, the UltraScale or UltraScale+ device needs be surface
mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
2. Thermal adhesive tape cut to the size of the heat sink is applied on the underside of the
heat sink at a modest angle with the use of a squeegee rubber roller. Apply pressure to
help reduce the possibility of air entrapment under the tape during application.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the thermal adhesive tape is glued to the backside of the silicon. A force
transducer is normally used to measure and limit the placement force.
4. A uniform and constant pressure is applied uniformly over the heat sink and held for a
defined time.
Note: The thermal adhesive tape hold time is based on manufacturer’s specifications.
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Chapter 11: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Push-Pin and Shoulder Screw Heat Sink Attachment Process with Phase Change Material (PCM)
Application
Prior to attaching the heat sink, the UltraScale or UltraScale+ device needs be surface
mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
Note: The jig or fixture needs to account for the push pin depth of the heat sink.
2. PCM tape, cut to the size of the heat sink, is applied on the underside of the heat sink
at a modest angle with the use of a squeegee rubber roller. Apply pressure to help
reduce the possibility of air entrapment under the tape during application.
3. Using the push-pin tool, heat sinks are applied over the packages ensuring a pin locking
action with the PCB holes. The compression load from springs applies the appropriate
mounting pressure required for proper thermal interface material performance.
Note: Heat sinks must not tilt during installation. This process cannot be automated due to the
mechanical locking action which requires manual handling. The PCB drill hole tolerances need to
be close enough to eliminate any issues concerning the heat sink attachment.
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Chapter 12
Mechanical and Thermal Design
Guidelines for Lidless Flip-chip Packages
Introduction
This chapter discusses the challenges of thermal management including reducing device
thermal resistance and optimal power dissipation without an increase in junction
temperature. The lidless UltraScale+ FPGA packages target the largest devices while
allowing for cooler operation temperatures (up to 10°C) with the same power dissipation.
Precise mechanical design and component thermal management is vital for device and
system performance. This document presents the unique thermal and mechanical design
requirements for lidless devices.
Lidless Flip-Chip Packages
The Xilinx flip-chip BGA packages exhibit a low-resistance thermal path that adequately
cools devices. These packages incorporate a heat spreader lid with additional thermal
interface material (Figure 12-1).
X-Ref Target - Figure 12-1
Figure 12-1: Flip-Chip BGA Construction with Heat Spreader and Thermal Interface Material
Thermal Interface Material Heat Spreader Lid
BGA Construction
X18047-031918
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Chapter 12: Mechanical and Thermal Design Guidelines for Lidless Flip-chip Packages
Materials with high thermal conductivity and consistent process applications deliver low
thermal resistance up to the heat spreader. A parallel effort to ensure optimized package
electrical return paths produces an enhanced power and ground plane arrangement in the
package. A boost in copper density on the planes improves the overall thermal conductivity
through the laminate. The extra density and distribution via fields in the package also
increases the vertical thermal conductivity.
The lidless packages (Figure 12-2) offer the same package substrate design with electrical
and board thermal conductivity similar to the flip-chip BGA packages. However, removing
the lid (heat spreader) and the thermal interface material allows for direct contact between
the external heat sink and the die. This further reduces the thermal resistance and exhibits
improved thermal behaviors. The use of custom passive or active heat-sink designs is
facilitated by incorporating two-phase (heat pipe, vapor chamber, or even liquid) cooling
methods directly adjacent to the source of the dissipated heat on the die, which allows for
a more efficient means of removing the heat from the device. Consequently, the device can
operate at higher ambient temperatures while in area-constrained surroundings resulting in
operational power advantages.
A unique feature of lidless packages is the addition of a stiffener ring around the periphery
of the package substrate, providing additional package rigidity and helping to improve the
overall package coplanarity (flatness). It also serves as a guide for the heat sink solution
applied to the device. For examples, see Figure 4-45, Figure 4-46, and Figure 4-47.
In the lidless packages, capacitors can be placed in the area surrounding the die. Contact
with electrically conductive materials must be avoided because the die-side capacitors,
which are only slightly shorter than the die height, could be electrically conductive. Any
thermal and mechanical solution higher than the die must not interfere with the package
stiffener. Therefore, the thermal solution must have an island, see System Level Heat Sink
Solutions in Chapter 10.
For further guidelines on mechanical and thermal designs of lidless packages, refer to
XAPP1301: Mechanical and Thermal Design Guidelines for Lidless Flip-Chip Packages
Application Note [Ref 19].
X-Ref Target - Figure 12-2
Figure 12-2: Lidless Flip-Chip BGA Construction
X18048-031918
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Appendix A
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
property at all stages of the design cycle. Topics include design assistance, advisories, and
troubleshooting tips.
Documentation Navigator and Design Hubs
Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support
resources, which you can filter and search to find information. To open the Xilinx
Documentation Navigator (DocNav):
• From the Vivado® IDE, select Help > Documentation and Tutorials.
• On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other
topics, which you can use to learn key concepts and address frequently asked questions. To
access the Design Hubs:
• In the Xilinx Documentation Navigator, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on Documentation Navigator, see the Documentation Navigator page
on the Xilinx website.
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Appendix A: Additional Resources and Legal Notices
References
1. UltraScale Architecture and Product Overview (DS890)
2. XQ UltraScale Architecture Data Sheet Overview (DS895)
3. UltraScale device data sheets:
°Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)
°Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)
°Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
°Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923)
4. Zynq UltraScale+ MPSoC Packaging and Pinouts User Guide (UG1075)
5. UltraScale Architecture SelectIO Resources User Guide (UG571)
6. UltraScale Architecture Clocking Resources User Guide (UG572)
7. UltraScale Architecture Configuration User Guide (UG570)
8. UltraScale Architecture GTH Transceivers User Guide (UG576)
9. UltraScale Architecture GTY Transceivers User Guide (UG578)
10. UltraScale Architecture System Monitor User Guide (UG580)
11. UltraScale Architecture PCB and Pin Planning User Guide (UG583)
12. FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424)
13. UltraScale Architecture FPGAs Memory IP Product Guide (PG150)
14. UltraScale Devices Gen3 Integrated Block for PCI Express Product Guide (PG156)
15. UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)
16. Integrated Interlaken 150G Product Guide (PG169)
17. UltraScale Devices Integrated Block for 100G Ethernet Product Guide (PG165)
18. UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)
19. Mechanical and Thermal Design Guidelines for Lidless Flip-Chip Packages Application
Note (XAPP1301)
20. MDDS files: Click on this link to find the UltraScale and UltraScale+ FPGA Packaging
Specifications. In step 2 select the product category: FPGAs and 3D ICs. In step 3, select
the product type. In step 4, click on the package specifications selection to find the
available MDDS files.
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Appendix A: Additional Resources and Legal Notices
21. The following websites contain additional information on heat management and contact
information.
°Wakefield: www.wakefield-vette.com
°Aavid: www.aavid.com
°Advanced Thermal Solutions: www.qats.com
°Radian Thermal Products: www.radianheatsinks.com
°Thermo Cool: www.thermocoolcorp.com
°CTS: www.ctscorp.com
22. Refer to the following websites for interface material sources:
°Henkel: www.henkel.com
°Bergquist Company: www.bergquistcompany.com
°AOS Thermal Compound: www.aosco.com
°Chomerics: www.chomerics.com
°Kester: www.kester.com
23. Refer to the following websites for CFD tools Xilinx supports with thermal models.
°Mentor Flotherm: www.mentor.com/products/mechanical/flotherm/flotherm/
°ANSYS Icepak: www.ansys.com
24. Refer to the thermal device models on xilinx.com.
25. The following papers are referenced for more information on thermal modelling.
°Lemczyk, T.F., Mack, B., Culham, J.R. and Yovanovich, M.M., 1992, “Printed Circuit
Board Trace Thermal Analysis and Effective Conductivity”, ASME J. Electronic
Packaging, Vol. 114, pp. 413 - 419.50.
°Refai-Ahmed, G. and Karimanal, K., 2003, “Validation of Compact Conduction Models
of BGA Under Realistic Boundary,” J. of Components and Packaging Technology, Vol.
26, No. 3, pp. 610-615.
°Sansoucy, E, Refai-Ahmed, G., and Karimanal, K., 2002, “Thermal Characterization of
TBGA Package for an integration in Board Level Analysis,” Eighth Intersociety on
Thermal Conference Phenomena in Electronic Systems, San Diego., USA.
°Karimanal,K and Refai-Ahmed, G., and., 2002, “Validation of Compact Conduction
Models of BGA Under Realistic Boundary Conditions,” Eighth Intersociety on
Thermal Conference Phenomena in Electronic Systems, San Diego, USA.
°Karminal, K. and Refai-Ahmed, G., 2001, ``Compact conduction Model (CCM) of
Microelectronic Packages- A BGA Validation Study,'' APACK Conference on Advance
in Packaging, Singapore.
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Appendix A: Additional Resources and Legal Notices
Please Read: Important Legal Notices
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